blob: e9b8ad0c0b7f31cc7a77dbcee717074125a53909 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shaohui Xie085ac1c2016-09-07 17:56:14 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Shaohui Xie085ac1c2016-09-07 17:56:14 +08004 */
5
6#ifndef __LS1046AQDS_H__
7#define __LS1046AQDS_H__
8
9#include "ls1046a_common.h"
10
Shaohui Xie085ac1c2016-09-07 17:56:14 +080011/* Physical Memory Map */
Shaohui Xie085ac1c2016-09-07 17:56:14 +080012
Shaohui Xie085ac1c2016-09-07 17:56:14 +080013#define SPD_EEPROM_ADDRESS 0x51
Shaohui Xie085ac1c2016-09-07 17:56:14 +080014
Shaohui Xie085ac1c2016-09-07 17:56:14 +080015#ifdef CONFIG_DDR_ECC
Shaohui Xie085ac1c2016-09-07 17:56:14 +080016#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
17#endif
18
Shaohui Xie085ac1c2016-09-07 17:56:14 +080019#ifdef CONFIG_SYS_DPAA_FMAN
Shaohui Xie085ac1c2016-09-07 17:56:14 +080020#define RGMII_PHY1_ADDR 0x1
21#define RGMII_PHY2_ADDR 0x2
22#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
23#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
24#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
25#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
26/* PHY address on QSGMII riser card on slot 2 */
27#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
28#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
29#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
30#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
31#endif
32
Shaohui Xie085ac1c2016-09-07 17:56:14 +080033/* IFC */
34#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Shaohui Xie085ac1c2016-09-07 17:56:14 +080035/*
Tom Rini6a5dccc2022-11-16 13:10:41 -050036 * CFG_SYS_FLASH_BASE has the final address (core view)
37 * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
38 * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
Simon Glass72cc5382022-10-20 18:22:39 -060039 * CONFIG_TEXT_BASE is linked to 0x60000000 for booting
Shaohui Xie085ac1c2016-09-07 17:56:14 +080040 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050041#define CFG_SYS_FLASH_BASE 0x60000000
42#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
43#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
Shaohui Xie085ac1c2016-09-07 17:56:14 +080044#endif
45
Shaohui Xie56007a02016-10-28 14:24:02 +080046/* LPUART */
47#ifdef CONFIG_LPUART
Shaohui Xie56007a02016-10-28 14:24:02 +080048#define CFG_UART_MUX_MASK 0x6
49#define CFG_UART_MUX_SHIFT 1
50#define CFG_LPUART_EN 0x2
51#endif
52
Shaohui Xie085ac1c2016-09-07 17:56:14 +080053/*
54 * IFC Definitions
55 */
56#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Tom Rini6a5dccc2022-11-16 13:10:41 -050057#define CFG_SYS_NOR0_CSPR_EXT (0x0)
58#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +080059 CSPR_PORT_SIZE_16 | \
60 CSPR_MSEL_NOR | \
61 CSPR_V)
Tom Rini6a5dccc2022-11-16 13:10:41 -050062#define CFG_SYS_NOR1_CSPR_EXT (0x0)
63#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
Shaohui Xie085ac1c2016-09-07 17:56:14 +080064 + 0x8000000) | \
65 CSPR_PORT_SIZE_16 | \
66 CSPR_MSEL_NOR | \
67 CSPR_V)
Tom Rini7b577ba2022-11-16 13:10:25 -050068#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
Shaohui Xie085ac1c2016-09-07 17:56:14 +080069
Tom Rini7b577ba2022-11-16 13:10:25 -050070#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +080071 CSOR_NOR_TRHZ_80)
Tom Rini7b577ba2022-11-16 13:10:25 -050072#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +080073 FTIM0_NOR_TEADC(0x5) | \
York Sunebcd9d62017-12-11 08:39:05 -080074 FTIM0_NOR_TAVDS(0x6) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +080075 FTIM0_NOR_TEAHC(0x5))
Tom Rini7b577ba2022-11-16 13:10:25 -050076#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +080077 FTIM1_NOR_TRAD_NOR(0x1a) | \
78 FTIM1_NOR_TSEQRAD_NOR(0x13))
Tom Rini7b577ba2022-11-16 13:10:25 -050079#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
York Sunebcd9d62017-12-11 08:39:05 -080080 FTIM2_NOR_TCH(0x8) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +080081 FTIM2_NOR_TWPH(0xe) | \
82 FTIM2_NOR_TWP(0x1c))
Tom Rini7b577ba2022-11-16 13:10:25 -050083#define CFG_SYS_NOR_FTIM3 0
Shaohui Xie085ac1c2016-09-07 17:56:14 +080084
Tom Rini6a5dccc2022-11-16 13:10:41 -050085#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
86 CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
Shaohui Xie085ac1c2016-09-07 17:56:14 +080087
Tom Rini6a5dccc2022-11-16 13:10:41 -050088#define CFG_SYS_WRITE_SWAPPED_DATA
Shaohui Xie085ac1c2016-09-07 17:56:14 +080089
90/*
91 * NAND Flash Definitions
92 */
Shaohui Xie085ac1c2016-09-07 17:56:14 +080093
Tom Rinib4213492022-11-12 17:36:51 -050094#define CFG_SYS_NAND_BASE 0x7e800000
95#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
Shaohui Xie085ac1c2016-09-07 17:56:14 +080096
Tom Rinib4213492022-11-12 17:36:51 -050097#define CFG_SYS_NAND_CSPR_EXT (0x0)
Shaohui Xie085ac1c2016-09-07 17:56:14 +080098
Tom Rinib4213492022-11-12 17:36:51 -050099#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800100 | CSPR_PORT_SIZE_8 \
101 | CSPR_MSEL_NAND \
102 | CSPR_V)
Tom Rinib4213492022-11-12 17:36:51 -0500103#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
104#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800105 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
106 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
107 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
108 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
109 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
110 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
111
Tom Rinib4213492022-11-12 17:36:51 -0500112#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800113 FTIM0_NAND_TWP(0x18) | \
114 FTIM0_NAND_TWCHT(0x7) | \
115 FTIM0_NAND_TWH(0xa))
Tom Rinib4213492022-11-12 17:36:51 -0500116#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800117 FTIM1_NAND_TWBE(0x39) | \
118 FTIM1_NAND_TRR(0xe) | \
119 FTIM1_NAND_TRP(0x18))
Tom Rinib4213492022-11-12 17:36:51 -0500120#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800121 FTIM2_NAND_TREH(0xa) | \
122 FTIM2_NAND_TWHRE(0x1e))
Tom Rinib4213492022-11-12 17:36:51 -0500123#define CFG_SYS_NAND_FTIM3 0x0
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800124
Tom Rinib4213492022-11-12 17:36:51 -0500125#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800126#define CONFIG_MTD_NAND_VERIFY_WRITE
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800127#endif
128
129#ifdef CONFIG_NAND_BOOT
Tom Rinib4213492022-11-12 17:36:51 -0500130#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800131#endif
132
Rajesh Bhagat9af0a0b2018-11-05 18:02:40 +0000133#if defined(CONFIG_TFABOOT) || \
134 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800135#endif
136
137/*
138 * QIXIS Definitions
139 */
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800140
141#ifdef CONFIG_FSL_QIXIS
142#define QIXIS_BASE 0x7fb00000
143#define QIXIS_BASE_PHYS QIXIS_BASE
Tom Rini6a5dccc2022-11-16 13:10:41 -0500144#define CFG_SYS_I2C_FPGA_ADDR 0x66
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800145#define QIXIS_LBMAP_SWITCH 6
146#define QIXIS_LBMAP_MASK 0x0f
147#define QIXIS_LBMAP_SHIFT 0
148#define QIXIS_LBMAP_DFLTBANK 0x00
149#define QIXIS_LBMAP_ALTBANK 0x04
150#define QIXIS_LBMAP_NAND 0x09
151#define QIXIS_LBMAP_SD 0x00
152#define QIXIS_LBMAP_SD_QSPI 0xff
153#define QIXIS_LBMAP_QSPI 0xff
154#define QIXIS_RCW_SRC_NAND 0x110
155#define QIXIS_RCW_SRC_SD 0x040
156#define QIXIS_RCW_SRC_QSPI 0x045
157#define QIXIS_RST_CTL_RESET 0x41
158#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
159#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
160#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
161
Tom Rini6a5dccc2022-11-16 13:10:41 -0500162#define CFG_SYS_FPGA_CSPR_EXT (0x0)
163#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800164 CSPR_PORT_SIZE_8 | \
165 CSPR_MSEL_GPCM | \
166 CSPR_V)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500167#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
168#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800169 CSOR_NOR_NOR_MODE_AVD_NOR | \
170 CSOR_NOR_TRHZ_80)
171
172/*
173 * QIXIS Timing parameters for IFC GPCM
174 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500175#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800176 FTIM0_GPCM_TEADC(0x20) | \
177 FTIM0_GPCM_TEAHC(0x10))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500178#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800179 FTIM1_GPCM_TRAD(0x1f))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500180#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800181 FTIM2_GPCM_TCH(0x8) | \
182 FTIM2_GPCM_TWP(0xf0))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500183#define CFG_SYS_FPGA_FTIM3 0x0
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800184#endif
185
Rajesh Bhagat9af0a0b2018-11-05 18:02:40 +0000186#ifdef CONFIG_TFABOOT
Tom Rini6a5dccc2022-11-16 13:10:41 -0500187#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
188#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
189#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
190#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
191#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
192#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
193#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
194#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
195#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
196#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
197#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
198#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
199#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
200#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
201#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
202#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
203#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
204#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
205#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
206#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
207#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
208#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
209#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
210#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
211#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
212#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
213#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
214#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
215#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
216#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
217#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
218#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
Rajesh Bhagat9af0a0b2018-11-05 18:02:40 +0000219#else
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800220#ifdef CONFIG_NAND_BOOT
Tom Rini6a5dccc2022-11-16 13:10:41 -0500221#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
222#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
223#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
224#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
225#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
226#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
227#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
228#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
229#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
230#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
231#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
232#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
233#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
234#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
235#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
236#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
237#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
238#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
239#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
240#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
241#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
242#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
243#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
244#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
245#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
246#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
247#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
248#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
249#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
250#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
251#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
252#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800253#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500254#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
255#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
256#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
257#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
258#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
259#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
260#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
261#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
262#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
263#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
264#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
265#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
266#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
267#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
268#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
269#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
270#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
271#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
272#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
273#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
274#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
275#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
276#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
277#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
278#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
279#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
280#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
281#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
282#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
283#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
284#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
285#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800286#endif
Rajesh Bhagat9af0a0b2018-11-05 18:02:40 +0000287#endif
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800288
289/*
290 * I2C bus multiplexer
291 */
292#define I2C_MUX_PCA_ADDR_PRI 0x77
293#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
294#define I2C_RETIMER_ADDR 0x18
295#define I2C_MUX_CH_DEFAULT 0x8
296#define I2C_MUX_CH_CH7301 0xC
297#define I2C_MUX_CH5 0xD
298#define I2C_MUX_CH6 0xE
299#define I2C_MUX_CH7 0xF
300
301#define I2C_MUX_CH_VOL_MONITOR 0xa
302
303/* Voltage monitor on channel 2*/
304#define I2C_VOL_MONITOR_ADDR 0x40
305#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
306#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
307#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
308
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800309/* The lowest and highest voltage allowed for LS1046AQDS */
310#define VDD_MV_MIN 819
311#define VDD_MV_MAX 1212
312
313/*
314 * Miscellaneous configurable options
315 */
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800316
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800317/*
318 * Environment
319 */
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800320
Rajesh Bhagat9af0a0b2018-11-05 18:02:40 +0000321#ifdef CONFIG_TFABOOT
Biwen Li88dd2e82020-04-20 18:29:06 +0800322#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
323 "env exists secureboot && esbc_halt;;"
324#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
325 "env exists secureboot && esbc_halt;;"
326#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
327 "env exists secureboot && esbc_halt;;"
328#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
329 "env exists secureboot && esbc_halt;;"
Rajesh Bhagat9af0a0b2018-11-05 18:02:40 +0000330#endif
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800331
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800332#include <asm/fsl_secure_boot.h>
333
334#endif /* __LS1046AQDS_H__ */