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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Minkyu Kangfca30842009-10-01 17:20:28 +09002/*
3 * (C) Copyright 2009 SAMSUNG Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
5 * Heungjun Kim <riverful.kim@samsung.com>
6 *
7 * based on drivers/serial/s3c64xx.c
Minkyu Kangfca30842009-10-01 17:20:28 +09008 */
9
10#include <common.h>
Simon Glass767e7372014-09-14 16:36:17 -060011#include <dm.h>
12#include <errno.h>
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +053013#include <fdtdec.h>
Mike Frysingerf96c0422011-04-29 18:03:29 +000014#include <linux/compiler.h>
Minkyu Kangfca30842009-10-01 17:20:28 +090015#include <asm/io.h>
Minkyu Kangfca30842009-10-01 17:20:28 +090016#include <asm/arch/clk.h>
Simon Glass405fd142015-07-02 18:15:53 -060017#include <asm/arch/uart.h>
Minkyu Kangfca30842009-10-01 17:20:28 +090018#include <serial.h>
Thomas Abrahamc81fdbe2016-04-23 22:18:11 +053019#include <clk.h>
Minkyu Kangfca30842009-10-01 17:20:28 +090020
John Rigby0d21ed02010-12-20 18:27:51 -070021DECLARE_GLOBAL_DATA_PTR;
22
Simon Glass767e7372014-09-14 16:36:17 -060023#define RX_FIFO_COUNT_SHIFT 0
24#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
25#define RX_FIFO_FULL (1 << 8)
26#define TX_FIFO_COUNT_SHIFT 16
27#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
28#define TX_FIFO_FULL (1 << 24)
Akshay Saraswat63f10902013-03-21 20:33:04 +000029
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +053030/* Information about a serial port */
Simon Glass767e7372014-09-14 16:36:17 -060031struct s5p_serial_platdata {
32 struct s5p_uart *reg; /* address of registers in physical memory */
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +053033 u8 port_id; /* uart port number */
Simon Glass767e7372014-09-14 16:36:17 -060034};
Minkyu Kangfca30842009-10-01 17:20:28 +090035
36/*
Minkyu Kangbaa36882010-03-24 16:59:30 +090037 * The coefficient, used to calculate the baudrate on S5P UARTs is
Minkyu Kangfca30842009-10-01 17:20:28 +090038 * calculated as
39 * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
40 * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
41 * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
42 */
43static const int udivslot[] = {
44 0,
45 0x0080,
46 0x0808,
47 0x0888,
48 0x2222,
49 0x4924,
50 0x4a52,
51 0x54aa,
52 0x5555,
53 0xd555,
54 0xd5d5,
55 0xddd5,
56 0xdddd,
57 0xdfdd,
58 0xdfdf,
59 0xffdf,
60};
61
Simon Glass405fd142015-07-02 18:15:53 -060062static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
Minkyu Kangfca30842009-10-01 17:20:28 +090063{
Simon Glass405fd142015-07-02 18:15:53 -060064 /* enable FIFOs, auto clear Rx FIFO */
65 writel(0x3, &uart->ufcon);
66 writel(0, &uart->umcon);
67 /* 8N1 */
68 writel(0x3, &uart->ulcon);
69 /* No interrupts, no DMA, pure polling */
70 writel(0x245, &uart->ucon);
71}
72
73static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk,
74 int baudrate)
75{
Minkyu Kangfca30842009-10-01 17:20:28 +090076 u32 val;
77
Minkyu Kang36f25cf2010-08-24 15:51:55 +090078 val = uclk / baudrate;
Minkyu Kangfca30842009-10-01 17:20:28 +090079
80 writel(val / 16 - 1, &uart->ubrdiv);
Minkyu Kangbfa14242010-09-28 14:35:02 +090081
Minkyu Kangafae8aa2011-01-24 14:43:25 +090082 if (s5p_uart_divslot())
Minkyu Kangbfa14242010-09-28 14:35:02 +090083 writew(udivslot[val % 16], &uart->rest.slot);
84 else
85 writeb(val % 16, &uart->rest.value);
Simon Glass405fd142015-07-02 18:15:53 -060086}
87
Simon Glass8ed4bc12015-07-02 18:15:55 -060088#ifndef CONFIG_SPL_BUILD
Simon Glass405fd142015-07-02 18:15:53 -060089int s5p_serial_setbrg(struct udevice *dev, int baudrate)
90{
91 struct s5p_serial_platdata *plat = dev->platdata;
92 struct s5p_uart *const uart = plat->reg;
Thomas Abrahamc81fdbe2016-04-23 22:18:11 +053093 u32 uclk;
94
95#ifdef CONFIG_CLK_EXYNOS
Stephen Warrena9622432016-06-17 09:44:00 -060096 struct clk clk;
Thomas Abrahamc81fdbe2016-04-23 22:18:11 +053097 u32 ret;
98
Stephen Warrena9622432016-06-17 09:44:00 -060099 ret = clk_get_by_index(dev, 1, &clk);
Thomas Abrahamc81fdbe2016-04-23 22:18:11 +0530100 if (ret < 0)
101 return ret;
Stephen Warrena9622432016-06-17 09:44:00 -0600102 uclk = clk_get_rate(&clk);
Thomas Abrahamc81fdbe2016-04-23 22:18:11 +0530103#else
104 uclk = get_uart_clk(plat->port_id);
105#endif
Simon Glass405fd142015-07-02 18:15:53 -0600106
107 s5p_serial_baud(uart, uclk, baudrate);
Simon Glass767e7372014-09-14 16:36:17 -0600108
109 return 0;
Minkyu Kangfca30842009-10-01 17:20:28 +0900110}
111
Simon Glass767e7372014-09-14 16:36:17 -0600112static int s5p_serial_probe(struct udevice *dev)
Minkyu Kangfca30842009-10-01 17:20:28 +0900113{
Simon Glass767e7372014-09-14 16:36:17 -0600114 struct s5p_serial_platdata *plat = dev->platdata;
115 struct s5p_uart *const uart = plat->reg;
Minkyu Kangfca30842009-10-01 17:20:28 +0900116
Simon Glass405fd142015-07-02 18:15:53 -0600117 s5p_serial_init(uart);
Minkyu Kangfca30842009-10-01 17:20:28 +0900118
Minkyu Kangfca30842009-10-01 17:20:28 +0900119 return 0;
120}
121
Simon Glass767e7372014-09-14 16:36:17 -0600122static int serial_err_check(const struct s5p_uart *const uart, int op)
Minkyu Kangfca30842009-10-01 17:20:28 +0900123{
Minkyu Kang9455aab2009-11-10 20:23:50 +0900124 unsigned int mask;
Minkyu Kangfca30842009-10-01 17:20:28 +0900125
Minkyu Kang9455aab2009-11-10 20:23:50 +0900126 /*
127 * UERSTAT
128 * Break Detect [3]
129 * Frame Err [2] : receive operation
130 * Parity Err [1] : receive operation
131 * Overrun Err [0] : receive operation
132 */
133 if (op)
134 mask = 0x8;
135 else
136 mask = 0xf;
Minkyu Kangfca30842009-10-01 17:20:28 +0900137
Minkyu Kang9455aab2009-11-10 20:23:50 +0900138 return readl(&uart->uerstat) & mask;
Minkyu Kangfca30842009-10-01 17:20:28 +0900139}
140
Simon Glass767e7372014-09-14 16:36:17 -0600141static int s5p_serial_getc(struct udevice *dev)
Minkyu Kangfca30842009-10-01 17:20:28 +0900142{
Simon Glass767e7372014-09-14 16:36:17 -0600143 struct s5p_serial_platdata *plat = dev->platdata;
144 struct s5p_uart *const uart = plat->reg;
Minkyu Kangfca30842009-10-01 17:20:28 +0900145
Simon Glass767e7372014-09-14 16:36:17 -0600146 if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
147 return -EAGAIN;
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530148
Simon Glass767e7372014-09-14 16:36:17 -0600149 serial_err_check(uart, 0);
Minkyu Kang76229812010-07-06 20:08:29 +0900150 return (int)(readb(&uart->urxh) & 0xff);
Minkyu Kangfca30842009-10-01 17:20:28 +0900151}
152
Simon Glass767e7372014-09-14 16:36:17 -0600153static int s5p_serial_putc(struct udevice *dev, const char ch)
Minkyu Kangfca30842009-10-01 17:20:28 +0900154{
Simon Glass767e7372014-09-14 16:36:17 -0600155 struct s5p_serial_platdata *plat = dev->platdata;
156 struct s5p_uart *const uart = plat->reg;
Minkyu Kangfca30842009-10-01 17:20:28 +0900157
Simon Glass767e7372014-09-14 16:36:17 -0600158 if (readl(&uart->ufstat) & TX_FIFO_FULL)
159 return -EAGAIN;
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530160
Simon Glass767e7372014-09-14 16:36:17 -0600161 writeb(ch, &uart->utxh);
162 serial_err_check(uart, 1);
Minkyu Kangfca30842009-10-01 17:20:28 +0900163
Simon Glass767e7372014-09-14 16:36:17 -0600164 return 0;
Minkyu Kangfca30842009-10-01 17:20:28 +0900165}
166
Simon Glass767e7372014-09-14 16:36:17 -0600167static int s5p_serial_pending(struct udevice *dev, bool input)
Minkyu Kangfca30842009-10-01 17:20:28 +0900168{
Simon Glass767e7372014-09-14 16:36:17 -0600169 struct s5p_serial_platdata *plat = dev->platdata;
170 struct s5p_uart *const uart = plat->reg;
171 uint32_t ufstat = readl(&uart->ufstat);
Minkyu Kangfca30842009-10-01 17:20:28 +0900172
Simon Glass767e7372014-09-14 16:36:17 -0600173 if (input)
174 return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
175 else
176 return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
Marek Vasut5bcdf242012-09-09 18:48:28 +0200177}
Minkyu Kangfca30842009-10-01 17:20:28 +0900178
Simon Glass767e7372014-09-14 16:36:17 -0600179static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530180{
Simon Glass767e7372014-09-14 16:36:17 -0600181 struct s5p_serial_platdata *plat = dev->platdata;
182 fdt_addr_t addr;
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530183
Simon Glassba1dea42017-05-17 17:18:05 -0600184 addr = devfdt_get_addr(dev);
Simon Glass767e7372014-09-14 16:36:17 -0600185 if (addr == FDT_ADDR_T_NONE)
186 return -EINVAL;
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530187
Simon Glass767e7372014-09-14 16:36:17 -0600188 plat->reg = (struct s5p_uart *)addr;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700189 plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Thomas Abraham214a3952016-04-23 22:18:10 +0530190 "id", dev->seq);
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530191 return 0;
192}
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530193
Simon Glass767e7372014-09-14 16:36:17 -0600194static const struct dm_serial_ops s5p_serial_ops = {
195 .putc = s5p_serial_putc,
196 .pending = s5p_serial_pending,
197 .getc = s5p_serial_getc,
198 .setbrg = s5p_serial_setbrg,
199};
Rajeshwari Shindebd19fa92013-06-24 16:47:22 +0530200
Simon Glass767e7372014-09-14 16:36:17 -0600201static const struct udevice_id s5p_serial_ids[] = {
202 { .compatible = "samsung,exynos4210-uart" },
203 { }
204};
Marek Vasut533e31e2012-09-12 19:39:57 +0200205
Simon Glass767e7372014-09-14 16:36:17 -0600206U_BOOT_DRIVER(serial_s5p) = {
207 .name = "serial_s5p",
208 .id = UCLASS_SERIAL,
209 .of_match = s5p_serial_ids,
210 .ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
211 .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
212 .probe = s5p_serial_probe,
213 .ops = &s5p_serial_ops,
214 .flags = DM_FLAG_PRE_RELOC,
215};
Simon Glass8ed4bc12015-07-02 18:15:55 -0600216#endif
Simon Glass74afb292015-07-02 18:15:54 -0600217
218#ifdef CONFIG_DEBUG_UART_S5P
219
220#include <debug_uart.h>
221
Simon Glass60517d72015-10-18 19:51:23 -0600222static inline void _debug_uart_init(void)
Simon Glass74afb292015-07-02 18:15:54 -0600223{
224 struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
225
226 s5p_serial_init(uart);
227 s5p_serial_baud(uart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
228}
229
230static inline void _debug_uart_putc(int ch)
231{
232 struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
233
234 while (readl(&uart->ufstat) & TX_FIFO_FULL);
235
236 writeb(ch, &uart->utxh);
237}
238
239DEBUG_UART_FUNCS
240
241#endif