clk: convert API to match reset/mailbox style
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
provider now implements a single set of clocks. This provides a simpler
conceptual interface to clients, and better aligns with device tree
clock bindings.
* Clocks are now identified with a single "struct clk", rather than
requiring clients to store the clock provider device and clock identity
values separately. For simple clock consumers, this isolates clients
from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
clk-uclass.h contains the provider API. This aligns with the recently
added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
can customize these operations if needed. This also aligns with the
recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.
Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.
test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index cb55c5a..6225479 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -94,13 +94,13 @@
u32 uclk;
#ifdef CONFIG_CLK_EXYNOS
- struct udevice *clk_dev;
+ struct clk clk;
u32 ret;
- ret = clk_get_by_index(dev, 1, &clk_dev);
+ ret = clk_get_by_index(dev, 1, &clk);
if (ret < 0)
return ret;
- uclk = clk_get_periph_rate(clk_dev, ret);
+ uclk = clk_get_rate(&clk);
#else
uclk = get_uart_clk(plat->port_id);
#endif