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git01.mediatek.com / filogic / uboot / b177bf3f0c89b36d302d9e34e240a5569b482dd2 / . / drivers / spi / rk_spi.h
blob: 2e0d1eeb9fdbee0fc8f556d1aa739011b055a084 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glassd1c13772015-09-01 19:19:37 -0600[diff] [blame]2/*
3 * SPI driver for rockchip
4 *
5 * (C) Copyright 2015 Google, Inc
6 *
7 * (C) Copyright 2008-2013 Rockchip Electronics
8 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
Simon Glassd1c13772015-09-01 19:19:37 -0600[diff] [blame]9 */
10
11#ifndef __RK_SPI_H
12#define __RK_SPI_H
13
14struct rockchip_spi {
15 u32 ctrlr0;
16 u32 ctrlr1;
17 u32 enr;
18 u32 ser;
19 u32 baudr;
20 u32 txftlr;
21 u32 rxftlr;
22 u32 txflr;
23 u32 rxflr;
24 u32 sr;
25 u32 ipr;
26 u32 imr;
27 u32 isr;
28 u32 risr;
29 u32 icr;
30 u32 dmacr;
31 u32 dmatdlr;
32 u32 dmardlr; /* 0x44 */
33 u32 reserved[0xef];
34 u32 txdr[0x100]; /* 0x400 */
35 u32 rxdr[0x100]; /* 0x800 */
36};
37
38/* CTRLR0 */
39enum {
40 DFS_SHIFT = 0, /* Data Frame Size */
41 DFS_MASK = 3,
42 DFS_4BIT = 0,
43 DFS_8BIT,
44 DFS_16BIT,
45 DFS_RESV,
46
47 CFS_SHIFT = 2, /* Control Frame Size */
48 CFS_MASK = 0xf,
49
50 SCPH_SHIFT = 6, /* Serial Clock Phase */
51 SCPH_MASK = 1,
52 SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */
53 SCPH_TOGSTA, /* SCLK toggles at start of first data bit */
54
55 SCOL_SHIFT = 7, /* Serial Clock Polarity */
56 SCOL_MASK = 1,
57 SCOL_LOW = 0, /* Inactive state of serial clock is low */
58 SCOL_HIGH, /* Inactive state of serial clock is high */
59
60 CSM_SHIFT = 8, /* Chip Select Mode */
61 CSM_MASK = 0x3,
62 CSM_KEEP = 0, /* ss_n stays low after each frame */
63 CSM_HALF, /* ss_n high for half sclk_out cycles */
64 CSM_ONE, /* ss_n high for one sclk_out cycle */
65 CSM_RESV,
66
67 SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */
68 SSN_DELAY_MASK = 1,
69 SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */
70 SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */
71
72 SEM_SHIFT = 11, /* Serial Endian Mode */
73 SEM_MASK = 1,
74 SEM_LITTLE = 0, /* little endian */
75 SEM_BIG, /* big endian */
76
77 FBM_SHIFT = 12, /* First Bit Mode */
78 FBM_MASK = 1,
79 FBM_MSB = 0, /* first bit is MSB */
80 FBM_LSB, /* first bit in LSB */
81
82 HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */
83 HALF_WORD_MASK = 1,
84 HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
85 HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
86
87 RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */
88 RXDSD_MASK = 3,
89
90 FRF_SHIFT = 16, /* Frame Format */
91 FRF_MASK = 3,
92 FRF_SPI = 0, /* Motorola SPI */
93 FRF_SSP, /* Texas Instruments SSP*/
94 FRF_MICROWIRE, /* National Semiconductors Microwire */
95 FRF_RESV,
96
97 TMOD_SHIFT = 18, /* Transfer Mode */
98 TMOD_MASK = 3,
99 TMOD_TR = 0, /* xmit & recv */
100 TMOD_TO, /* xmit only */
101 TMOD_RO, /* recv only */
102 TMOD_RESV,
103
104 OMOD_SHIFT = 20, /* Operation Mode */
105 OMOD_MASK = 1,
106 OMOD_MASTER = 0, /* Master Mode */
107 OMOD_SLAVE, /* Slave Mode */
108};
109
110/* SR */
111enum {
112 SR_MASK = 0x7f,
113 SR_BUSY = 1 << 0,
114 SR_TF_FULL = 1 << 1,
115 SR_TF_EMPT = 1 << 2,
116 SR_RF_EMPT = 1 << 3,
117 SR_RF_FULL = 1 << 4,
118};
119
120#define ROCKCHIP_SPI_TIMEOUT_MS 1000
Philipp Tomsich45447882017-04-20 22:05:51 +0200[diff] [blame]121
122/*
123 * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
124 * hardware limitation... the Linux kernel source has the following
125 * comment:
126 * "sclk_out: spi master internal logic in rk3x can support 50Mhz"
127 */
128#define ROCKCHIP_SPI_MAX_RATE 50000000
Simon Glassd1c13772015-09-01 19:19:37 -0600[diff] [blame]129
130#endif /* __RK_SPI_H */