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git01.mediatek.com / filogic / uboot / 45447884beef6209e9665609734274d4c0ef492e / . / drivers / spi / rk_spi.h
blob: 02aa9d0436892c4a35b4e9bd4c9576a5e63419dc [file] [log] [blame]
Simon Glassd1c13772015-09-01 19:19:37 -0600[diff] [blame]1/*
2 * SPI driver for rockchip
3 *
4 * (C) Copyright 2015 Google, Inc
5 *
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#ifndef __RK_SPI_H
13#define __RK_SPI_H
14
15struct rockchip_spi {
16 u32 ctrlr0;
17 u32 ctrlr1;
18 u32 enr;
19 u32 ser;
20 u32 baudr;
21 u32 txftlr;
22 u32 rxftlr;
23 u32 txflr;
24 u32 rxflr;
25 u32 sr;
26 u32 ipr;
27 u32 imr;
28 u32 isr;
29 u32 risr;
30 u32 icr;
31 u32 dmacr;
32 u32 dmatdlr;
33 u32 dmardlr; /* 0x44 */
34 u32 reserved[0xef];
35 u32 txdr[0x100]; /* 0x400 */
36 u32 rxdr[0x100]; /* 0x800 */
37};
38
39/* CTRLR0 */
40enum {
41 DFS_SHIFT = 0, /* Data Frame Size */
42 DFS_MASK = 3,
43 DFS_4BIT = 0,
44 DFS_8BIT,
45 DFS_16BIT,
46 DFS_RESV,
47
48 CFS_SHIFT = 2, /* Control Frame Size */
49 CFS_MASK = 0xf,
50
51 SCPH_SHIFT = 6, /* Serial Clock Phase */
52 SCPH_MASK = 1,
53 SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */
54 SCPH_TOGSTA, /* SCLK toggles at start of first data bit */
55
56 SCOL_SHIFT = 7, /* Serial Clock Polarity */
57 SCOL_MASK = 1,
58 SCOL_LOW = 0, /* Inactive state of serial clock is low */
59 SCOL_HIGH, /* Inactive state of serial clock is high */
60
61 CSM_SHIFT = 8, /* Chip Select Mode */
62 CSM_MASK = 0x3,
63 CSM_KEEP = 0, /* ss_n stays low after each frame */
64 CSM_HALF, /* ss_n high for half sclk_out cycles */
65 CSM_ONE, /* ss_n high for one sclk_out cycle */
66 CSM_RESV,
67
68 SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */
69 SSN_DELAY_MASK = 1,
70 SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */
71 SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */
72
73 SEM_SHIFT = 11, /* Serial Endian Mode */
74 SEM_MASK = 1,
75 SEM_LITTLE = 0, /* little endian */
76 SEM_BIG, /* big endian */
77
78 FBM_SHIFT = 12, /* First Bit Mode */
79 FBM_MASK = 1,
80 FBM_MSB = 0, /* first bit is MSB */
81 FBM_LSB, /* first bit in LSB */
82
83 HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */
84 HALF_WORD_MASK = 1,
85 HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
86 HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
87
88 RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */
89 RXDSD_MASK = 3,
90
91 FRF_SHIFT = 16, /* Frame Format */
92 FRF_MASK = 3,
93 FRF_SPI = 0, /* Motorola SPI */
94 FRF_SSP, /* Texas Instruments SSP*/
95 FRF_MICROWIRE, /* National Semiconductors Microwire */
96 FRF_RESV,
97
98 TMOD_SHIFT = 18, /* Transfer Mode */
99 TMOD_MASK = 3,
100 TMOD_TR = 0, /* xmit & recv */
101 TMOD_TO, /* xmit only */
102 TMOD_RO, /* recv only */
103 TMOD_RESV,
104
105 OMOD_SHIFT = 20, /* Operation Mode */
106 OMOD_MASK = 1,
107 OMOD_MASTER = 0, /* Master Mode */
108 OMOD_SLAVE, /* Slave Mode */
109};
110
111/* SR */
112enum {
113 SR_MASK = 0x7f,
114 SR_BUSY = 1 << 0,
115 SR_TF_FULL = 1 << 1,
116 SR_TF_EMPT = 1 << 2,
117 SR_RF_EMPT = 1 << 3,
118 SR_RF_FULL = 1 << 4,
119};
120
121#define ROCKCHIP_SPI_TIMEOUT_MS 1000
Philipp Tomsich45447882017-04-20 22:05:51 +0200[diff] [blame^]122
123/*
124 * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
125 * hardware limitation... the Linux kernel source has the following
126 * comment:
127 * "sclk_out: spi master internal logic in rk3x can support 50Mhz"
128 */
129#define ROCKCHIP_SPI_MAX_RATE 50000000
Simon Glassd1c13772015-09-01 19:19:37 -0600[diff] [blame]130
131#endif /* __RK_SPI_H */