Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b15705aa9538a7c223cc5c217ce9407883ca3c18 / . / arch / arm / include / asm / arch-am33xx / cpu.h
blob: 79081de700b486f43f172d85b536fd3200b6f854 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]2/*
3 * cpu.h
4 *
5 * AM33xx specific header file
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]8 */
9
10#ifndef _AM33XX_CPU_H
11#define _AM33XX_CPU_H
12
13#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
14#include <asm/types.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]15#include <linux/bitops.h>
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]16#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
17
18#include <asm/arch/hardware.h>
19
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]20#define CL_BIT(x) (0 << x)
21
22/* Timer register bits */
23#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
24#define TCLR_AR BIT(1) /* Auto reload */
25#define TCLR_PRE BIT(5) /* Pre-scaler enable */
26#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
27#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
Hannes Petermaier66ad0642014-06-04 10:19:26 +0200[diff] [blame]28#define TCLR_CE BIT(6) /* compare mode enable */
29#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
30#define TCLR_TCM BIT(8) /* edge detection of input pin*/
31#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
32#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
33#define TCLR_CAPTMODE BIT(13) /* capture mode */
34#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]35
Hannes Petermaier66ad0642014-06-04 10:19:26 +0200[diff] [blame]36#define TCFG_RESET BIT(0) /* software reset */
37#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
38#define TCFG_IDLEMOD_SHIFT (2) /* power management */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]39
Lokesh Vutla72996bf2016-10-04 09:34:50 +0530[diff] [blame]40/* cpu-id for AM43XX AM33XX and TI81XX family */
41#define AM437X 0xB98C
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]42#define AM335X 0xB944
Matt Porter691fbe32013-03-15 10:07:06 +0000[diff] [blame]43#define TI81XX 0xB81E
44#define DEVICE_ID (CTRL_BASE + 0x0600)
Tom Rinif021dba2013-08-30 16:28:45 -0400[diff] [blame]45#define DEVICE_ID_MASK 0x1FFF
Lokesh Vutla1bda3732017-05-05 12:59:08 +0530[diff] [blame]46#define PACKAGE_TYPE_SHIFT 16
47#define PACKAGE_TYPE_MASK (3 << 16)
48
49/* Package Type */
50#define PACKAGE_TYPE_UNDEFINED 0x0
51#define PACKAGE_TYPE_ZCZ 0x1
52#define PACKAGE_TYPE_ZCE 0x2
53#define PACKAGE_TYPE_RESERVED 0x3
Tom Rinif021dba2013-08-30 16:28:45 -0400[diff] [blame]54
55/* MPU max frequencies */
56#define AM335X_ZCZ_300 0x1FEF
57#define AM335X_ZCZ_600 0x1FAF
58#define AM335X_ZCZ_720 0x1F2F
59#define AM335X_ZCZ_800 0x1E2F
60#define AM335X_ZCZ_1000 0x1C2F
61#define AM335X_ZCE_300 0x1FDF
62#define AM335X_ZCE_600 0x1F9F
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]63
64/* This gives the status of the boot mode pins on the evm */
65#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
66 | BIT(3) | BIT(4))
67
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]68#define PRM_RSTCTRL_RESET 0x01
Lokesh Vutlae89f1542012-05-29 19:26:41 +0000[diff] [blame]69#define PRM_RSTST_WARM_RESET_MASK 0x232
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]70
Russ Dillbe5bacc2018-03-20 12:23:00 +0530[diff] [blame]71/* EMIF Control register bits */
72#define EMIF_CTRL_DEVOFF BIT(0)
73
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]74#ifndef __KERNEL_STRICT_NAMES
75#ifndef __ASSEMBLY__
Lukasz Majewskid9db5902017-02-19 23:24:36 +0100[diff] [blame]76#include <asm/ti-common/omap_wdt.h>
Ilya Yanok2ebbb862012-11-06 13:06:30 +0000[diff] [blame]77
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]78#ifndef CONFIG_AM43XX
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]79/* Encapsulating core pll registers */
80struct cm_wkuppll {
81 unsigned int wkclkstctrl; /* offset 0x00 */
82 unsigned int wkctrlclkctrl; /* offset 0x04 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]83 unsigned int wkgpio0clkctrl; /* offset 0x08 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]84 unsigned int wkl4wkclkctrl; /* offset 0x0c */
Hannes Petermaier66ad0642014-06-04 10:19:26 +0200[diff] [blame]85 unsigned int timer0clkctrl; /* offset 0x10 */
86 unsigned int resv2[3];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]87 unsigned int idlestdpllmpu; /* offset 0x20 */
Heiko Schocher85754732016-06-07 08:31:19 +0200[diff] [blame]88 unsigned int sscdeltamstepdllmpu; /* off 0x24 */
89 unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]90 unsigned int clkseldpllmpu; /* offset 0x2c */
91 unsigned int resv4[1];
92 unsigned int idlestdpllddr; /* offset 0x34 */
93 unsigned int resv5[2];
94 unsigned int clkseldpllddr; /* offset 0x40 */
95 unsigned int resv6[4];
96 unsigned int clkseldplldisp; /* offset 0x54 */
97 unsigned int resv7[1];
98 unsigned int idlestdpllcore; /* offset 0x5c */
99 unsigned int resv8[2];
100 unsigned int clkseldpllcore; /* offset 0x68 */
101 unsigned int resv9[1];
102 unsigned int idlestdpllper; /* offset 0x70 */
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]103 unsigned int resv10[2];
104 unsigned int clkdcoldodpllper; /* offset 0x7c */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]105 unsigned int divm4dpllcore; /* offset 0x80 */
106 unsigned int divm5dpllcore; /* offset 0x84 */
107 unsigned int clkmoddpllmpu; /* offset 0x88 */
108 unsigned int clkmoddpllper; /* offset 0x8c */
109 unsigned int clkmoddpllcore; /* offset 0x90 */
110 unsigned int clkmoddpllddr; /* offset 0x94 */
111 unsigned int clkmoddplldisp; /* offset 0x98 */
112 unsigned int clkseldpllper; /* offset 0x9c */
113 unsigned int divm2dpllddr; /* offset 0xA0 */
114 unsigned int divm2dplldisp; /* offset 0xA4 */
115 unsigned int divm2dpllmpu; /* offset 0xA8 */
116 unsigned int divm2dpllper; /* offset 0xAC */
117 unsigned int resv11[1];
118 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
Patil, Rachna5f70c512012-01-22 23:47:01 +0000[diff] [blame]119 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
Hannes Petermaier94360592014-02-07 14:06:50 +0100[diff] [blame]120 unsigned int wkup_adctscctrl; /* offset 0xBC */
Hannes Petermaier66ad0642014-06-04 10:19:26 +0200[diff] [blame]121 unsigned int resv12;
122 unsigned int timer1clkctrl; /* offset 0xC4 */
123 unsigned int resv13[4];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]124 unsigned int divm6dpllcore; /* offset 0xD8 */
125};
126
127/**
128 * Encapsulating peripheral functional clocks
129 * pll registers
130 */
131struct cm_perpll {
132 unsigned int l4lsclkstctrl; /* offset 0x00 */
133 unsigned int l3sclkstctrl; /* offset 0x04 */
134 unsigned int l4fwclkstctrl; /* offset 0x08 */
135 unsigned int l3clkstctrl; /* offset 0x0c */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]136 unsigned int resv1;
137 unsigned int cpgmac0clkctrl; /* offset 0x14 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]138 unsigned int lcdclkctrl; /* offset 0x18 */
139 unsigned int usb0clkctrl; /* offset 0x1C */
140 unsigned int resv2;
141 unsigned int tptc0clkctrl; /* offset 0x24 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]142 unsigned int emifclkctrl; /* offset 0x28 */
143 unsigned int ocmcramclkctrl; /* offset 0x2c */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]144 unsigned int gpmcclkctrl; /* offset 0x30 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]145 unsigned int mcasp0clkctrl; /* offset 0x34 */
146 unsigned int uart5clkctrl; /* offset 0x38 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]147 unsigned int mmc0clkctrl; /* offset 0x3C */
148 unsigned int elmclkctrl; /* offset 0x40 */
149 unsigned int i2c2clkctrl; /* offset 0x44 */
150 unsigned int i2c1clkctrl; /* offset 0x48 */
151 unsigned int spi0clkctrl; /* offset 0x4C */
152 unsigned int spi1clkctrl; /* offset 0x50 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]153 unsigned int resv3[3];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]154 unsigned int l4lsclkctrl; /* offset 0x60 */
155 unsigned int l4fwclkctrl; /* offset 0x64 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]156 unsigned int mcasp1clkctrl; /* offset 0x68 */
157 unsigned int uart1clkctrl; /* offset 0x6C */
158 unsigned int uart2clkctrl; /* offset 0x70 */
159 unsigned int uart3clkctrl; /* offset 0x74 */
160 unsigned int uart4clkctrl; /* offset 0x78 */
161 unsigned int timer7clkctrl; /* offset 0x7C */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]162 unsigned int timer2clkctrl; /* offset 0x80 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]163 unsigned int timer3clkctrl; /* offset 0x84 */
164 unsigned int timer4clkctrl; /* offset 0x88 */
165 unsigned int resv4[8];
166 unsigned int gpio1clkctrl; /* offset 0xAC */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]167 unsigned int gpio2clkctrl; /* offset 0xB0 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]168 unsigned int gpio3clkctrl; /* offset 0xB4 */
169 unsigned int resv5;
170 unsigned int tpccclkctrl; /* offset 0xBC */
171 unsigned int dcan0clkctrl; /* offset 0xC0 */
172 unsigned int dcan1clkctrl; /* offset 0xC4 */
Hannes Petermaier94360592014-02-07 14:06:50 +0100[diff] [blame]173 unsigned int resv6;
174 unsigned int epwmss1clkctrl; /* offset 0xCC */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]175 unsigned int emiffwclkctrl; /* offset 0xD0 */
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]176 unsigned int epwmss0clkctrl; /* offset 0xD4 */
177 unsigned int epwmss2clkctrl; /* offset 0xD8 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]178 unsigned int l3instrclkctrl; /* offset 0xDC */
179 unsigned int l3clkctrl; /* Offset 0xE0 */
Hannes Petermaier66ad0642014-06-04 10:19:26 +0200[diff] [blame]180 unsigned int resv8[2];
181 unsigned int timer5clkctrl; /* offset 0xEC */
182 unsigned int timer6clkctrl; /* offset 0xF0 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]183 unsigned int mmc1clkctrl; /* offset 0xF4 */
184 unsigned int mmc2clkctrl; /* offset 0xF8 */
185 unsigned int resv9[8];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]186 unsigned int l4hsclkstctrl; /* offset 0x11C */
187 unsigned int l4hsclkctrl; /* offset 0x120 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]188 unsigned int resv10[8];
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]189 unsigned int cpswclkstctrl; /* offset 0x144 */
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]190 unsigned int lcdcclkstctrl; /* offset 0x148 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]191};
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]192
193/* Encapsulating Display pll registers */
194struct cm_dpll {
Hannes Petermaier66ad0642014-06-04 10:19:26 +0200[diff] [blame]195 unsigned int resv1;
196 unsigned int clktimer7clk; /* offset 0x04 */
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]197 unsigned int clktimer2clk; /* offset 0x08 */
Hannes Petermaier66ad0642014-06-04 10:19:26 +0200[diff] [blame]198 unsigned int clktimer3clk; /* offset 0x0C */
199 unsigned int clktimer4clk; /* offset 0x10 */
200 unsigned int resv2;
201 unsigned int clktimer5clk; /* offset 0x18 */
202 unsigned int clktimer6clk; /* offset 0x1C */
203 unsigned int resv3[2];
204 unsigned int clktimer1clk; /* offset 0x28 */
205 unsigned int resv4[2];
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]206 unsigned int clklcdcpixelclk; /* offset 0x34 */
207};
James Doublesin53c723b2014-12-22 16:26:11 -0600[diff] [blame]208
209struct prm_device_inst {
210 unsigned int prm_rstctrl;
211 unsigned int prm_rsttime;
212 unsigned int prm_rstst;
213};
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]214#else
215/* Encapsulating core pll registers */
216struct cm_wkuppll {
217 unsigned int resv0[136];
218 unsigned int wkl4wkclkctrl; /* offset 0x220 */
Kishon Vijay Abraham Iac75bb12015-02-23 18:39:45 +0530[diff] [blame]219 unsigned int resv1[7];
220 unsigned int usbphy0clkctrl; /* offset 0x240 */
221 unsigned int resv112;
222 unsigned int usbphy1clkctrl; /* offset 0x248 */
223 unsigned int resv113[45];
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]224 unsigned int wkclkstctrl; /* offset 0x300 */
225 unsigned int resv2[15];
226 unsigned int wkup_i2c0ctrl; /* offset 0x340 */
227 unsigned int resv3;
228 unsigned int wkup_uart0ctrl; /* offset 0x348 */
229 unsigned int resv4[5];
230 unsigned int wkctrlclkctrl; /* offset 0x360 */
231 unsigned int resv5;
232 unsigned int wkgpio0clkctrl; /* offset 0x368 */
233
234 unsigned int resv6[109];
235 unsigned int clkmoddpllcore; /* offset 0x520 */
236 unsigned int idlestdpllcore; /* offset 0x524 */
237 unsigned int resv61;
238 unsigned int clkseldpllcore; /* offset 0x52C */
239 unsigned int resv7[2];
240 unsigned int divm4dpllcore; /* offset 0x538 */
241 unsigned int divm5dpllcore; /* offset 0x53C */
242 unsigned int divm6dpllcore; /* offset 0x540 */
243
244 unsigned int resv8[7];
245 unsigned int clkmoddpllmpu; /* offset 0x560 */
246 unsigned int idlestdpllmpu; /* offset 0x564 */
247 unsigned int resv9;
248 unsigned int clkseldpllmpu; /* offset 0x56c */
249 unsigned int divm2dpllmpu; /* offset 0x570 */
250
251 unsigned int resv10[11];
252 unsigned int clkmoddpllddr; /* offset 0x5A0 */
253 unsigned int idlestdpllddr; /* offset 0x5A4 */
254 unsigned int resv11;
255 unsigned int clkseldpllddr; /* offset 0x5AC */
256 unsigned int divm2dpllddr; /* offset 0x5B0 */
257
258 unsigned int resv12[11];
259 unsigned int clkmoddpllper; /* offset 0x5E0 */
260 unsigned int idlestdpllper; /* offset 0x5E4 */
261 unsigned int resv13;
262 unsigned int clkseldpllper; /* offset 0x5EC */
263 unsigned int divm2dpllper; /* offset 0x5F0 */
264 unsigned int resv14[8];
265 unsigned int clkdcoldodpllper; /* offset 0x614 */
266
267 unsigned int resv15[2];
268 unsigned int clkmoddplldisp; /* offset 0x620 */
269 unsigned int resv16[2];
270 unsigned int clkseldplldisp; /* offset 0x62C */
271 unsigned int divm2dplldisp; /* offset 0x630 */
272};
273
274/*
275 * Encapsulating peripheral functional clocks
276 * pll registers
277 */
278struct cm_perpll {
279 unsigned int l3clkstctrl; /* offset 0x00 */
280 unsigned int resv0[7];
281 unsigned int l3clkctrl; /* Offset 0x20 */
Kishon Vijay Abraham Iac75bb12015-02-23 18:39:45 +0530[diff] [blame]282 unsigned int resv112[7];
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]283 unsigned int l3instrclkctrl; /* offset 0x40 */
284 unsigned int resv2[3];
285 unsigned int ocmcramclkctrl; /* offset 0x50 */
286 unsigned int resv3[9];
287 unsigned int tpccclkctrl; /* offset 0x78 */
288 unsigned int resv4;
289 unsigned int tptc0clkctrl; /* offset 0x80 */
290
291 unsigned int resv5[7];
292 unsigned int l4hsclkctrl; /* offset 0x0A0 */
293 unsigned int resv6;
294 unsigned int l4fwclkctrl; /* offset 0x0A8 */
295 unsigned int resv7[85];
296 unsigned int l3sclkstctrl; /* offset 0x200 */
297 unsigned int resv8[7];
298 unsigned int gpmcclkctrl; /* offset 0x220 */
299 unsigned int resv9[5];
300 unsigned int mcasp0clkctrl; /* offset 0x238 */
301 unsigned int resv10;
302 unsigned int mcasp1clkctrl; /* offset 0x240 */
303 unsigned int resv11;
304 unsigned int mmc2clkctrl; /* offset 0x248 */
Sourav Poddar7ba4ac52013-12-21 12:50:12 +0530[diff] [blame]305 unsigned int resv12[3];
306 unsigned int qspiclkctrl; /* offset 0x258 */
307 unsigned int resv121;
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]308 unsigned int usb0clkctrl; /* offset 0x260 */
Kishon Vijay Abraham Iac75bb12015-02-23 18:39:45 +0530[diff] [blame]309 unsigned int resv122;
310 unsigned int usb1clkctrl; /* offset 0x268 */
311 unsigned int resv13[101];
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]312 unsigned int l4lsclkstctrl; /* offset 0x400 */
313 unsigned int resv14[7];
314 unsigned int l4lsclkctrl; /* offset 0x420 */
315 unsigned int resv15;
316 unsigned int dcan0clkctrl; /* offset 0x428 */
317 unsigned int resv16;
318 unsigned int dcan1clkctrl; /* offset 0x430 */
319 unsigned int resv17[13];
320 unsigned int elmclkctrl; /* offset 0x468 */
321
322 unsigned int resv18[3];
323 unsigned int gpio1clkctrl; /* offset 0x478 */
324 unsigned int resv19;
325 unsigned int gpio2clkctrl; /* offset 0x480 */
326 unsigned int resv20;
327 unsigned int gpio3clkctrl; /* offset 0x488 */
Dave Gerlach00822ca2014-02-10 11:41:49 -0500[diff] [blame]328 unsigned int resv41;
329 unsigned int gpio4clkctrl; /* offset 0x490 */
330 unsigned int resv42;
331 unsigned int gpio5clkctrl; /* offset 0x498 */
332 unsigned int resv21[3];
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]333
334 unsigned int i2c1clkctrl; /* offset 0x4A8 */
335 unsigned int resv22;
336 unsigned int i2c2clkctrl; /* offset 0x4B0 */
337 unsigned int resv23[3];
338 unsigned int mmc0clkctrl; /* offset 0x4C0 */
339 unsigned int resv24;
340 unsigned int mmc1clkctrl; /* offset 0x4C8 */
341
342 unsigned int resv25[13];
343 unsigned int spi0clkctrl; /* offset 0x500 */
344 unsigned int resv26;
345 unsigned int spi1clkctrl; /* offset 0x508 */
346 unsigned int resv27[9];
347 unsigned int timer2clkctrl; /* offset 0x530 */
348 unsigned int resv28;
349 unsigned int timer3clkctrl; /* offset 0x538 */
350 unsigned int resv29;
351 unsigned int timer4clkctrl; /* offset 0x540 */
352 unsigned int resv30[5];
353 unsigned int timer7clkctrl; /* offset 0x558 */
354
355 unsigned int resv31[9];
356 unsigned int uart1clkctrl; /* offset 0x580 */
357 unsigned int resv32;
358 unsigned int uart2clkctrl; /* offset 0x588 */
359 unsigned int resv33;
360 unsigned int uart3clkctrl; /* offset 0x590 */
361 unsigned int resv34;
362 unsigned int uart4clkctrl; /* offset 0x598 */
363 unsigned int resv35;
364 unsigned int uart5clkctrl; /* offset 0x5A0 */
Kishon Vijay Abraham Iac75bb12015-02-23 18:39:45 +0530[diff] [blame]365 unsigned int resv36[5];
366 unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
367 unsigned int resv361;
368 unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
369 unsigned int resv3611[79];
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]370
371 unsigned int emifclkstctrl; /* offset 0x700 */
Kishon Vijay Abraham Iac75bb12015-02-23 18:39:45 +0530[diff] [blame]372 unsigned int resv362[7];
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]373 unsigned int emifclkctrl; /* offset 0x720 */
374 unsigned int resv37[3];
375 unsigned int emiffwclkctrl; /* offset 0x730 */
376 unsigned int resv371;
377 unsigned int otfaemifclkctrl; /* offset 0x738 */
378 unsigned int resv38[57];
379 unsigned int lcdclkctrl; /* offset 0x820 */
380 unsigned int resv39[183];
381 unsigned int cpswclkstctrl; /* offset 0xB00 */
382 unsigned int resv40[7];
383 unsigned int cpgmac0clkctrl; /* offset 0xB20 */
384};
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]385
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]386struct cm_device_inst {
387 unsigned int cm_clkout1_ctrl;
388 unsigned int cm_dll_ctrl;
389};
390
James Doublesin53c723b2014-12-22 16:26:11 -0600[diff] [blame]391struct prm_device_inst {
Russ Dillbe5bacc2018-03-20 12:23:00 +0530[diff] [blame]392 unsigned int rstctrl;
393 unsigned int rstst;
394 unsigned int rsttime;
395 unsigned int sram_count;
396 unsigned int ldo_sram_core_set; /* offset 0x10 */
397 unsigned int ldo_sram_core_ctr;
398 unsigned int ldo_sram_mpu_setu;
399 unsigned int ldo_sram_mpu_ctrl;
400 unsigned int io_count; /* offset 0x20 */
401 unsigned int io_pmctrl;
402 unsigned int vc_val_bypass;
403 unsigned int resv1;
404 unsigned int emif_ctrl; /* offset 0x30 */
James Doublesin53c723b2014-12-22 16:26:11 -0600[diff] [blame]405};
406
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]407struct cm_dpll {
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]408 unsigned int resv1;
409 unsigned int clktimer2clk; /* offset 0x04 */
Steve Kipisz8405db82015-02-11 18:54:28 -0500[diff] [blame]410 unsigned int resv2[11];
411 unsigned int clkselmacclk; /* offset 0x34 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]412};
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]413#endif /* CONFIG_AM43XX */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]414
Vaibhav Hiremath2d7da5f2012-03-08 17:15:47 +0530[diff] [blame]415/* Control Module RTC registers */
416struct cm_rtc {
417 unsigned int rtcclkctrl; /* offset 0x0 */
418 unsigned int clkstctrl; /* offset 0x4 */
419};
420
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]421/* Timer 32 bit registers */
422struct gptimer {
423 unsigned int tidr; /* offset 0x00 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]424 unsigned char res1[12];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]425 unsigned int tiocp_cfg; /* offset 0x10 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]426 unsigned char res2[12];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]427 unsigned int tier; /* offset 0x20 */
428 unsigned int tistatr; /* offset 0x24 */
429 unsigned int tistat; /* offset 0x28 */
430 unsigned int tisr; /* offset 0x2c */
431 unsigned int tcicr; /* offset 0x30 */
432 unsigned int twer; /* offset 0x34 */
433 unsigned int tclr; /* offset 0x38 */
434 unsigned int tcrr; /* offset 0x3c */
435 unsigned int tldr; /* offset 0x40 */
436 unsigned int ttgr; /* offset 0x44 */
437 unsigned int twpc; /* offset 0x48 */
438 unsigned int tmar; /* offset 0x4c */
439 unsigned int tcar1; /* offset 0x50 */
440 unsigned int tscir; /* offset 0x54 */
441 unsigned int tcar2; /* offset 0x58 */
442};
443
444/* UART Registers */
445struct uart_sys {
446 unsigned int resv1[21];
447 unsigned int uartsyscfg; /* offset 0x54 */
448 unsigned int uartsyssts; /* offset 0x58 */
449};
450
451/* VTP Registers */
452struct vtp_reg {
453 unsigned int vtp0ctrlreg;
454};
455
456/* Control Status Register */
457struct ctrl_stat {
458 unsigned int resv1[16];
459 unsigned int statusreg; /* ofset 0x40 */
Satyanarayana, Sandhya11784752012-08-09 18:29:57 +0000[diff] [blame]460 unsigned int resv2[51];
461 unsigned int secure_emif_sdram_config; /* offset 0x0110 */
Lokesh Vutla42c213a2013-12-10 15:02:20 +0530[diff] [blame]462 unsigned int resv3[319];
463 unsigned int dev_attr;
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]464};
Steve Sakoman6229e332012-06-04 05:35:34 +0000[diff] [blame]465
466/* AM33XX GPIO registers */
467#define OMAP_GPIO_REVISION 0x0000
468#define OMAP_GPIO_SYSCONFIG 0x0010
469#define OMAP_GPIO_SYSSTATUS 0x0114
470#define OMAP_GPIO_IRQSTATUS1 0x002c
471#define OMAP_GPIO_IRQSTATUS2 0x0030
Heiko Schocher8aa45482016-06-07 08:31:17 +0200[diff] [blame]472#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
473#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
Steve Sakoman6229e332012-06-04 05:35:34 +0000[diff] [blame]474#define OMAP_GPIO_CTRL 0x0130
475#define OMAP_GPIO_OE 0x0134
476#define OMAP_GPIO_DATAIN 0x0138
477#define OMAP_GPIO_DATAOUT 0x013c
478#define OMAP_GPIO_LEVELDETECT0 0x0140
479#define OMAP_GPIO_LEVELDETECT1 0x0144
480#define OMAP_GPIO_RISINGDETECT 0x0148
481#define OMAP_GPIO_FALLINGDETECT 0x014c
482#define OMAP_GPIO_DEBOUNCE_EN 0x0150
483#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
484#define OMAP_GPIO_CLEARDATAOUT 0x0190
485#define OMAP_GPIO_SETDATAOUT 0x0194
486
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]487/* Control Device Register */
Cooper Jr., Franklindf25e352014-06-27 13:31:15 -0500[diff] [blame]488
489 /* Control Device Register */
490#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
491#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
492#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
493
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]494struct ctrl_dev {
495 unsigned int deviceid; /* offset 0x00 */
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]496 unsigned int resv1[7];
497 unsigned int usb_ctrl0; /* offset 0x20 */
498 unsigned int resv2;
499 unsigned int usb_ctrl1; /* offset 0x28 */
500 unsigned int resv3;
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]501 unsigned int macid0l; /* offset 0x30 */
502 unsigned int macid0h; /* offset 0x34 */
503 unsigned int macid1l; /* offset 0x38 */
504 unsigned int macid1h; /* offset 0x3c */
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]505 unsigned int resv4[4];
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]506 unsigned int miisel; /* offset 0x50 */
Cooper Jr., Franklindf25e352014-06-27 13:31:15 -0500[diff] [blame]507 unsigned int resv5[7];
508 unsigned int mreqprio_0; /* offset 0x70 */
509 unsigned int mreqprio_1; /* offset 0x74 */
510 unsigned int resv6[97];
Tom Rinif021dba2013-08-30 16:28:45 -0400[diff] [blame]511 unsigned int efuse_sma; /* offset 0x1FC */
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]512};
Heiko Schocherc4fea292013-08-19 16:38:56 +0200[diff] [blame]513
Cooper Jr., Franklindf25e352014-06-27 13:31:15 -0500[diff] [blame]514/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
515#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
516#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
517#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
518
519struct l3f_cfg_bwlimiter {
520 u32 padding0[2];
521 u32 modena_init0_bw_fractional;
522 u32 modena_init0_bw_integer;
523 u32 modena_init0_watermark_0;
524};
525
Heiko Schocherc4fea292013-08-19 16:38:56 +0200[diff] [blame]526/* gmii_sel register defines */
527#define GMII1_SEL_MII 0x0
528#define GMII1_SEL_RMII 0x1
529#define GMII1_SEL_RGMII 0x2
530#define GMII2_SEL_MII 0x0
531#define GMII2_SEL_RMII 0x4
532#define GMII2_SEL_RGMII 0x8
533#define RGMII1_IDMODE BIT(4)
534#define RGMII2_IDMODE BIT(5)
535#define RMII1_IO_CLK_EN BIT(6)
536#define RMII2_IO_CLK_EN BIT(7)
537
538#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
539#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
540#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
541#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
542#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
543
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]544/* PWMSS */
545struct pwmss_regs {
546 unsigned int idver;
547 unsigned int sysconfig;
548 unsigned int clkconfig;
549 unsigned int clkstatus;
550};
551#define ECAP_CLK_EN BIT(0)
552#define ECAP_CLK_STOP_REQ BIT(1)
tomas.melin@vaisala.comcf1fcf42016-09-16 10:21:39 +0000[diff] [blame]553#define EPWM_CLK_EN BIT(8)
554#define EPWM_CLK_STOP_REQ BIT(9)
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]555
556struct pwmss_ecap_regs {
557 unsigned int tsctr;
558 unsigned int ctrphs;
559 unsigned int cap1;
560 unsigned int cap2;
561 unsigned int cap3;
562 unsigned int cap4;
563 unsigned int resv1[4];
564 unsigned short ecctl1;
565 unsigned short ecctl2;
566};
567
tomas.melin@vaisala.comcf1fcf42016-09-16 10:21:39 +0000[diff] [blame]568struct pwmss_epwm_regs {
569 unsigned short tbctl;
570 unsigned short tbsts;
571 unsigned short tbphshr;
572 unsigned short tbphs;
573 unsigned short tbcnt;
574 unsigned short tbprd;
575 unsigned short res1;
576 unsigned short cmpctl;
577 unsigned short cmpahr;
578 unsigned short cmpa;
579 unsigned short cmpb;
580 unsigned short aqctla;
581 unsigned short aqctlb;
582 unsigned short aqsfrc;
583 unsigned short aqcsfrc;
584 unsigned short dbctl;
585 unsigned short dbred;
586 unsigned short dbfed;
587 unsigned short tzsel;
588 unsigned short tzctl;
589 unsigned short tzflg;
590 unsigned short tzclr;
591 unsigned short tzfrc;
592 unsigned short etsel;
593 unsigned short etps;
594 unsigned short etflg;
595 unsigned short etclr;
596 unsigned short etfrc;
597 unsigned short pcctl;
598 unsigned int res2[66];
599 unsigned short hrcnfg;
600};
601
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]602/* Capture Control register 2 */
603#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
604#define ECTRL2_MDSL_ECAP BIT(9)
605#define ECTRL2_CTRSTP_FREERUN BIT(4)
606#define ECTRL2_PLSL_LOW BIT(10)
607#define ECTRL2_SYNC_EN BIT(5)
608
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]609#endif /* __ASSEMBLY__ */
610#endif /* __KERNEL_STRICT_NAMES */
611
612#endif /* _AM33XX_CPU_H */