blob: ccd0c8352e21461165da0fc415e9d15eee1b5855 [file] [log] [blame]
Aneesh Vb8e60b92011-07-21 09:10:21 -04001/*
2 * (C) Copyright 2002
3 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Aneesh Vb8e60b92011-07-21 09:10:21 -040010 */
11
12MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
13 LENGTH = CONFIG_SPL_MAX_SIZE }
14MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
15 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
16
17OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
18OUTPUT_ARCH(arm)
19ENTRY(_start)
20SECTIONS
21{
22 .text :
23 {
Pavel Machek63c37f12012-08-30 19:20:22 +020024 __start = .;
Benoît Thébaudeau3f7740f2014-08-21 15:43:11 +020025 *(.vectors)
Benoît Thébaudeau3954db82013-04-11 09:36:03 +000026 arch/arm/cpu/armv7/start.o (.text*)
Pavel Machek63c37f12012-08-30 19:20:22 +020027 *(.text*)
Aneesh Vb8e60b92011-07-21 09:10:21 -040028 } >.sram
29
30 . = ALIGN(4);
31 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
32
33 . = ALIGN(4);
34 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
Marek Vasut607092a2012-10-12 10:27:03 +000035
Aneesh Vb8e60b92011-07-21 09:10:21 -040036 . = ALIGN(4);
Heiko Schocherf53f2b82013-10-22 11:03:18 +020037 .u_boot_list : {
Tom Rini14d643b2013-11-15 12:20:33 -050038 KEEP(*(SORT(.u_boot_list*_i2c_*)));
Heiko Schocherf53f2b82013-10-22 11:03:18 +020039 } >.sram
Tom Rini14d643b2013-11-15 12:20:33 -050040
Heiko Schocherf53f2b82013-10-22 11:03:18 +020041 . = ALIGN(4);
Aneesh Vb8e60b92011-07-21 09:10:21 -040042 __image_copy_end = .;
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010043
44 .end :
45 {
46 *(.__end)
47 }
Aneesh Vb8e60b92011-07-21 09:10:21 -040048
49 .bss :
50 {
51 . = ALIGN(4);
52 __bss_start = .;
53 *(.bss*)
54 . = ALIGN(4);
Simon Glassed70c8f2013-03-14 06:54:53 +000055 __bss_end = .;
Aneesh Vb8e60b92011-07-21 09:10:21 -040056 } >.sdram
57}