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git01.mediatek.com / filogic / uboot / f53f2b84cc0b4ee5f1ed4d117e6b9fad9eaa834c / . / arch / arm / cpu / armv7 / omap-common / u-boot-spl.lds
blob: 989083c8084a05ba1f5091ed976ec10516cb3964 [file] [log] [blame]
Aneesh Vb8e60b92011-07-21 09:10:21 -0400[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]9 * SPDX-License-Identifier: GPL-2.0+
Aneesh Vb8e60b92011-07-21 09:10:21 -0400[diff] [blame]10 */
11
12MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
13 LENGTH = CONFIG_SPL_MAX_SIZE }
14MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
15 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
16
17OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
18OUTPUT_ARCH(arm)
19ENTRY(_start)
20SECTIONS
21{
22 .text :
23 {
Pavel Machek63c37f12012-08-30 19:20:22 +0200[diff] [blame]24 __start = .;
Benoît Thébaudeau3954db82013-04-11 09:36:03 +0000[diff] [blame]25 arch/arm/cpu/armv7/start.o (.text*)
Pavel Machek63c37f12012-08-30 19:20:22 +0200[diff] [blame]26 *(.text*)
Aneesh Vb8e60b92011-07-21 09:10:21 -0400[diff] [blame]27 } >.sram
28
29 . = ALIGN(4);
30 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
31
32 . = ALIGN(4);
33 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]34
Aneesh Vb8e60b92011-07-21 09:10:21 -0400[diff] [blame]35 . = ALIGN(4);
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200[diff] [blame^]36 .u_boot_list : {
37 KEEP(*(SORT(.u_boot_list*)));
38 } >.sram
39 . = ALIGN(4);
Aneesh Vb8e60b92011-07-21 09:10:21 -0400[diff] [blame]40 __image_copy_end = .;
41 _end = .;
42
43 .bss :
44 {
45 . = ALIGN(4);
46 __bss_start = .;
47 *(.bss*)
48 . = ALIGN(4);
Simon Glassed70c8f2013-03-14 06:54:53 +0000[diff] [blame]49 __bss_end = .;
Aneesh Vb8e60b92011-07-21 09:10:21 -0400[diff] [blame]50 } >.sdram
51}