Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 1 | if ARCH_ROCKCHIP |
| 2 | |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 3 | config ROCKCHIP_RK3036 |
| 4 | bool "Support Rockchip RK3036" |
| 5 | select CPU_V7 |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 6 | select SUPPORT_SPL |
| 7 | select SPL |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 8 | help |
| 9 | The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 |
| 10 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 11 | and video codec support. Peripherals include Gigabit Ethernet, |
| 12 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 13 | |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 14 | config ROCKCHIP_RK3128 |
| 15 | bool "Support Rockchip RK3128" |
| 16 | select CPU_V7 |
| 17 | help |
| 18 | The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 |
| 19 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 20 | and video codec support. Peripherals include Gigabit Ethernet, |
| 21 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 22 | |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 23 | config ROCKCHIP_RK3188 |
| 24 | bool "Support Rockchip RK3188" |
| 25 | select CPU_V7 |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 26 | select SPL_BOARD_INIT if SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 27 | select SUPPORT_SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 28 | select SPL |
Philipp Tomsich | 5aa3f9d | 2017-10-10 16:21:17 +0200 | [diff] [blame] | 29 | select SPL_CLK |
| 30 | select SPL_PINCTRL |
| 31 | select SPL_REGMAP |
| 32 | select SPL_SYSCON |
| 33 | select SPL_RAM |
| 34 | select SPL_DRIVERS_MISC_SUPPORT |
Philipp Tomsich | 16c689c | 2017-10-10 16:21:15 +0200 | [diff] [blame] | 35 | select SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
Heiko Stübner | 015f69a | 2017-04-06 00:19:36 +0200 | [diff] [blame] | 36 | select BOARD_LATE_INIT |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 37 | select ROCKCHIP_BROM_HELPER |
| 38 | help |
| 39 | The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 |
| 40 | including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two |
| 41 | video interfaces, several memory options and video codec support. |
| 42 | Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, |
| 43 | UART, SPI, I2C and PWMs. |
| 44 | |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 45 | config ROCKCHIP_RK322X |
| 46 | bool "Support Rockchip RK3228/RK3229" |
| 47 | select CPU_V7 |
| 48 | select SUPPORT_SPL |
| 49 | select SPL |
| 50 | select ROCKCHIP_BROM_HELPER |
| 51 | select DEBUG_UART_BOARD_INIT |
| 52 | help |
| 53 | The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 |
| 54 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 55 | and video codec support. Peripherals include Gigabit Ethernet, |
| 56 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 57 | |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 58 | config ROCKCHIP_RK3288 |
| 59 | bool "Support Rockchip RK3288" |
Andreas Färber | 6c42703 | 2016-07-14 05:09:26 +0200 | [diff] [blame] | 60 | select CPU_V7 |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 61 | select SPL_BOARD_INIT if SPL |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 62 | select SUPPORT_SPL |
| 63 | select SPL |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 64 | help |
| 65 | The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 |
| 66 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 67 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 68 | and video codec support. Peripherals include Gigabit Ethernet, |
Andreas Färber | 531e8e0 | 2016-11-02 18:03:01 +0100 | [diff] [blame] | 69 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 70 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 71 | config ROCKCHIP_RK3328 |
| 72 | bool "Support Rockchip RK3328" |
| 73 | select ARM64 |
| 74 | help |
| 75 | The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. |
| 76 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 77 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 78 | and video codec support. Peripherals include Gigabit Ethernet, |
| 79 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 80 | |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 81 | config ROCKCHIP_RK3368 |
| 82 | bool "Support Rockchip RK3368" |
| 83 | select ARM64 |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 84 | select SUPPORT_SPL |
| 85 | select SUPPORT_TPL |
Philipp Tomsich | 01b219e | 2017-07-28 20:03:07 +0200 | [diff] [blame] | 86 | select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL |
| 87 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 88 | imply SPL_SEPARATE_BSS |
| 89 | imply SPL_SERIAL_SUPPORT |
| 90 | imply TPL_SERIAL_SUPPORT |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 91 | select DEBUG_UART_BOARD_INIT |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 92 | select SYS_NS16550 |
| 93 | help |
Philipp Tomsich | 9f3deaf | 2017-06-10 00:47:53 +0200 | [diff] [blame] | 94 | The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised |
| 95 | into a big and little cluster with 4 cores each) Cortex-A53 including |
| 96 | AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache |
| 97 | (for the little cluster), PowerVR G6110 based graphics, one video |
| 98 | output processor supporting LVDS/HDMI/eDP, several DDR3 options and |
| 99 | video codec support. |
| 100 | |
| 101 | On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, |
| 102 | I2S, UARTs, SPI, I2C and PWMs. |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 103 | |
Philipp Tomsich | cbacb40 | 2017-08-02 21:26:18 +0200 | [diff] [blame] | 104 | if ROCKCHIP_RK3368 |
| 105 | |
| 106 | config TPL_LDSCRIPT |
| 107 | default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" |
| 108 | |
Philipp Tomsich | 7d1319b | 2017-07-28 20:20:41 +0200 | [diff] [blame] | 109 | config TPL_TEXT_BASE |
| 110 | default 0xff8c1000 |
| 111 | |
| 112 | config TPL_MAX_SIZE |
| 113 | default 28672 |
| 114 | |
| 115 | config TPL_STACK |
| 116 | default 0xff8cffff |
| 117 | |
Philipp Tomsich | cbacb40 | 2017-08-02 21:26:18 +0200 | [diff] [blame] | 118 | endif |
| 119 | |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 120 | config ROCKCHIP_RK3399 |
| 121 | bool "Support Rockchip RK3399" |
| 122 | select ARM64 |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 123 | select SUPPORT_SPL |
| 124 | select SPL |
| 125 | select SPL_SEPARATE_BSS |
Philipp Tomsich | d17d8cf | 2017-07-26 12:29:01 +0200 | [diff] [blame] | 126 | select SPL_SERIAL_SUPPORT |
| 127 | select SPL_DRIVERS_MISC_SUPPORT |
Philipp Tomsich | 41029e6 | 2017-04-01 12:59:25 +0200 | [diff] [blame] | 128 | select DEBUG_UART_BOARD_INIT |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 129 | select BOARD_LATE_INIT |
Andy Yan | d2349d9 | 2017-10-11 15:00:49 +0800 | [diff] [blame] | 130 | select ROCKCHIP_BROM_HELPER |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 131 | help |
| 132 | The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 |
| 133 | and quad-core Cortex-A53. |
| 134 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 135 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 136 | and video codec support. Peripherals include Gigabit Ethernet, |
| 137 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 138 | |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 139 | config ROCKCHIP_RV1108 |
| 140 | bool "Support Rockchip RV1108" |
| 141 | select CPU_V7 |
| 142 | help |
| 143 | The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 |
| 144 | and a DSP. |
| 145 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 146 | config SPL_ROCKCHIP_BACK_TO_BROM |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 147 | bool "SPL returns to bootrom" |
| 148 | default y if ROCKCHIP_RK3036 |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 149 | select ROCKCHIP_BROM_HELPER |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 150 | depends on SPL |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 151 | help |
| 152 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 153 | SPL will return to the boot rom, which will then load the U-Boot |
| 154 | binary to keep going on. |
| 155 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 156 | config TPL_ROCKCHIP_BACK_TO_BROM |
| 157 | bool "TPL returns to bootrom" |
| 158 | default y if ROCKCHIP_RK3368 |
| 159 | select ROCKCHIP_BROM_HELPER |
| 160 | depends on TPL |
| 161 | help |
| 162 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 163 | SPL will return to the boot rom, which will then load the U-Boot |
| 164 | binary to keep going on. |
| 165 | |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 166 | config ROCKCHIP_BOOT_MODE_REG |
| 167 | hex "Rockchip boot mode flag register address" |
| 168 | default 0x200081c8 if ROCKCHIP_RK3036 |
| 169 | default 0x20004040 if ROCKCHIP_RK3188 |
| 170 | default 0x110005c8 if ROCKCHIP_RK322X |
| 171 | default 0xff730094 if ROCKCHIP_RK3288 |
| 172 | default 0xff738200 if ROCKCHIP_RK3368 |
| 173 | default 0xff320300 if ROCKCHIP_RK3399 |
| 174 | default 0x10300580 if ROCKCHIP_RV1108 |
| 175 | default 0 |
| 176 | help |
| 177 | The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) |
| 178 | according to the value from this register. |
| 179 | |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 180 | config ROCKCHIP_SPL_RESERVE_IRAM |
| 181 | hex "Size of IRAM reserved in SPL" |
Kever Yang | 60a5007 | 2017-12-18 15:13:19 +0800 | [diff] [blame] | 182 | default 0 |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 183 | help |
| 184 | SPL may need reserve memory for firmware loaded by SPL, whose load |
| 185 | address is in IRAM and may overlay with SPL text area if not |
| 186 | reserved. |
| 187 | |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 188 | config ROCKCHIP_BROM_HELPER |
| 189 | bool |
| 190 | |
Philipp Tomsich | 9f1a447 | 2017-10-10 16:21:10 +0200 | [diff] [blame] | 191 | config SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 192 | bool "SPL requires early-return (for RK3188-style BROM) to BROM" |
| 193 | depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 194 | help |
| 195 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 196 | first stage in segments and enter multiple times. E.g. on |
| 197 | the RK3188, the first 1KB of the first stage are loaded |
| 198 | first and entered; after returning to the BROM, the |
| 199 | remainder of the first stage is loaded, but the BROM |
| 200 | re-enters at the same address/to the same code as previously. |
| 201 | |
| 202 | This enables support code in the BOOT0 hook for the SPL stage |
| 203 | to allow multiple entries. |
| 204 | |
| 205 | config TPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 206 | bool "TPL requires early-return (for RK3188-style BROM) to BROM" |
| 207 | depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 208 | help |
| 209 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 210 | first stage in segments and enter multiple times. E.g. on |
| 211 | the RK3188, the first 1KB of the first stage are loaded |
| 212 | first and entered; after returning to the BROM, the |
| 213 | remainder of the first stage is loaded, but the BROM |
| 214 | re-enters at the same address/to the same code as previously. |
| 215 | |
| 216 | This enables support code in the BOOT0 hook for the TPL stage |
| 217 | to allow multiple entries. |
| 218 | |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 219 | config SPL_MMC_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 220 | default y if !SPL_ROCKCHIP_BACK_TO_BROM |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 221 | |
huang lin | 1115b64 | 2015-11-17 14:20:27 +0800 | [diff] [blame] | 222 | source "arch/arm/mach-rockchip/rk3036/Kconfig" |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 223 | source "arch/arm/mach-rockchip/rk3128/Kconfig" |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 224 | source "arch/arm/mach-rockchip/rk3188/Kconfig" |
Kever Yang | a4f460d | 2017-06-23 17:17:54 +0800 | [diff] [blame] | 225 | source "arch/arm/mach-rockchip/rk322x/Kconfig" |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 226 | source "arch/arm/mach-rockchip/rk3288/Kconfig" |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 227 | source "arch/arm/mach-rockchip/rk3328/Kconfig" |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 228 | source "arch/arm/mach-rockchip/rk3368/Kconfig" |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 229 | source "arch/arm/mach-rockchip/rk3399/Kconfig" |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 230 | source "arch/arm/mach-rockchip/rv1108/Kconfig" |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 231 | endif |