Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / af6e2a784aed79dc58228f72dede8006c8e11da7 / . / arch / arm / dts / k3-am642-evm-u-boot.dtsi
blob: c85f57d40fe8a7a5975eaee5cf380ecdf9189ed8 [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame^]10 tick-timer = &main_timer0;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]11 };
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]12
13 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-pre-ram;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]15 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]16};
17
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame^]18&vtt_supply {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]19 bootph-pre-ram;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame^]20};
21
22&cbass_main {
23 bootph-pre-ram;
24};
25
26&cbass_mcu {
27 bootph-pre-ram;
28};
29
30&main_timer0 {
31 bootph-pre-ram;
32 clock-frequency = <200000000>;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]33};
34
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]35&main_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]37 chipid@14 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]39 };
40};
41
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]42&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame^]44};
45
46&main_i2c0_pins_default {
47 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]48};
49
50&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]52};
53
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame^]54&main_uart0_pins_default {
55 bootph-pre-ram;
56};
57
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]58&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]60};
61
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]62&usb0 {
63 dr_mode="peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]65};
66
67&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]69};
70
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]71&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]73};
74
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]75&main_usb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]77};
78
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]79&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]81};
82
83&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]85};
86
87&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]89 k3_sysreset: sysreset-controller {
90 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]92 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]93};
94
95&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]97};
98
99&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]101};
102
103&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]105};
106
107&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]109};
110
111&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]113};
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]114
115&cpsw3g {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame^]116 bootph-pre-ram;
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]117};
118
119&cpsw_port2 {
120 status = "disabled";
121};