Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007-2012 |
| 3 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 4 | * Tom Cubie <tangliang@allwinnertech.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef _SUNXI_GPIO_H |
| 10 | #define _SUNXI_GPIO_H |
| 11 | |
| 12 | #include <linux/types.h> |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 13 | #include <asm/arch/cpu.h> |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * sunxi has 9 banks of gpio, they are: |
| 17 | * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 |
| 18 | * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 |
| 19 | * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 |
| 20 | */ |
| 21 | |
| 22 | #define SUNXI_GPIO_A 0 |
| 23 | #define SUNXI_GPIO_B 1 |
| 24 | #define SUNXI_GPIO_C 2 |
| 25 | #define SUNXI_GPIO_D 3 |
| 26 | #define SUNXI_GPIO_E 4 |
| 27 | #define SUNXI_GPIO_F 5 |
| 28 | #define SUNXI_GPIO_G 6 |
| 29 | #define SUNXI_GPIO_H 7 |
| 30 | #define SUNXI_GPIO_I 8 |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * This defines the number of GPIO banks for the _main_ GPIO controller. |
| 34 | * You should fix up the padding in struct sunxi_gpio_reg below if you |
| 35 | * change this. |
| 36 | */ |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 37 | #define SUNXI_GPIO_BANKS 9 |
| 38 | |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 39 | /* |
| 40 | * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) |
| 41 | * at a different register offset. |
| 42 | * |
| 43 | * sun6i has 2 banks: |
| 44 | * PL0 - PL8 | PM0 - PM7 |
| 45 | * |
| 46 | * sun8i has 1 bank: |
| 47 | * PL0 - PL11 |
Hans de Goede | 8760c91 | 2015-01-26 16:46:43 +0100 | [diff] [blame] | 48 | * |
| 49 | * sun9i has 3 banks: |
| 50 | * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 51 | */ |
| 52 | #define SUNXI_GPIO_L 11 |
| 53 | #define SUNXI_GPIO_M 12 |
Hans de Goede | 8760c91 | 2015-01-26 16:46:43 +0100 | [diff] [blame] | 54 | #define SUNXI_GPIO_N 13 |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 55 | |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 56 | struct sunxi_gpio { |
| 57 | u32 cfg[4]; |
| 58 | u32 dat; |
| 59 | u32 drv[2]; |
| 60 | u32 pull[2]; |
| 61 | }; |
| 62 | |
| 63 | /* gpio interrupt control */ |
| 64 | struct sunxi_gpio_int { |
| 65 | u32 cfg[3]; |
| 66 | u32 ctl; |
| 67 | u32 sta; |
| 68 | u32 deb; /* interrupt debounce */ |
| 69 | }; |
| 70 | |
| 71 | struct sunxi_gpio_reg { |
| 72 | struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; |
| 73 | u8 res[0xbc]; |
| 74 | struct sunxi_gpio_int gpio_int; |
| 75 | }; |
| 76 | |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 77 | #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ |
| 78 | &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ |
| 79 | &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 80 | |
| 81 | #define GPIO_BANK(pin) ((pin) >> 5) |
| 82 | #define GPIO_NUM(pin) ((pin) & 0x1f) |
| 83 | |
| 84 | #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) |
| 85 | #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) |
| 86 | |
Paul Kocialkowski | c97e168 | 2015-03-22 18:07:08 +0100 | [diff] [blame] | 87 | #define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 88 | #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) |
| 89 | |
| 90 | #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) |
| 91 | #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) |
| 92 | |
| 93 | /* GPIO bank sizes */ |
| 94 | #define SUNXI_GPIO_A_NR 32 |
| 95 | #define SUNXI_GPIO_B_NR 32 |
| 96 | #define SUNXI_GPIO_C_NR 32 |
| 97 | #define SUNXI_GPIO_D_NR 32 |
| 98 | #define SUNXI_GPIO_E_NR 32 |
| 99 | #define SUNXI_GPIO_F_NR 32 |
| 100 | #define SUNXI_GPIO_G_NR 32 |
| 101 | #define SUNXI_GPIO_H_NR 32 |
| 102 | #define SUNXI_GPIO_I_NR 32 |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 103 | #define SUNXI_GPIO_L_NR 32 |
| 104 | #define SUNXI_GPIO_M_NR 32 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 105 | |
| 106 | #define SUNXI_GPIO_NEXT(__gpio) \ |
| 107 | ((__gpio##_START) + (__gpio##_NR) + 0) |
| 108 | |
| 109 | enum sunxi_gpio_number { |
| 110 | SUNXI_GPIO_A_START = 0, |
| 111 | SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), |
| 112 | SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), |
| 113 | SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), |
| 114 | SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), |
| 115 | SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), |
| 116 | SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), |
| 117 | SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), |
| 118 | SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 119 | SUNXI_GPIO_L_START = 352, |
| 120 | SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), |
Hans de Goede | 8760c91 | 2015-01-26 16:46:43 +0100 | [diff] [blame] | 121 | SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), |
Hans de Goede | 1fc9c4a | 2014-12-24 19:34:38 +0100 | [diff] [blame] | 122 | SUNXI_GPIO_AXP0_START = 1024, |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | /* SUNXI GPIO number definitions */ |
| 126 | #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) |
| 127 | #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) |
| 128 | #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) |
| 129 | #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) |
| 130 | #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) |
| 131 | #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) |
| 132 | #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) |
| 133 | #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) |
| 134 | #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) |
Hans de Goede | 0ee7268 | 2014-10-22 16:47:45 +0800 | [diff] [blame] | 135 | #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) |
| 136 | #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) |
Hans de Goede | 8760c91 | 2015-01-26 16:46:43 +0100 | [diff] [blame] | 137 | #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 138 | |
Hans de Goede | 1fc9c4a | 2014-12-24 19:34:38 +0100 | [diff] [blame] | 139 | #define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) |
| 140 | |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 141 | /* GPIO pin function config */ |
| 142 | #define SUNXI_GPIO_INPUT 0 |
| 143 | #define SUNXI_GPIO_OUTPUT 1 |
| 144 | |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 145 | #define SUNXI_GPA_EMAC 2 |
| 146 | #define SUN6I_GPA_GMAC 2 |
| 147 | #define SUN7I_GPA_GMAC 5 |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 148 | #define SUN6I_GPA_SDC2 5 |
| 149 | #define SUN6I_GPA_SDC3 4 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 150 | |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 151 | #define SUN4I_GPB_TWI0 2 |
| 152 | #define SUN4I_GPB_TWI1 2 |
| 153 | #define SUN5I_GPB_TWI1 2 |
| 154 | #define SUN4I_GPB_TWI2 2 |
| 155 | #define SUN5I_GPB_TWI2 2 |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 156 | #define SUN4I_GPB_UART0 2 |
| 157 | #define SUN5I_GPB_UART0 2 |
Laurent Itti | 20dfe00 | 2015-05-05 17:02:00 -0700 | [diff] [blame] | 158 | #define SUN8I_GPB_UART2 2 |
Chen-Yu Tsai | 28b7192 | 2015-06-23 19:57:25 +0800 | [diff] [blame] | 159 | #define SUN8I_A33_GPB_UART0 3 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 160 | |
Karol Gugala | 7bea893 | 2015-07-23 14:33:01 +0200 | [diff] [blame] | 161 | #define SUNXI_GPC_NAND 2 |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 162 | #define SUNXI_GPC_SDC2 3 |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 163 | #define SUN6I_GPC_SDC3 4 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 164 | |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 165 | #define SUN8I_GPD_SDC1 3 |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 166 | #define SUNXI_GPD_LCD0 2 |
| 167 | #define SUNXI_GPD_LVDS0 3 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 168 | |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 169 | #define SUN5I_GPE_SDC2 3 |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 170 | #define SUN8I_GPE_TWI2 3 |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 171 | |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 172 | #define SUNXI_GPF_SDC0 2 |
| 173 | #define SUNXI_GPF_UART0 4 |
| 174 | #define SUN8I_GPF_UART0 3 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 175 | |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 176 | #define SUN4I_GPG_SDC1 4 |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 177 | #define SUN5I_GPG_SDC1 2 |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 178 | #define SUN6I_GPG_SDC1 2 |
| 179 | #define SUN8I_GPG_SDC1 2 |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 180 | #define SUN6I_GPG_TWI3 2 |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 181 | #define SUN5I_GPG_UART1 4 |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 182 | |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 183 | #define SUN4I_GPH_SDC1 5 |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 184 | #define SUN6I_GPH_TWI0 2 |
| 185 | #define SUN8I_GPH_TWI0 2 |
| 186 | #define SUN6I_GPH_TWI1 2 |
| 187 | #define SUN8I_GPH_TWI1 2 |
| 188 | #define SUN6I_GPH_TWI2 2 |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 189 | #define SUN6I_GPH_UART0 2 |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 190 | #define SUN9I_GPH_UART0 2 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 191 | |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 192 | #define SUNXI_GPI_SDC3 2 |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 193 | #define SUN7I_GPI_TWI3 3 |
| 194 | #define SUN7I_GPI_TWI4 3 |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 195 | |
Hans de Goede | 7c59038 | 2014-12-13 10:25:14 +0100 | [diff] [blame] | 196 | #define SUN6I_GPL0_R_P2WI_SCK 3 |
| 197 | #define SUN6I_GPL1_R_P2WI_SDA 3 |
Oliver Schinagl | 4f9a008 | 2013-07-25 14:07:42 +0200 | [diff] [blame] | 198 | |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 199 | #define SUN8I_GPL_R_RSB 2 |
| 200 | #define SUN8I_GPL_R_UART 2 |
Chen-Yu Tsai | 6ee6388 | 2014-10-22 16:47:47 +0800 | [diff] [blame] | 201 | |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 202 | #define SUN9I_GPN_R_RSB 3 |
Hans de Goede | 8760c91 | 2015-01-26 16:46:43 +0100 | [diff] [blame] | 203 | |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 204 | /* GPIO pin pull-up/down config */ |
| 205 | #define SUNXI_GPIO_PULL_DISABLE 0 |
| 206 | #define SUNXI_GPIO_PULL_UP 1 |
| 207 | #define SUNXI_GPIO_PULL_DOWN 2 |
| 208 | |
Paul Kocialkowski | 6604a13 | 2015-03-22 18:07:09 +0100 | [diff] [blame] | 209 | /* Virtual AXP0 GPIOs */ |
Hans de Goede | 08607d1 | 2015-04-22 11:31:22 +0200 | [diff] [blame] | 210 | #define SUNXI_GPIO_AXP0_PREFIX "AXP0-" |
| 211 | #define SUNXI_GPIO_AXP0_VBUS_DETECT 4 |
| 212 | #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 |
| 213 | #define SUNXI_GPIO_AXP0_GPIO_COUNT 6 |
Paul Kocialkowski | 6604a13 | 2015-03-22 18:07:09 +0100 | [diff] [blame] | 214 | |
Simon Glass | d862453 | 2014-10-30 20:25:47 -0600 | [diff] [blame] | 215 | void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); |
| 216 | void sunxi_gpio_set_cfgpin(u32 pin, u32 val); |
| 217 | int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 218 | int sunxi_gpio_get_cfgpin(u32 pin); |
| 219 | int sunxi_gpio_set_drv(u32 pin, u32 val); |
| 220 | int sunxi_gpio_set_pull(u32 pin, u32 val); |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 221 | int sunxi_name_to_gpio_bank(const char *name); |
Ian Campbell | af47147 | 2014-06-05 19:00:15 +0100 | [diff] [blame] | 222 | int sunxi_name_to_gpio(const char *name); |
| 223 | #define name_to_gpio(name) sunxi_name_to_gpio(name) |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 224 | |
Hans de Goede | 3ae1d13 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 225 | #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO |
| 226 | int axp_gpio_init(void); |
| 227 | #else |
| 228 | static inline int axp_gpio_init(void) { return 0; } |
| 229 | #endif |
| 230 | |
Ian Campbell | b2765ec | 2014-05-05 11:52:24 +0100 | [diff] [blame] | 231 | #endif /* _SUNXI_GPIO_H */ |