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Ian Campbellb2765ec2014-05-05 11:52:24 +01001/*
2 * (C) Copyright 2007-2012
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Tom Cubie <tangliang@allwinnertech.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef _SUNXI_GPIO_H
10#define _SUNXI_GPIO_H
11
12#include <linux/types.h>
Hans de Goede0ee72682014-10-22 16:47:45 +080013#include <asm/arch/cpu.h>
Ian Campbellb2765ec2014-05-05 11:52:24 +010014
15/*
16 * sunxi has 9 banks of gpio, they are:
17 * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
18 * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
19 * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
20 */
21
22#define SUNXI_GPIO_A 0
23#define SUNXI_GPIO_B 1
24#define SUNXI_GPIO_C 2
25#define SUNXI_GPIO_D 3
26#define SUNXI_GPIO_E 4
27#define SUNXI_GPIO_F 5
28#define SUNXI_GPIO_G 6
29#define SUNXI_GPIO_H 7
30#define SUNXI_GPIO_I 8
Hans de Goede0ee72682014-10-22 16:47:45 +080031
32/*
33 * This defines the number of GPIO banks for the _main_ GPIO controller.
34 * You should fix up the padding in struct sunxi_gpio_reg below if you
35 * change this.
36 */
Ian Campbellb2765ec2014-05-05 11:52:24 +010037#define SUNXI_GPIO_BANKS 9
38
Hans de Goede0ee72682014-10-22 16:47:45 +080039/*
40 * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
41 * at a different register offset.
42 *
43 * sun6i has 2 banks:
44 * PL0 - PL8 | PM0 - PM7
45 *
46 * sun8i has 1 bank:
47 * PL0 - PL11
48 */
49#define SUNXI_GPIO_L 11
50#define SUNXI_GPIO_M 12
51
Ian Campbellb2765ec2014-05-05 11:52:24 +010052struct sunxi_gpio {
53 u32 cfg[4];
54 u32 dat;
55 u32 drv[2];
56 u32 pull[2];
57};
58
59/* gpio interrupt control */
60struct sunxi_gpio_int {
61 u32 cfg[3];
62 u32 ctl;
63 u32 sta;
64 u32 deb; /* interrupt debounce */
65};
66
67struct sunxi_gpio_reg {
68 struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
69 u8 res[0xbc];
70 struct sunxi_gpio_int gpio_int;
71};
72
Hans de Goede0ee72682014-10-22 16:47:45 +080073#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
74 &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
75 &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
Ian Campbellb2765ec2014-05-05 11:52:24 +010076
77#define GPIO_BANK(pin) ((pin) >> 5)
78#define GPIO_NUM(pin) ((pin) & 0x1f)
79
80#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
81#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
82
83#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
84#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
85
86#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
87#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
88
89/* GPIO bank sizes */
90#define SUNXI_GPIO_A_NR 32
91#define SUNXI_GPIO_B_NR 32
92#define SUNXI_GPIO_C_NR 32
93#define SUNXI_GPIO_D_NR 32
94#define SUNXI_GPIO_E_NR 32
95#define SUNXI_GPIO_F_NR 32
96#define SUNXI_GPIO_G_NR 32
97#define SUNXI_GPIO_H_NR 32
98#define SUNXI_GPIO_I_NR 32
Hans de Goede0ee72682014-10-22 16:47:45 +080099#define SUNXI_GPIO_L_NR 32
100#define SUNXI_GPIO_M_NR 32
Ian Campbellb2765ec2014-05-05 11:52:24 +0100101
102#define SUNXI_GPIO_NEXT(__gpio) \
103 ((__gpio##_START) + (__gpio##_NR) + 0)
104
105enum sunxi_gpio_number {
106 SUNXI_GPIO_A_START = 0,
107 SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
108 SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
109 SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
110 SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
111 SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
112 SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
113 SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
114 SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
Hans de Goede0ee72682014-10-22 16:47:45 +0800115 SUNXI_GPIO_L_START = 352,
116 SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
Hans de Goede1fc9c4a2014-12-24 19:34:38 +0100117 SUNXI_GPIO_AXP0_START = 1024,
Ian Campbellb2765ec2014-05-05 11:52:24 +0100118};
119
120/* SUNXI GPIO number definitions */
121#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
122#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
123#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
124#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
125#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
126#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
127#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
128#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
129#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
Hans de Goede0ee72682014-10-22 16:47:45 +0800130#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
131#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
Ian Campbellb2765ec2014-05-05 11:52:24 +0100132
Hans de Goede1fc9c4a2014-12-24 19:34:38 +0100133#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
134
Ian Campbellb2765ec2014-05-05 11:52:24 +0100135/* GPIO pin function config */
136#define SUNXI_GPIO_INPUT 0
137#define SUNXI_GPIO_OUTPUT 1
138
139#define SUNXI_GPA0_EMAC 2
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100140#define SUN6I_GPA0_GMAC 2
Ian Campbellb2765ec2014-05-05 11:52:24 +0100141#define SUN7I_GPA0_GMAC 5
142
143#define SUNXI_GPB0_TWI0 2
144
145#define SUN4I_GPB22_UART0_TX 2
146#define SUN4I_GPB23_UART0_RX 2
147
148#define SUN5I_GPB19_UART0_TX 2
149#define SUN5I_GPB20_UART0_RX 2
150
Ian Campbellb2765ec2014-05-05 11:52:24 +0100151#define SUNXI_GPC6_SDC2 3
152
153#define SUNXI_GPF0_SDC0 2
154
155#define SUNXI_GPF2_SDC0 2
Chen-Yu Tsaia9272412014-10-22 16:47:41 +0800156
Ian Campbell8f32aaa2014-10-24 21:20:47 +0100157#ifdef CONFIG_MACH_SUN8I
Chen-Yu Tsaia9272412014-10-22 16:47:41 +0800158#define SUNXI_GPF2_UART0_TX 3
159#define SUNXI_GPF4_UART0_RX 3
160#else
Ian Campbellb2765ec2014-05-05 11:52:24 +0100161#define SUNXI_GPF2_UART0_TX 4
162#define SUNXI_GPF4_UART0_RX 4
Chen-Yu Tsaia9272412014-10-22 16:47:41 +0800163#endif
Ian Campbellb2765ec2014-05-05 11:52:24 +0100164
165#define SUN4I_GPG0_SDC1 4
166
Hans de Goedee11b7842014-12-22 11:39:57 +0100167#define SUN5I_GPG3_SDC1 2
168
169#define SUN5I_GPG3_UART1_TX 4
170#define SUN5I_GPG4_UART1_RX 4
171
Ian Campbellb2765ec2014-05-05 11:52:24 +0100172#define SUN4I_GPH22_SDC1 5
173
Chen-Yu Tsai086ef822014-10-03 20:16:27 +0800174#define SUN6I_GPH20_UART0_TX 2
175#define SUN6I_GPH21_UART0_RX 2
176
Ian Campbellb2765ec2014-05-05 11:52:24 +0100177#define SUN4I_GPI4_SDC3 2
178
Hans de Goede7c590382014-12-13 10:25:14 +0100179#define SUN6I_GPL0_R_P2WI_SCK 3
180#define SUN6I_GPL1_R_P2WI_SDA 3
Oliver Schinagl4f9a0082013-07-25 14:07:42 +0200181
Hans de Goede699415b2014-11-29 13:38:35 +0100182#define SUN8I_GPL0_R_RSB_SCK 2
183#define SUN8I_GPL1_R_RSB_SDA 2
Chen-Yu Tsai6ee63882014-10-22 16:47:47 +0800184#define SUN8I_GPL2_R_UART_TX 2
185#define SUN8I_GPL3_R_UART_RX 2
186
Ian Campbellb2765ec2014-05-05 11:52:24 +0100187/* GPIO pin pull-up/down config */
188#define SUNXI_GPIO_PULL_DISABLE 0
189#define SUNXI_GPIO_PULL_UP 1
190#define SUNXI_GPIO_PULL_DOWN 2
191
Simon Glassd8624532014-10-30 20:25:47 -0600192void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
193void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
194int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
Ian Campbellb2765ec2014-05-05 11:52:24 +0100195int sunxi_gpio_get_cfgpin(u32 pin);
196int sunxi_gpio_set_drv(u32 pin, u32 val);
197int sunxi_gpio_set_pull(u32 pin, u32 val);
Ian Campbellaf471472014-06-05 19:00:15 +0100198int sunxi_name_to_gpio(const char *name);
199#define name_to_gpio(name) sunxi_name_to_gpio(name)
Ian Campbellb2765ec2014-05-05 11:52:24 +0100200
201#endif /* _SUNXI_GPIO_H */