blob: 2051207f0ba93a11a4b6415d8825e8a3375266b8 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Main sandbox devicetree
4 */
5
Simon Glass66c164b2014-02-26 15:59:14 -07006/dts-v1/;
7
Simon Glass07bb5e72019-05-18 11:59:48 -06008#include <config.h>
9
Simon Glass66c164b2014-02-26 15:59:14 -070010/ {
Simon Glassfd91fc92014-10-13 23:41:48 -060011 #address-cells = <1>;
Simon Glassf905be82015-03-05 12:25:13 -070012 #size-cells = <1>;
Simon Glass00c34d5b2017-06-15 21:37:53 -060013 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +010014 compatible = "sandbox";
Simon Glassfd91fc92014-10-13 23:41:48 -060015
Simon Glass70778bc2015-03-05 12:25:26 -070016 aliases {
Simon Glass72138b92015-04-20 12:37:28 -060017 i2c0 = &i2c_0;
Tom Rini4a3ca482020-02-11 12:41:23 -050018 pci0 = &pcic;
Simon Glass72138b92015-04-20 12:37:28 -060019 rtc0 = &rtc_0;
Mario Six95922152018-08-09 14:51:19 +020020 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -060021 spi0 = &spi;
Simon Glass70778bc2015-03-05 12:25:26 -070022 };
23
Simon Glass5e135d32022-10-20 18:23:15 -060024 binman: binman {
25 };
26
Simon Glass07bb5e72019-05-18 11:59:48 -060027 memory {
28 reg = <0 CONFIG_SYS_SDRAM_SIZE>;
29 };
30
Heinrich Schuchardtad935702020-03-14 12:13:39 +010031 reserved-memory {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 ranges;
35
36 reservation_test0 {
37 size = <0x4000>;
38 alignment = <0x2000>;
39 };
40
41 reservation_test1: restest@a000 {
42 reg = <0x00d0a000 0x2000>;
43 };
44
45 reservation_test2: restest@7000 {
46 reg = <0x00d07000 0x1000>;
47 };
48 };
49
Simon Glass699c9ca2018-10-01 12:22:08 -060050 cros_ec: cros-ec {
Simon Glass73f220c2015-03-26 09:29:39 -060051 reg = <0 0>;
Simon Glasse98524a2020-12-19 10:39:56 -070052 u-boot,dm-pre-proper;
Simon Glass73f220c2015-03-26 09:29:39 -060053 compatible = "google,cros-ec-sandbox";
Simon Glass1f6acb52014-02-27 13:25:59 -070054 };
55
Yannick Fertré9712c822019-10-07 15:29:05 +020056 dsi_host: dsi_host {
57 compatible = "sandbox,dsi-host";
58 status = "okay";
59 };
60
Joe Hershberger89590c82018-07-02 14:47:54 -050061 ethrawbus {
62 compatible = "sandbox,eth-raw-bus";
63 skip-localhost = <0>;
64 };
65
Simon Glass45ab0082015-05-22 15:42:16 -060066 eth@10002000 {
67 compatible = "sandbox,eth";
68 reg = <0x10002000 0x1000>;
Simon Glass45ab0082015-05-22 15:42:16 -060069 };
70
Simon Glass72138b92015-04-20 12:37:28 -060071 i2c_0: i2c@0 {
Simon Glass4f46a592014-12-10 08:55:53 -070072 #address-cells = <1>;
73 #size-cells = <0>;
Simon Glassf905be82015-03-05 12:25:13 -070074 reg = <0 0>;
Simon Glass4f46a592014-12-10 08:55:53 -070075 compatible = "sandbox,i2c";
76 clock-frequency = <400000>;
Masahiro Yamada0b53a752015-08-27 12:44:30 +090077 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glass4d4558e2020-10-03 11:31:36 -060079 u-boot,dm-pre-reloc;
Simon Glassfefc7ba2017-04-10 11:34:51 -060080 };
81
Tom Rini4a3ca482020-02-11 12:41:23 -050082 pcic: pci@0 {
Simon Glass70778bc2015-03-05 12:25:26 -070083 compatible = "sandbox,pci";
84 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -050085 bus-range = <0x00 0xff>;
Simon Glass70778bc2015-03-05 12:25:26 -070086 #address-cells = <3>;
87 #size-cells = <2>;
88 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
89 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass70778bc2015-03-05 12:25:26 -070090 };
91
Simon Glassed3698a2019-05-18 11:59:42 -060092 spi: spi@0 {
Simon Glasse98524a2020-12-19 10:39:56 -070093 u-boot,dm-pre-proper;
Simon Glass45ab0082015-05-22 15:42:16 -060094 #address-cells = <1>;
95 #size-cells = <0>;
96 reg = <0 0>;
97 compatible = "sandbox,spi";
98 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger6ab76992015-03-22 17:09:13 -050099 };
Simon Glass66c164b2014-02-26 15:59:14 -0700100};
Simon Glass73f220c2015-03-26 09:29:39 -0600101
Simon Glass28db4692019-05-18 11:59:41 -0600102#include "sandbox.dtsi"
Simon Glass73f220c2015-03-26 09:29:39 -0600103#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200104#include "sandbox_pmic.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -0600105
106#ifdef CONFIG_SANDBOX_VPL
107#include "sandbox_vpl.dtsi"
108#endif