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git01.mediatek.com / filogic / uboot / aec069e160b0d52a2882161dc28efb40d68b54c3 / . / arch / riscv / dts / microchip-mpfs-icicle-kit.dts
blob: 762dcfc69447e947f48499fe8fcf66734a25a93c [file] [log] [blame]
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]3 * Copyright (C) 2021-2022 Microchip Technology Inc.
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]6
7/dts-v1/;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]8
9#include "microchip-mpfs.dtsi"
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]10
11/* Clock frequency (in Hz) of the rtcclk */
12#define RTCCLK_FREQ 1000000
13
14/ {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]15 model = "Microchip PolarFire-SoC Icicle Kit";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]16 compatible = "microchip,mpfs-icicle-reference-rtlv2210",
17 "microchip,mpfs-icicle-kit", "microchip,mpfs";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]18
19 aliases {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]20 serial1 = &uart1;
21 ethernet0 = &mac1;
Padmarao Begarida2a6d02022-10-27 11:32:00 +0530[diff] [blame]22 spi0 = &qspi;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]23 };
24
25 chosen {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]26 stdout-path = "serial1";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]27 };
28
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]29 cpus {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]30 timebase-frequency = <RTCCLK_FREQ>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]31 };
32
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]33 ddrc_cache_lo: memory@80000000 {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]34 device_type = "memory";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]35 reg = <0x0 0x80000000 0x0 0x40000000>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]36 status = "okay";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]37 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]38
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]39 ddrc_cache_hi: memory@1040000000 {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]40 device_type = "memory";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]41 reg = <0x10 0x40000000 0x0 0x40000000>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]42 status = "okay";
43 };
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]44
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
48 ranges;
49
50 hss_payload: region@BFC00000 {
51 reg = <0x0 0xBFC00000 0x0 0x400000>;
52 no-map;
53 };
54 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]55};
56
57&uart1 {
58 status = "okay";
59};
60
61&mmc {
62 status = "okay";
63
64 bus-width = <4>;
65 disable-wp;
66 cap-mmc-highspeed;
67 cap-sd-highspeed;
68 card-detect-delay = <200>;
69 mmc-ddr-1_8v;
70 mmc-hs200-1_8v;
71 sd-uhs-sdr12;
72 sd-uhs-sdr25;
73 sd-uhs-sdr50;
74 sd-uhs-sdr104;
75};
76
77&i2c1 {
78 status = "okay";
79 clock-frequency = <100000>;
80
81 pac193x: pac193x@10 {
82 compatible = "microchip,pac1934";
83 reg = <0x10>;
84 samp-rate = <64>;
85 status = "okay";
86 ch1: channel0 {
87 uohms-shunt-res = <10000>;
88 rail-name = "VDDREG";
89 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]90 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]91 ch2: channel1 {
92 uohms-shunt-res = <10000>;
93 rail-name = "VDDA25";
94 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]95 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]96 ch3: channel2 {
97 uohms-shunt-res = <10000>;
98 rail-name = "VDD25";
99 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]100 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]101 ch4: channel3 {
102 uohms-shunt-res = <10000>;
103 rail-name = "VDDA_REG";
104 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]105 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]106 };
107};
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]108
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]109&mac1 {
110 status = "okay";
111 phy-mode = "sgmii";
112 phy-handle = <&phy1>;
113 phy1: ethernet-phy@9 {
114 reg = <9>;
115 ti,fifo-depth = <0x1>;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]116 };
117};
Padmarao Begarida2a6d02022-10-27 11:32:00 +0530[diff] [blame]118
119&qspi {
120 status = "okay";
121 num-cs = <1>;
122
123 flash0: flash@0 {
124 compatible = "spi-nand";
125 reg = <0x0>;
126 spi-tx-bus-width = <4>;
127 spi-rx-bus-width = <4>;
128 spi-max-frequency = <20000000>;
129 spi-cpol;
130 spi-cpha;
131 };
132};