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git01.mediatek.com / filogic / uboot / ae17df27d9f6782a37be392f73eadad34689a976 / . / arch / arm / cpu / arm926ejs / start.S
blob: f05113da9df21ff5a28ebc644fc83bf5399f8606 [file] [log] [blame]
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]1/*
2 * armboot - Startup Code for ARM926EJS CPU-core
3 *
4 * Copyright (c) 2003 Texas Instruments
5 *
wdenke3a06802004-06-06 23:13:55 +0000[diff] [blame]6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]7 *
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundelf1b3f2b2009-05-13 10:54:10 +0200[diff] [blame]10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
Albert ARIBAUD340983d2011-04-22 19:41:02 +0200[diff] [blame]13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]14 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]15 * SPDX-License-Identifier: GPL-2.0+
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]16 */
17
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]18#include <asm-offsets.h>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]19#include <config.h>
Wolfgang Denk66e8d442009-07-24 00:17:48 +0200[diff] [blame]20#include <common.h>
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]21
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]22/*
23 *************************************************************************
24 *
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]25 * Startup Code (reset vector)
26 *
27 * do important init only if we don't start from memory!
28 * setup Memory and board specific bits prior to relocation.
29 * relocate armboot to ram
30 * setup stack
31 *
32 *************************************************************************
33 */
34
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200[diff] [blame]35 .globl reset
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]36
37reset:
38 /*
39 * set the cpu to SVC32 mode
40 */
41 mrs r0,cpsr
42 bic r0,r0,#0x1f
43 orr r0,r0,#0xd3
44 msr cpsr,r0
45
46 /*
47 * we do sys-critical inits only at reboot,
48 * not when booting from ram!
49 */
Christian Riesch11bf5762012-02-02 00:44:37 +0000[diff] [blame]50#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]51 bl cpu_init_crit
Christian Riesch11bf5762012-02-02 00:44:37 +0000[diff] [blame]52#endif
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]53
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]54 bl _main
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200[diff] [blame]55
56/*------------------------------------------------------------------------------*/
57
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000[diff] [blame]58 .globl c_runtime_cpu_setup
59c_runtime_cpu_setup:
60
61 bx lr
62
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]63/*
64 *************************************************************************
65 *
66 * CPU_init_critical registers
67 *
68 * setup important registers
69 * setup memory timing
70 *
71 *************************************************************************
72 */
Christian Riesch11bf5762012-02-02 00:44:37 +0000[diff] [blame]73#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]74cpu_init_crit:
75 /*
Sughosh Ganu4cb71862012-02-02 00:44:38 +0000[diff] [blame]76 * flush D cache before disabling it
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]77 */
78 mov r0, #0
Sughosh Ganu4cb71862012-02-02 00:44:38 +0000[diff] [blame]79flush_dcache:
80 mrc p15, 0, r15, c7, c10, 3
81 bne flush_dcache
82
83 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
84 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]85
86 /*
Christian Riescha927d262012-02-02 00:44:40 +0000[diff] [blame]87 * disable MMU and D cache
88 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]89 */
90 mrc p15, 0, r0, c1, c0, 0
Christian Riesch48c2d6d2012-02-02 00:44:39 +0000[diff] [blame]91 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]92 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
Christian Riesch48c2d6d2012-02-02 00:44:39 +0000[diff] [blame]93#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
94 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
95#else
96 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
97#endif
Yuichiro Goto8d4b7e92016-02-25 10:23:34 +0900[diff] [blame]98 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
Christian Riescha927d262012-02-02 00:44:40 +0000[diff] [blame]99#ifndef CONFIG_SYS_ICACHE_OFF
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]100 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
Christian Riescha927d262012-02-02 00:44:40 +0000[diff] [blame]101#endif
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]102 mcr p15, 0, r0, c1, c0, 0
103
104 /*
105 * Go setup Memory and board specific bits prior to relocation.
106 */
107 mov ip, lr /* perserve link reg across call */
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200[diff] [blame]108 bl lowlevel_init /* go setup pll,mux,memory */
wdenk7eaacc52003-08-29 22:00:43 +0000[diff] [blame]109 mov lr, ip /* restore link */
Heiko Schocherc8a6d752011-11-09 20:06:23 +0000[diff] [blame]110 mov pc, lr /* back to my caller */
Christian Riesch11bf5762012-02-02 00:44:37 +0000[diff] [blame]111#endif /* CONFIG_SKIP_LOWLEVEL_INIT */