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wdenk7eaacc52003-08-29 22:00:43 +00001/*
2 * armboot - Startup Code for ARM926EJS CPU-core
3 *
4 * Copyright (c) 2003 Texas Instruments
5 *
wdenke3a06802004-06-06 23:13:55 +00006 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
wdenk7eaacc52003-08-29 22:00:43 +00007 *
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundelf1b3f2b2009-05-13 10:54:10 +020010 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
wdenk7eaacc52003-08-29 22:00:43 +000011 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
Albert Aribaud6d1fcb12010-10-11 13:13:28 +020013 * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
wdenk7eaacc52003-08-29 22:00:43 +000014 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
Wolfgang Denk0191e472010-10-26 14:34:52 +020034#include <asm-offsets.h>
wdenk7eaacc52003-08-29 22:00:43 +000035#include <config.h>
Wolfgang Denk66e8d442009-07-24 00:17:48 +020036#include <common.h>
wdenk7eaacc52003-08-29 22:00:43 +000037#include <version.h>
38
39#if defined(CONFIG_OMAP1610)
40#include <./configs/omap1510.h>
wdenke3a06802004-06-06 23:13:55 +000041#elif defined(CONFIG_OMAP730)
42#include <./configs/omap730.h>
wdenk7eaacc52003-08-29 22:00:43 +000043#endif
44
45/*
46 *************************************************************************
47 *
48 * Jump vector table as in table 3.1 in [1]
49 *
50 *************************************************************************
51 */
52
53
54.globl _start
55_start:
56 b reset
John Rigbya9f3cf52010-01-25 23:12:52 -070057#ifdef CONFIG_PRELOADER
58/* No exception handlers in preloader */
59 ldr pc, _hang
60 ldr pc, _hang
61 ldr pc, _hang
62 ldr pc, _hang
63 ldr pc, _hang
64 ldr pc, _hang
65 ldr pc, _hang
66
67_hang:
68 .word do_hang
69/* pad to 64 byte boundary */
70 .word 0x12345678
71 .word 0x12345678
72 .word 0x12345678
73 .word 0x12345678
74 .word 0x12345678
75 .word 0x12345678
76 .word 0x12345678
77#else
wdenk7eaacc52003-08-29 22:00:43 +000078 ldr pc, _undefined_instruction
79 ldr pc, _software_interrupt
80 ldr pc, _prefetch_abort
81 ldr pc, _data_abort
82 ldr pc, _not_used
83 ldr pc, _irq
84 ldr pc, _fiq
85
86_undefined_instruction:
87 .word undefined_instruction
88_software_interrupt:
89 .word software_interrupt
90_prefetch_abort:
91 .word prefetch_abort
92_data_abort:
93 .word data_abort
94_not_used:
95 .word not_used
96_irq:
97 .word irq
98_fiq:
99 .word fiq
100
John Rigbya9f3cf52010-01-25 23:12:52 -0700101#endif /* CONFIG_PRELOADER */
wdenk7eaacc52003-08-29 22:00:43 +0000102 .balignl 16,0xdeadbeef
103
104
105/*
106 *************************************************************************
107 *
108 * Startup Code (reset vector)
109 *
110 * do important init only if we don't start from memory!
111 * setup Memory and board specific bits prior to relocation.
112 * relocate armboot to ram
113 * setup stack
114 *
115 *************************************************************************
116 */
117
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200118.globl _TEXT_BASE
wdenk7eaacc52003-08-29 22:00:43 +0000119_TEXT_BASE:
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200120 .word CONFIG_SYS_TEXT_BASE
wdenk7eaacc52003-08-29 22:00:43 +0000121
wdenk7eaacc52003-08-29 22:00:43 +0000122/*
wdenk927034e2004-02-08 19:38:38 +0000123 * These are defined in the board-specific linker script.
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200124 * Subtracting _start from them lets the linker put their
125 * relative position in the executable instead of leaving
126 * them null.
wdenk7eaacc52003-08-29 22:00:43 +0000127 */
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200128.globl _bss_start_ofs
129_bss_start_ofs:
130 .word __bss_start - _start
wdenk927034e2004-02-08 19:38:38 +0000131
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200132.globl _bss_end_ofs
133_bss_end_ofs:
134 .word _end - _start
wdenk7eaacc52003-08-29 22:00:43 +0000135
wdenk7eaacc52003-08-29 22:00:43 +0000136#ifdef CONFIG_USE_IRQ
137/* IRQ stack memory (calculated at run-time) */
138.globl IRQ_STACK_START
139IRQ_STACK_START:
140 .word 0x0badc0de
141
142/* IRQ stack memory (calculated at run-time) */
143.globl FIQ_STACK_START
144FIQ_STACK_START:
145 .word 0x0badc0de
146#endif
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200147
148#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
149/* IRQ stack memory (calculated at run-time) + 8 bytes */
150.globl IRQ_STACK_START_IN
151IRQ_STACK_START_IN:
152 .word 0x0badc0de
153
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200154/*
155 * the actual reset code
156 */
157
158reset:
159 /*
160 * set the cpu to SVC32 mode
161 */
162 mrs r0,cpsr
163 bic r0,r0,#0x1f
164 orr r0,r0,#0xd3
165 msr cpsr,r0
166
167 /*
168 * we do sys-critical inits only at reboot,
169 * not when booting from ram!
170 */
171#ifndef CONFIG_SKIP_LOWLEVEL_INIT
172 bl cpu_init_crit
173#endif
174
175/* Set stackpointer in internal RAM to call board_init_f */
176call_board_init_f:
177 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
178 ldr r0,=0x00000000
179 bl board_init_f
180
181/*------------------------------------------------------------------------------*/
182
183/*
184 * void relocate_code (addr_sp, gd, addr_moni)
185 *
186 * This "function" does not return, instead it continues in RAM
187 * after relocating the monitor code.
188 *
189 */
190 .globl relocate_code
191relocate_code:
192 mov r4, r0 /* save addr_sp */
193 mov r5, r1 /* save addr of gd */
194 mov r6, r2 /* save addr of destination */
195 mov r7, r2 /* save addr of destination */
196
197 /* Set up the stack */
198stack_setup:
199 mov sp, r4
200
201 adr r0, _start
202 ldr r2, _TEXT_BASE
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200203 ldr r3, _bss_start_ofs
204 add r2, r0, r3 /* r2 <- source end address */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200205 cmp r0, r6
206 beq clear_bss
207
208#ifndef CONFIG_SKIP_RELOCATE_UBOOT
209copy_loop:
210 ldmia r0!, {r9-r10} /* copy from source address [r0] */
211 stmia r6!, {r9-r10} /* copy to target address [r1] */
Albert Aribaud0668d162010-10-05 16:06:39 +0200212 cmp r0, r2 /* until source end address [r2] */
213 blo copy_loop
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200214
215#ifndef CONFIG_PRELOADER
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200216 /*
217 * fix .rel.dyn relocations
218 */
219 ldr r0, _TEXT_BASE /* r0 <- Text base */
220 sub r9, r7, r0 /* r9 <- relocation offset */
221 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
222 add r10, r10, r0 /* r10 <- sym table in FLASH */
223 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
224 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
225 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
226 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200227fixloop:
Gray Remlinea4b2c82010-10-24 16:18:31 +0100228 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
229 add r0, r0, r9 /* r0 <- location to fix up in RAM */
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200230 ldr r1, [r2, #4]
231 and r8, r1, #0xff
Gray Remlinea4b2c82010-10-24 16:18:31 +0100232 cmp r8, #23 /* relative fixup? */
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200233 beq fixrel
Gray Remlinea4b2c82010-10-24 16:18:31 +0100234 cmp r8, #2 /* absolute fixup? */
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200235 beq fixabs
236 /* ignore unknown type of fixup */
237 b fixnext
238fixabs:
239 /* absolute fix: set location to (offset) symbol value */
240 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
241 add r1, r10, r1 /* r1 <- address of symbol in table */
242 ldr r1, [r1, #4] /* r1 <- symbol value */
243 add r1, r9 /* r1 <- relocated sym addr */
244 b fixnext
245fixrel:
246 /* relative fix: increase location by offset */
247 ldr r1, [r0]
248 add r1, r1, r9
249fixnext:
250 str r1, [r0]
Gray Remlinea4b2c82010-10-24 16:18:31 +0100251 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200252 cmp r2, r3
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200253 blo fixloop
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200254#endif
255#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
wdenk7eaacc52003-08-29 22:00:43 +0000256
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200257clear_bss:
258#ifndef CONFIG_PRELOADER
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200259 ldr r0, _bss_start_ofs
260 ldr r1, _bss_end_ofs
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200261 ldr r3, _TEXT_BASE /* Text base */
262 mov r4, r7 /* reloc addr */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200263 add r0, r0, r4
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200264 add r1, r1, r4
265 mov r2, #0x00000000 /* clear */
266
267clbss_l:str r2, [r0] /* clear loop... */
268 add r0, r0, #4
269 cmp r0, r1
270 bne clbss_l
wdenk7eaacc52003-08-29 22:00:43 +0000271
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200272 bl coloured_LED_init
273 bl red_LED_on
274#endif
275
276/*
277 * We are done. Do not return, instead branch to second part of board
278 * initialization, now running from RAM.
279 */
280#ifdef CONFIG_NAND_SPL
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200281 ldr r0, _nand_boot_ofs
Heiko Schocher0a2817f2010-10-11 14:08:14 +0200282 mov pc, r0
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200283
Heiko Schocher0a2817f2010-10-11 14:08:14 +0200284_nand_boot_ofs:
285 .word nand_boot
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200286#else
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200287 ldr r0, _board_init_r_ofs
288 adr r1, _start
289 add r0, r0, r1
290 add lr, r0, r9
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200291 /* setup parameters for board_init_r */
292 mov r0, r5 /* gd_t */
293 mov r1, r7 /* dest_addr */
294 /* jump to it ... */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200295 mov pc, lr
296
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200297_board_init_r_ofs:
298 .word board_init_r - _start
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200299#endif
300
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200301_rel_dyn_start_ofs:
302 .word __rel_dyn_start - _start
303_rel_dyn_end_ofs:
304 .word __rel_dyn_end - _start
305_dynsym_start_ofs:
306 .word __dynsym_start - _start
307
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200308#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
wdenk7eaacc52003-08-29 22:00:43 +0000309/*
310 * the actual reset code
311 */
312
313reset:
314 /*
315 * set the cpu to SVC32 mode
316 */
317 mrs r0,cpsr
318 bic r0,r0,#0x1f
319 orr r0,r0,#0xd3
320 msr cpsr,r0
321
wdenk7eaacc52003-08-29 22:00:43 +0000322 /*
wdenkc0aa5c52003-12-06 19:49:23 +0000323 * we do sys-critical inits only at reboot,
324 * not when booting from ram!
wdenk7eaacc52003-08-29 22:00:43 +0000325 */
wdenk3d3d99f2005-04-04 12:44:11 +0000326#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkc0aa5c52003-12-06 19:49:23 +0000327 bl cpu_init_crit
328#endif
329
wdenk3d3d99f2005-04-04 12:44:11 +0000330#ifndef CONFIG_SKIP_RELOCATE_UBOOT
wdenkc0aa5c52003-12-06 19:49:23 +0000331relocate: /* relocate U-Boot to RAM */
332 adr r0, _start /* r0 <- current position of code */
333 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
334 cmp r0, r1 /* don't reloc during debug */
335 beq stack_setup
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200336 ldr r3, _bss_start_ofs /* r3 <- _bss_start - _start */
337 add r2, r0, r3 /* r2 <- source end address */
wdenk7eaacc52003-08-29 22:00:43 +0000338
wdenk7eaacc52003-08-29 22:00:43 +0000339copy_loop:
wdenkc0aa5c52003-12-06 19:49:23 +0000340 ldmia r0!, {r3-r10} /* copy from source address [r0] */
341 stmia r1!, {r3-r10} /* copy to target address [r1] */
Albert Aribaud0668d162010-10-05 16:06:39 +0200342 cmp r0, r2 /* until source end address [r2] */
343 blo copy_loop
wdenk3d3d99f2005-04-04 12:44:11 +0000344#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
wdenk7eaacc52003-08-29 22:00:43 +0000345
wdenkc0aa5c52003-12-06 19:49:23 +0000346 /* Set up the stack */
347stack_setup:
348 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
John Rigbya9f3cf52010-01-25 23:12:52 -0700349 sub sp, r0, #128 /* leave 32 words for abort-stack */
350#ifndef CONFIG_PRELOADER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200351 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200352 sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
wdenkc0aa5c52003-12-06 19:49:23 +0000353#ifdef CONFIG_USE_IRQ
354 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
355#endif
John Rigbya9f3cf52010-01-25 23:12:52 -0700356#endif /* CONFIG_PRELOADER */
wdenkc0aa5c52003-12-06 19:49:23 +0000357 sub sp, r0, #12 /* leave 3 words for abort-stack */
Vitaly Kuzmichev9c2cec42010-06-15 22:18:11 +0400358 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
wdenk7eaacc52003-08-29 22:00:43 +0000359
wdenk927034e2004-02-08 19:38:38 +0000360clear_bss:
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200361 adr r2, _start
362 ldr r0, _bss_start_ofs /* find start of bss segment */
363 add r0, r0, r2
364 ldr r1, _bss_end_ofs /* stop here */
365 add r1, r1, r2
Wolfgang Denka1be4762008-05-20 16:00:29 +0200366 mov r2, #0x00000000 /* clear */
wdenk927034e2004-02-08 19:38:38 +0000367
John Rigbya9f3cf52010-01-25 23:12:52 -0700368#ifndef CONFIG_PRELOADER
wdenk927034e2004-02-08 19:38:38 +0000369clbss_l:str r2, [r0] /* clear loop... */
370 add r0, r0, #4
371 cmp r0, r1
Albert Aribaud0668d162010-10-05 16:06:39 +0200372 blo clbss_l
wdenk927034e2004-02-08 19:38:38 +0000373
Stelian Popd1aea1c2008-01-30 21:15:54 +0000374 bl coloured_LED_init
375 bl red_LED_on
John Rigbya9f3cf52010-01-25 23:12:52 -0700376#endif /* CONFIG_PRELOADER */
Stelian Popd1aea1c2008-01-30 21:15:54 +0000377
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200378 ldr r0, _start_armboot_ofs
379 adr r1, _start
380 add r0, r0, r1
381 ldr pc, r0
wdenk7eaacc52003-08-29 22:00:43 +0000382
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200383_start_armboot_ofs:
John Rigbya9f3cf52010-01-25 23:12:52 -0700384#ifdef CONFIG_NAND_SPL
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200385 .word nand_boot - _start
John Rigbya9f3cf52010-01-25 23:12:52 -0700386#else
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200387 .word start_armboot - _start
John Rigbya9f3cf52010-01-25 23:12:52 -0700388#endif /* CONFIG_NAND_SPL */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200389#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
wdenk7eaacc52003-08-29 22:00:43 +0000390
391/*
392 *************************************************************************
393 *
394 * CPU_init_critical registers
395 *
396 * setup important registers
397 * setup memory timing
398 *
399 *************************************************************************
400 */
Stelian Pop72a6f142008-01-19 21:09:35 +0000401#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenk7eaacc52003-08-29 22:00:43 +0000402cpu_init_crit:
403 /*
404 * flush v4 I/D caches
405 */
406 mov r0, #0
407 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
408 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
409
410 /*
411 * disable MMU stuff and caches
412 */
413 mrc p15, 0, r0, c1, c0, 0
414 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
415 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
416 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
417 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
418 mcr p15, 0, r0, c1, c0, 0
419
420 /*
421 * Go setup Memory and board specific bits prior to relocation.
422 */
423 mov ip, lr /* perserve link reg across call */
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200424 bl lowlevel_init /* go setup pll,mux,memory */
wdenk7eaacc52003-08-29 22:00:43 +0000425 mov lr, ip /* restore link */
426 mov pc, lr /* back to my caller */
Stelian Pop72a6f142008-01-19 21:09:35 +0000427#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
428
John Rigbya9f3cf52010-01-25 23:12:52 -0700429#ifndef CONFIG_PRELOADER
wdenk7eaacc52003-08-29 22:00:43 +0000430/*
431 *************************************************************************
432 *
433 * Interrupt handling
434 *
435 *************************************************************************
436 */
437
438@
439@ IRQ stack frame.
440@
441#define S_FRAME_SIZE 72
442
443#define S_OLD_R0 68
444#define S_PSR 64
445#define S_PC 60
446#define S_LR 56
447#define S_SP 52
448
449#define S_IP 48
450#define S_FP 44
451#define S_R10 40
452#define S_R9 36
453#define S_R8 32
454#define S_R7 28
455#define S_R6 24
456#define S_R5 20
457#define S_R4 16
458#define S_R3 12
459#define S_R2 8
460#define S_R1 4
461#define S_R0 0
462
463#define MODE_SVC 0x13
464#define I_BIT 0x80
465
466/*
467 * use bad_save_user_regs for abort/prefetch/undef/swi ...
468 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
469 */
470
471 .macro bad_save_user_regs
472 @ carve out a frame on current user stack
473 sub sp, sp, #S_FRAME_SIZE
474 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200475#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200476 adr r2, _start
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200477 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
Wolfgang Denk0191e472010-10-26 14:34:52 +0200478 sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200479#else
480 ldr r2, IRQ_STACK_START_IN
481#endif
wdenk7eaacc52003-08-29 22:00:43 +0000482 @ get values for "aborted" pc and cpsr (into parm regs)
483 ldmia r2, {r2 - r3}
484 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
485 add r5, sp, #S_SP
486 mov r1, lr
487 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
488 mov r0, sp @ save current stack into r0 (param register)
489 .endm
490
491 .macro irq_save_user_regs
492 sub sp, sp, #S_FRAME_SIZE
493 stmia sp, {r0 - r12} @ Calling r0-r12
494 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
495 add r8, sp, #S_PC
496 stmdb r8, {sp, lr}^ @ Calling SP, LR
497 str lr, [r8, #0] @ Save calling PC
498 mrs r6, spsr
499 str r6, [r8, #4] @ Save CPSR
500 str r0, [r8, #8] @ Save OLD_R0
501 mov r0, sp
502 .endm
503
504 .macro irq_restore_user_regs
505 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
506 mov r0, r0
507 ldr lr, [sp, #S_PC] @ Get PC
508 add sp, sp, #S_FRAME_SIZE
509 subs pc, lr, #4 @ return & move spsr_svc into cpsr
510 .endm
511
512 .macro get_bad_stack
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200513#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
Albert Aribaud6d1fcb12010-10-11 13:13:28 +0200514 adr r13, _start @ setup our mode stack
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200515 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
Wolfgang Denk0191e472010-10-26 14:34:52 +0200516 sub r13, r13, #(GENERATED_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200517#else
518 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
519#endif
wdenk7eaacc52003-08-29 22:00:43 +0000520
521 str lr, [r13] @ save caller lr in position 0 of saved stack
522 mrs lr, spsr @ get the spsr
523 str lr, [r13, #4] @ save spsr in position 1 of saved stack
524 mov r13, #MODE_SVC @ prepare SVC-Mode
525 @ msr spsr_c, r13
526 msr spsr, r13 @ switch modes, make sure moves will execute
527 mov lr, pc @ capture return pc
528 movs pc, lr @ jump to next instruction & switch modes.
529 .endm
530
531 .macro get_irq_stack @ setup IRQ stack
532 ldr sp, IRQ_STACK_START
533 .endm
534
535 .macro get_fiq_stack @ setup FIQ stack
536 ldr sp, FIQ_STACK_START
537 .endm
John Rigbya9f3cf52010-01-25 23:12:52 -0700538#endif /* CONFIG_PRELOADER */
wdenk7eaacc52003-08-29 22:00:43 +0000539
540/*
541 * exception handlers
542 */
John Rigbya9f3cf52010-01-25 23:12:52 -0700543#ifdef CONFIG_PRELOADER
544 .align 5
545do_hang:
546 ldr sp, _TEXT_BASE /* switch to abort stack */
5471:
548 bl 1b /* hang and never return */
549#else /* !CONFIG_PRELOADER */
wdenk7eaacc52003-08-29 22:00:43 +0000550 .align 5
551undefined_instruction:
552 get_bad_stack
553 bad_save_user_regs
554 bl do_undefined_instruction
555
556 .align 5
557software_interrupt:
558 get_bad_stack
559 bad_save_user_regs
560 bl do_software_interrupt
561
562 .align 5
563prefetch_abort:
564 get_bad_stack
565 bad_save_user_regs
566 bl do_prefetch_abort
567
568 .align 5
569data_abort:
570 get_bad_stack
571 bad_save_user_regs
572 bl do_data_abort
573
574 .align 5
575not_used:
576 get_bad_stack
577 bad_save_user_regs
578 bl do_not_used
579
580#ifdef CONFIG_USE_IRQ
581
582 .align 5
583irq:
584 get_irq_stack
585 irq_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200586 bl do_irq
wdenk7eaacc52003-08-29 22:00:43 +0000587 irq_restore_user_regs
588
589 .align 5
590fiq:
591 get_fiq_stack
592 /* someone ought to write a more effiction fiq_save_user_regs */
593 irq_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200594 bl do_fiq
wdenk7eaacc52003-08-29 22:00:43 +0000595 irq_restore_user_regs
596
597#else
598
599 .align 5
600irq:
601 get_bad_stack
602 bad_save_user_regs
603 bl do_irq
604
605 .align 5
606fiq:
607 get_bad_stack
608 bad_save_user_regs
609 bl do_fiq
610
611#endif
John Rigbya9f3cf52010-01-25 23:12:52 -0700612#endif /* CONFIG_PRELOADER */