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git01.mediatek.com / filogic / uboot / acba7c226d735ee221895b950afa9207727e58cc / . / drivers / pinctrl / mediatek / pinctrl-mt7623.c
blob: 2703e6f754c15aae170f9220cee243d22c73a483 [file] [log] [blame]
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 */
6
7#include <dm.h>
8
9#include "pinctrl-mtk-common.h"
10
11#define PIN_BOND_REG0 0xb10
12#define PIN_BOND_REG1 0xf20
13#define PIN_BOND_REG2 0xef0
14#define BOND_PCIE_CLR (0x77 << 3)
15#define BOND_I2S_CLR 0x3
16#define BOND_MSDC0E_CLR 0x1
17
18#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
19 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
20 _x_bits, 15, false)
21
22#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
23 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
24 _x_bits, 16, false)
25
26#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
27 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
28 _x_bits, 16, true)
29
30static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
31 PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
32};
33
34static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
35 PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
36 PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
37};
38
39static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
40 PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
41};
42
43static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
44 PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
45};
46
47static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
48 PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
49 PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
50 PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
51 PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
52 PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
53 PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
54 PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
55 PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
56 PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
57 PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
58 PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
59 PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
60 PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
61 PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
62 PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
63 PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
64 PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
65 PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
66 PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
67 PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
68 PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
69 PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
70 PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
71 PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
72 PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
73 PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
74 PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
75 PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
76 PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
77 PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
78 PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
79 PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
80 PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
81 PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
82 PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
83 PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1),
84 PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1),
85 PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1),
86 PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1),
87 PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1),
88 PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1),
89 PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1),
90 PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1),
91 PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1),
92 PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1),
93 PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1),
94 PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1),
95 PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1),
96 PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1),
97 PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1),
98 PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1),
99 PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1),
100 PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1),
101 PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1),
102 PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1),
103 PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1),
104 PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1),
105 PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1),
106 PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1),
107 PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1),
108 PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1),
109 PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1),
110 PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1),
111 PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1),
112};
113
114static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = {
115 PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1),
116 PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1),
117 PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1),
118 PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1),
119 PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1),
120 PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1),
121 PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1),
122 PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1),
123 PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1),
124 PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1),
125 PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1),
126 PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1),
127 PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1),
128 PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1),
129 PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1),
130 PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1),
131 PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1),
132 PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1),
133 PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1),
134 PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1),
135 PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1),
136 PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1),
137 PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1),
138 PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1),
139 PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1),
140 PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1),
141 PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1),
142 PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1),
143 PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1),
144 PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1),
145 PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1),
146 PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1),
147 PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1),
148 PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1),
149 PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1),
150 PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1),
151 PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1),
152 PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1),
153 PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1),
154 PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1),
155 PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1),
156 PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1),
157 PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1),
158 PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1),
159 PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1),
160 PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1),
161 PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1),
162 PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1),
163 PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1),
164 PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1),
165 PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1),
166 PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1),
167 PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1),
168 PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1),
169 PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1),
170 PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1),
171 PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1),
172 PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1),
173 PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1),
174 PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1),
175 PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1),
176 PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1),
177 PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1),
178 PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1),
179 PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1),
180 PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1),
181 PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1),
182 PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1),
183 PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1),
184 PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10),
185 PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1),
186 PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1),
187 PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1),
188 PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1),
189 PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1),
190 PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1),
191 PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1),
192 PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1),
193 PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1),
194 PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1),
195 PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1),
196 PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1),
197 PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1),
198 PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1),
199 PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1),
200};
201
202static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = {
203 PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1),
204};
205
206static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = {
207 PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1),
208};
209
210static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {
211 PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4),
212 PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4),
213 PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4),
214 PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4),
215 PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4),
216 PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4),
217 PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4),
218 PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4),
219 PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4),
220 PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4),
221 PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4),
222 PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4),
223 PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4),
224 PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4),
225 PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4),
226 PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4),
227 PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4),
228 PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4),
229 PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4),
230 PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4),
231 PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4),
232 PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4),
233 PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4),
234 PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4),
235 PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4),
236 PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4),
237 PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4),
238 PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4),
239 PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4),
240 PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4),
241 PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4),
242 PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4),
243 PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4),
244 PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4),
245 PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4),
246 PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4),
247 PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4),
248 PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4),
249 PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4),
250 PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4),
251 PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4),
252 PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4),
253 PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4),
254 PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4),
255 PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4),
256 PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4),
257 PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4),
258 PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4),
259 PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4),
260 PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4),
261 PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4),
262 PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4),
263};
264
David Woodhouse32102752020-06-19 12:40:20 +0100[diff] [blame]265static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = {
266 /* MSDC0 */
267 PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1),
268 PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1),
269 PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1),
270 PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1),
271 PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1),
272 PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1),
273 PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1),
274 PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1),
275 PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1),
276 PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1),
277 PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1),
278 /* MSDC1 */
279 PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1),
280 PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1),
281 PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1),
282 PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1),
283 PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1),
284 PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1),
285 /* MSDC1 */
286 PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1),
287 PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1),
288 PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1),
289 PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1),
290 PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1),
291 PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1),
292 /* MSDC0E */
293 PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1),
294 PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1),
295 PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1),
296 PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1),
297 PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1),
298 PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1),
299 PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1),
300 PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1),
301 PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1),
302 PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1),
303 PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1),
304 PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1),
305};
306
307static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = {
308 /* MSDC0 */
309 PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1),
310 PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1),
311 PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1),
312 PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1),
313 PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1),
314 PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1),
315 PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1),
316 PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1),
317 PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1),
318 PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1),
319 PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1),
320 /* MSDC1 */
321 PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1),
322 PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1),
323 PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1),
324 PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1),
325 PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1),
326 PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1),
327 /* MSDC2 */
328 PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1),
329 PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1),
330 PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1),
331 PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1),
332 PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1),
333 PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1),
334 /* MSDC0E */
335 PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1),
336 PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1),
337 PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1),
338 PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1),
339 PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1),
340 PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1),
341 PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1),
342 PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1),
343 PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1),
344 PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1),
345 PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1),
346 PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1),
347};
348
349static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {
350 /* MSDC0 */
351 PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1),
352 PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1),
353 PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1),
354 PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1),
355 PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1),
356 PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1),
357 PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1),
358 PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1),
359 PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1),
360 PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1),
361 PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1),
362 /* MSDC1 */
363 PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1),
364 PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1),
365 PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1),
366 PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1),
367 PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1),
368 PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1),
369 /* MSDC2 */
370 PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1),
371 PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1),
372 PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1),
373 PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1),
374 PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1),
375 PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1),
376 /* MSDC0E */
377 PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1),
378 PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1),
379 PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1),
380 PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1),
381 PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1),
382 PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1),
383 PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1),
384 PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1),
385 PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1),
386 PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1),
387 PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1),
388 PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
389};
390
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]391static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
392 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
393 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
394 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),
395 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range),
396 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range),
397 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range),
398 [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range),
399 [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range),
400 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range),
David Woodhouse32102752020-06-19 12:40:20 +0100[diff] [blame]401 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range),
402 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range),
403 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range),
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]404};
405
406static const struct mtk_pin_desc mt7623_pins[] = {
407 MTK_PIN(0, "PWRAP_SPI0_MI", DRV_GRP3),
408 MTK_PIN(1, "PWRAP_SPI0_MO", DRV_GRP3),
409 MTK_PIN(2, "PWRAP_INT", DRV_GRP3),
410 MTK_PIN(3, "PWRAP_SPI0_CK", DRV_GRP3),
411 MTK_PIN(4, "PWRAP_SPI0_CSN", DRV_GRP3),
412 MTK_PIN(5, "PWRAP_SPI0_CK2", DRV_GRP3),
413 MTK_PIN(6, "PWRAP_SPI0_CSN2", DRV_GRP3),
414 MTK_PIN(7, "SPI1_CSN", DRV_GRP3),
415 MTK_PIN(8, "SPI1_MI", DRV_GRP3),
416 MTK_PIN(9, "SPI1_MO", DRV_GRP3),
417 MTK_PIN(10, "RTC32K_CK", DRV_GRP3),
418 MTK_PIN(11, "WATCHDOG", DRV_GRP3),
419 MTK_PIN(12, "SRCLKENA", DRV_GRP3),
420 MTK_PIN(13, "SRCLKENAI", DRV_GRP3),
421 MTK_PIN(14, "URXD2", DRV_GRP1),
422 MTK_PIN(15, "UTXD2", DRV_GRP1),
423 MTK_PIN(16, "I2S5_DATA_IN", DRV_GRP1),
424 MTK_PIN(17, "I2S5_BCK", DRV_GRP1),
425 MTK_PIN(18, "PCM_CLK", DRV_GRP1),
426 MTK_PIN(19, "PCM_SYNC", DRV_GRP1),
427 MTK_PIN(20, "PCM_RX", DRV_GRP1),
428 MTK_PIN(21, "PCM_TX", DRV_GRP1),
429 MTK_PIN(22, "EINT0", DRV_GRP1),
430 MTK_PIN(23, "EINT1", DRV_GRP1),
431 MTK_PIN(24, "EINT2", DRV_GRP1),
432 MTK_PIN(25, "EINT3", DRV_GRP1),
433 MTK_PIN(26, "EINT4", DRV_GRP1),
434 MTK_PIN(27, "EINT5", DRV_GRP1),
435 MTK_PIN(28, "EINT6", DRV_GRP1),
436 MTK_PIN(29, "EINT7", DRV_GRP1),
437 MTK_PIN(30, "I2S5_LRCK", DRV_GRP1),
438 MTK_PIN(31, "I2S5_MCLK", DRV_GRP1),
439 MTK_PIN(32, "I2S5_DATA", DRV_GRP1),
440 MTK_PIN(33, "I2S1_DATA", DRV_GRP1),
441 MTK_PIN(34, "I2S1_DATA_IN", DRV_GRP1),
442 MTK_PIN(35, "I2S1_BCK", DRV_GRP1),
443 MTK_PIN(36, "I2S1_LRCK", DRV_GRP1),
444 MTK_PIN(37, "I2S1_MCLK", DRV_GRP1),
445 MTK_PIN(38, "I2S2_DATA", DRV_GRP1),
446 MTK_PIN(39, "JTMS", DRV_GRP3),
447 MTK_PIN(40, "JTCK", DRV_GRP3),
448 MTK_PIN(41, "JTDI", DRV_GRP3),
449 MTK_PIN(42, "JTDO", DRV_GRP3),
450 MTK_PIN(43, "NCLE", DRV_GRP1),
451 MTK_PIN(44, "NCEB1", DRV_GRP1),
452 MTK_PIN(45, "NCEB0", DRV_GRP1),
453 MTK_PIN(46, "IR", DRV_FIXED),
454 MTK_PIN(47, "NREB", DRV_GRP1),
455 MTK_PIN(48, "NRNB", DRV_GRP1),
456 MTK_PIN(49, "I2S0_DATA", DRV_GRP1),
457 MTK_PIN(50, "I2S2_BCK", DRV_GRP1),
458 MTK_PIN(51, "I2S2_DATA_IN", DRV_GRP1),
459 MTK_PIN(52, "I2S2_LRCK", DRV_GRP1),
460 MTK_PIN(53, "SPI0_CSN", DRV_GRP1),
461 MTK_PIN(54, "SPI0_CK", DRV_GRP1),
462 MTK_PIN(55, "SPI0_MI", DRV_GRP1),
463 MTK_PIN(56, "SPI0_MO", DRV_GRP1),
464 MTK_PIN(57, "SDA1", DRV_FIXED),
465 MTK_PIN(58, "SCL1", DRV_FIXED),
466 MTK_PIN(59, "RAMBUF_I_CLK", DRV_FIXED),
467 MTK_PIN(60, "WB_RSTB", DRV_GRP3),
468 MTK_PIN(61, "F2W_DATA", DRV_GRP3),
469 MTK_PIN(62, "F2W_CLK", DRV_GRP3),
470 MTK_PIN(63, "WB_SCLK", DRV_GRP3),
471 MTK_PIN(64, "WB_SDATA", DRV_GRP3),
472 MTK_PIN(65, "WB_SEN", DRV_GRP3),
473 MTK_PIN(66, "WB_CRTL0", DRV_GRP3),
474 MTK_PIN(67, "WB_CRTL1", DRV_GRP3),
475 MTK_PIN(68, "WB_CRTL2", DRV_GRP3),
476 MTK_PIN(69, "WB_CRTL3", DRV_GRP3),
477 MTK_PIN(70, "WB_CRTL4", DRV_GRP3),
478 MTK_PIN(71, "WB_CRTL5", DRV_GRP3),
479 MTK_PIN(72, "I2S0_DATA_IN", DRV_GRP1),
480 MTK_PIN(73, "I2S0_LRCK", DRV_GRP1),
481 MTK_PIN(74, "I2S0_BCK", DRV_GRP1),
482 MTK_PIN(75, "SDA0", DRV_FIXED),
483 MTK_PIN(76, "SCL0", DRV_FIXED),
484 MTK_PIN(77, "SDA2", DRV_FIXED),
485 MTK_PIN(78, "SCL2", DRV_FIXED),
486 MTK_PIN(79, "URXD0", DRV_FIXED),
487 MTK_PIN(80, "UTXD0", DRV_FIXED),
488 MTK_PIN(81, "URXD1", DRV_FIXED),
489 MTK_PIN(82, "UTXD1", DRV_FIXED),
490 MTK_PIN(83, "LCM_RST", DRV_FIXED),
491 MTK_PIN(84, "DSI_TE", DRV_FIXED),
492 MTK_PIN(85, "MSDC2_CMD", DRV_GRP4),
493 MTK_PIN(86, "MSDC2_CLK", DRV_GRP4),
494 MTK_PIN(87, "MSDC2_DAT0", DRV_GRP4),
495 MTK_PIN(88, "MSDC2_DAT1", DRV_GRP4),
496 MTK_PIN(89, "MSDC2_DAT2", DRV_GRP4),
497 MTK_PIN(90, "MSDC2_DAT3", DRV_GRP4),
498 MTK_PIN(91, "TDN3", DRV_FIXED),
499 MTK_PIN(92, "TDP3", DRV_FIXED),
500 MTK_PIN(93, "TDN2", DRV_FIXED),
501 MTK_PIN(94, "TDP2", DRV_FIXED),
502 MTK_PIN(95, "TCN", DRV_FIXED),
503 MTK_PIN(96, "TCP", DRV_FIXED),
504 MTK_PIN(97, "TDN1", DRV_FIXED),
505 MTK_PIN(98, "TDP1", DRV_FIXED),
506 MTK_PIN(99, "TDN0", DRV_FIXED),
507 MTK_PIN(100, "TDP0", DRV_FIXED),
508 MTK_PIN(101, "SPI2_CSN", DRV_FIXED),
509 MTK_PIN(102, "SPI2_MI", DRV_FIXED),
510 MTK_PIN(103, "SPI2_MO", DRV_FIXED),
511 MTK_PIN(104, "SPI2_CLK", DRV_FIXED),
512 MTK_PIN(105, "MSDC1_CMD", DRV_GRP4),
513 MTK_PIN(106, "MSDC1_CLK", DRV_GRP4),
514 MTK_PIN(107, "MSDC1_DAT0", DRV_GRP4),
515 MTK_PIN(108, "MSDC1_DAT1", DRV_GRP4),
516 MTK_PIN(109, "MSDC1_DAT2", DRV_GRP4),
517 MTK_PIN(110, "MSDC1_DAT3", DRV_GRP4),
518 MTK_PIN(111, "MSDC0_DAT7", DRV_GRP4),
519 MTK_PIN(112, "MSDC0_DAT6", DRV_GRP4),
520 MTK_PIN(113, "MSDC0_DAT5", DRV_GRP4),
521 MTK_PIN(114, "MSDC0_DAT4", DRV_GRP4),
522 MTK_PIN(115, "MSDC0_RSTB", DRV_GRP4),
523 MTK_PIN(116, "MSDC0_CMD", DRV_GRP4),
524 MTK_PIN(117, "MSDC0_CLK", DRV_GRP4),
525 MTK_PIN(118, "MSDC0_DAT3", DRV_GRP4),
526 MTK_PIN(119, "MSDC0_DAT2", DRV_GRP4),
527 MTK_PIN(120, "MSDC0_DAT1", DRV_GRP4),
528 MTK_PIN(121, "MSDC0_DAT0", DRV_GRP4),
529 MTK_PIN(122, "CEC", DRV_FIXED),
530 MTK_PIN(123, "HTPLG", DRV_FIXED),
531 MTK_PIN(124, "HDMISCK", DRV_FIXED),
532 MTK_PIN(125, "HDMISD", DRV_FIXED),
533 MTK_PIN(126, "I2S0_MCLK", DRV_GRP1),
534 MTK_PIN(127, "RAMBUF_IDATA0", DRV_FIXED),
535 MTK_PIN(128, "RAMBUF_IDATA1", DRV_FIXED),
536 MTK_PIN(129, "RAMBUF_IDATA2", DRV_FIXED),
537 MTK_PIN(130, "RAMBUF_IDATA3", DRV_FIXED),
538 MTK_PIN(131, "RAMBUF_IDATA4", DRV_FIXED),
539 MTK_PIN(132, "RAMBUF_IDATA5", DRV_FIXED),
540 MTK_PIN(133, "RAMBUF_IDATA6", DRV_FIXED),
541 MTK_PIN(134, "RAMBUF_IDATA7", DRV_FIXED),
542 MTK_PIN(135, "RAMBUF_IDATA8", DRV_FIXED),
543 MTK_PIN(136, "RAMBUF_IDATA9", DRV_FIXED),
544 MTK_PIN(137, "RAMBUF_IDATA10", DRV_FIXED),
545 MTK_PIN(138, "RAMBUF_IDATA11", DRV_FIXED),
546 MTK_PIN(139, "RAMBUF_IDATA12", DRV_FIXED),
547 MTK_PIN(140, "RAMBUF_IDATA13", DRV_FIXED),
548 MTK_PIN(141, "RAMBUF_IDATA14", DRV_FIXED),
549 MTK_PIN(142, "RAMBUF_IDATA15", DRV_FIXED),
550 MTK_PIN(143, "RAMBUF_ODATA0", DRV_FIXED),
551 MTK_PIN(144, "RAMBUF_ODATA1", DRV_FIXED),
552 MTK_PIN(145, "RAMBUF_ODATA2", DRV_FIXED),
553 MTK_PIN(146, "RAMBUF_ODATA3", DRV_FIXED),
554 MTK_PIN(147, "RAMBUF_ODATA4", DRV_FIXED),
555 MTK_PIN(148, "RAMBUF_ODATA5", DRV_FIXED),
556 MTK_PIN(149, "RAMBUF_ODATA6", DRV_FIXED),
557 MTK_PIN(150, "RAMBUF_ODATA7", DRV_FIXED),
558 MTK_PIN(151, "RAMBUF_ODATA8", DRV_FIXED),
559 MTK_PIN(152, "RAMBUF_ODATA9", DRV_FIXED),
560 MTK_PIN(153, "RAMBUF_ODATA10", DRV_FIXED),
561 MTK_PIN(154, "RAMBUF_ODATA11", DRV_FIXED),
562 MTK_PIN(155, "RAMBUF_ODATA12", DRV_FIXED),
563 MTK_PIN(156, "RAMBUF_ODATA13", DRV_FIXED),
564 MTK_PIN(157, "RAMBUF_ODATA14", DRV_FIXED),
565 MTK_PIN(158, "RAMBUF_ODATA15", DRV_FIXED),
566 MTK_PIN(159, "RAMBUF_BE0", DRV_FIXED),
567 MTK_PIN(160, "RAMBUF_BE1", DRV_FIXED),
568 MTK_PIN(161, "AP2PT_INT", DRV_FIXED),
569 MTK_PIN(162, "AP2PT_INT_CLR", DRV_FIXED),
570 MTK_PIN(163, "PT2AP_INT", DRV_FIXED),
571 MTK_PIN(164, "PT2AP_INT_CLR", DRV_FIXED),
572 MTK_PIN(165, "AP2UP_INT", DRV_FIXED),
573 MTK_PIN(166, "AP2UP_INT_CLR", DRV_FIXED),
574 MTK_PIN(167, "UP2AP_INT", DRV_FIXED),
575 MTK_PIN(168, "UP2AP_INT_CLR", DRV_FIXED),
576 MTK_PIN(169, "RAMBUF_ADDR0", DRV_FIXED),
577 MTK_PIN(170, "RAMBUF_ADDR1", DRV_FIXED),
578 MTK_PIN(171, "RAMBUF_ADDR2", DRV_FIXED),
579 MTK_PIN(172, "RAMBUF_ADDR3", DRV_FIXED),
580 MTK_PIN(173, "RAMBUF_ADDR4", DRV_FIXED),
581 MTK_PIN(174, "RAMBUF_ADDR5", DRV_FIXED),
582 MTK_PIN(175, "RAMBUF_ADDR6", DRV_FIXED),
583 MTK_PIN(176, "RAMBUF_ADDR7", DRV_FIXED),
584 MTK_PIN(177, "RAMBUF_ADDR8", DRV_FIXED),
585 MTK_PIN(178, "RAMBUF_ADDR9", DRV_FIXED),
586 MTK_PIN(179, "RAMBUF_ADDR10", DRV_FIXED),
587 MTK_PIN(180, "RAMBUF_RW", DRV_FIXED),
588 MTK_PIN(181, "RAMBUF_LAST", DRV_FIXED),
589 MTK_PIN(182, "RAMBUF_HP", DRV_FIXED),
590 MTK_PIN(183, "RAMBUF_REQ", DRV_FIXED),
591 MTK_PIN(184, "RAMBUF_ALE", DRV_FIXED),
592 MTK_PIN(185, "RAMBUF_DLE", DRV_FIXED),
593 MTK_PIN(186, "RAMBUF_WDLE", DRV_FIXED),
594 MTK_PIN(187, "RAMBUF_O_CLK", DRV_FIXED),
595 MTK_PIN(188, "I2S2_MCLK", DRV_GRP1),
596 MTK_PIN(189, "I2S3_DATA", DRV_GRP1),
597 MTK_PIN(190, "I2S3_DATA_IN", DRV_GRP1),
598 MTK_PIN(191, "I2S3_BCK", DRV_GRP1),
599 MTK_PIN(192, "I2S3_LRCK", DRV_GRP1),
600 MTK_PIN(193, "I2S3_MCLK", DRV_GRP1),
601 MTK_PIN(194, "I2S4_DATA", DRV_GRP1),
602 MTK_PIN(195, "I2S4_DATA_IN", DRV_GRP1),
603 MTK_PIN(196, "I2S4_BCK", DRV_GRP1),
604 MTK_PIN(197, "I2S4_LRCK", DRV_GRP1),
605 MTK_PIN(198, "I2S4_MCLK", DRV_GRP1),
606 MTK_PIN(199, "SPI1_CLK", DRV_GRP3),
607 MTK_PIN(200, "SPDIF_OUT", DRV_GRP1),
608 MTK_PIN(201, "SPDIF_IN0", DRV_GRP1),
609 MTK_PIN(202, "SPDIF_IN1", DRV_GRP1),
610 MTK_PIN(203, "PWM0", DRV_GRP1),
611 MTK_PIN(204, "PWM1", DRV_GRP1),
612 MTK_PIN(205, "PWM2", DRV_GRP1),
613 MTK_PIN(206, "PWM3", DRV_GRP1),
614 MTK_PIN(207, "PWM4", DRV_GRP1),
615 MTK_PIN(208, "AUD_EXT_CK1", DRV_GRP1),
616 MTK_PIN(209, "AUD_EXT_CK2", DRV_GRP1),
617 MTK_PIN(210, "AUD_CLOCK", DRV_GRP3),
618 MTK_PIN(211, "DVP_RESET", DRV_GRP3),
619 MTK_PIN(212, "DVP_CLOCK", DRV_GRP3),
620 MTK_PIN(213, "DVP_CS", DRV_GRP3),
621 MTK_PIN(214, "DVP_CK", DRV_GRP3),
622 MTK_PIN(215, "DVP_DI", DRV_GRP3),
623 MTK_PIN(216, "DVP_DO", DRV_GRP3),
624 MTK_PIN(217, "AP_CS", DRV_GRP3),
625 MTK_PIN(218, "AP_CK", DRV_GRP3),
626 MTK_PIN(219, "AP_DI", DRV_GRP3),
627 MTK_PIN(220, "AP_DO", DRV_GRP3),
628 MTK_PIN(221, "DVD_BCLK", DRV_GRP3),
629 MTK_PIN(222, "T8032_CLK", DRV_GRP3),
630 MTK_PIN(223, "AP_BCLK", DRV_GRP3),
631 MTK_PIN(224, "HOST_CS", DRV_GRP3),
632 MTK_PIN(225, "HOST_CK", DRV_GRP3),
633 MTK_PIN(226, "HOST_DO0", DRV_GRP3),
634 MTK_PIN(227, "HOST_DO1", DRV_GRP3),
635 MTK_PIN(228, "SLV_CS", DRV_GRP3),
636 MTK_PIN(229, "SLV_CK", DRV_GRP3),
637 MTK_PIN(230, "SLV_DI0", DRV_GRP3),
638 MTK_PIN(231, "SLV_DI1", DRV_GRP3),
639 MTK_PIN(232, "AP2DSP_INT", DRV_GRP3),
640 MTK_PIN(233, "AP2DSP_INT_CLR", DRV_GRP3),
641 MTK_PIN(234, "DSP2AP_INT", DRV_GRP3),
642 MTK_PIN(235, "DSP2AP_INT_CLR", DRV_GRP3),
643 MTK_PIN(236, "EXT_SDIO3", DRV_GRP1),
644 MTK_PIN(237, "EXT_SDIO2", DRV_GRP1),
645 MTK_PIN(238, "EXT_SDIO1", DRV_GRP1),
646 MTK_PIN(239, "EXT_SDIO0", DRV_GRP1),
647 MTK_PIN(240, "EXT_XCS", DRV_GRP1),
648 MTK_PIN(241, "EXT_SCK", DRV_GRP1),
649 MTK_PIN(242, "URTS2", DRV_GRP1),
650 MTK_PIN(243, "UCTS2", DRV_GRP1),
651 MTK_PIN(244, "HDMI_SDA_RX", DRV_FIXED),
652 MTK_PIN(245, "HDMI_SCL_RX", DRV_FIXED),
653 MTK_PIN(246, "MHL_SENCE", DRV_FIXED),
654 MTK_PIN(247, "HDMI_HPD_CBUS_RX", DRV_FIXED),
655 MTK_PIN(248, "HDMI_TESTOUTP_RX", DRV_GRP1),
656 MTK_PIN(249, "MSDC0E_RSTB", DRV_GRP4),
657 MTK_PIN(250, "MSDC0E_DAT7", DRV_GRP4),
658 MTK_PIN(251, "MSDC0E_DAT6", DRV_GRP4),
659 MTK_PIN(252, "MSDC0E_DAT5", DRV_GRP4),
660 MTK_PIN(253, "MSDC0E_DAT4", DRV_GRP4),
661 MTK_PIN(254, "MSDC0E_DAT3", DRV_GRP4),
662 MTK_PIN(255, "MSDC0E_DAT2", DRV_GRP4),
663 MTK_PIN(256, "MSDC0E_DAT1", DRV_GRP4),
664 MTK_PIN(257, "MSDC0E_DAT0", DRV_GRP4),
665 MTK_PIN(258, "MSDC0E_CMD", DRV_GRP4),
666 MTK_PIN(259, "MSDC0E_CLK", DRV_GRP4),
667 MTK_PIN(260, "MSDC0E_DSL", DRV_GRP4),
668 MTK_PIN(261, "MSDC1_INS", DRV_GRP4),
669 MTK_PIN(262, "G2_TXEN", DRV_GRP1),
670 MTK_PIN(263, "G2_TXD3", DRV_GRP1),
671 MTK_PIN(264, "G2_TXD2", DRV_GRP1),
672 MTK_PIN(265, "G2_TXD1", DRV_GRP1),
673 MTK_PIN(266, "G2_TXD0", DRV_GRP1),
674 MTK_PIN(267, "G2_TXC", DRV_GRP1),
675 MTK_PIN(268, "G2_RXC", DRV_GRP1),
676 MTK_PIN(269, "G2_RXD0", DRV_GRP1),
677 MTK_PIN(270, "G2_RXD1", DRV_GRP1),
678 MTK_PIN(271, "G2_RXD2", DRV_GRP1),
679 MTK_PIN(272, "G2_RXD3", DRV_GRP1),
680 MTK_PIN(273, "ESW_INT", DRV_GRP1),
681 MTK_PIN(274, "G2_RXDV", DRV_GRP1),
682 MTK_PIN(275, "MDC", DRV_GRP1),
683 MTK_PIN(276, "MDIO", DRV_GRP1),
684 MTK_PIN(277, "ESW_RST", DRV_GRP1),
685 MTK_PIN(278, "JTAG_RESET", DRV_GRP3),
686 MTK_PIN(279, "USB3_RES_BOND", DRV_GRP1),
687};
688
689/* List all groups consisting of these pins dedicated to the enablement of
690 * certain hardware block and the corresponding mode for all of the pins.
691 * The hardware probably has multiple combinations of these pinouts.
692 */
693
694/* AUDIO EXT CLK */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]695static const int mt7623_aud_ext_clk0_pins[] = { 208, };
696static const int mt7623_aud_ext_clk0_funcs[] = { 1, };
697static const int mt7623_aud_ext_clk1_pins[] = { 209, };
698static const int mt7623_aud_ext_clk1_funcs[] = { 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]699
700/* DISP PWM */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]701static const int mt7623_disp_pwm_0_pins[] = { 72, };
702static const int mt7623_disp_pwm_0_funcs[] = { 5, };
703static const int mt7623_disp_pwm_1_pins[] = { 203, };
704static const int mt7623_disp_pwm_1_funcs[] = { 2, };
705static const int mt7623_disp_pwm_2_pins[] = { 208, };
706static const int mt7623_disp_pwm_2_funcs[] = { 5, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]707
708/* ESW */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]709static const int mt7623_esw_int_pins[] = { 273, };
710static const int mt7623_esw_int_funcs[] = { 1, };
711static const int mt7623_esw_rst_pins[] = { 277, };
712static const int mt7623_esw_rst_funcs[] = { 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]713
714/* EPHY */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]715static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
716 269, 270, 271, 272, 274, };
717static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]718
719/* EXT_SDIO */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]720static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
721static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]722
723/* HDMI RX */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]724static const int mt7623_hdmi_rx_pins[] = { 247, 248, };
725static const int mt7623_hdmi_rx_funcs[] = { 1, 1 };
726static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
727static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]728
729/* HDMI TX */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]730static const int mt7623_hdmi_cec_pins[] = { 122, };
731static const int mt7623_hdmi_cec_funcs[] = { 1, };
732static const int mt7623_hdmi_htplg_pins[] = { 123, };
733static const int mt7623_hdmi_htplg_funcs[] = { 1, };
734static const int mt7623_hdmi_i2c_pins[] = { 124, 125, };
735static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]736
737/* I2C */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]738static const int mt7623_i2c0_pins[] = { 75, 76, };
739static const int mt7623_i2c0_funcs[] = { 1, 1, };
740static const int mt7623_i2c1_0_pins[] = { 57, 58, };
741static const int mt7623_i2c1_0_funcs[] = { 1, 1, };
742static const int mt7623_i2c1_1_pins[] = { 242, 243, };
743static const int mt7623_i2c1_1_funcs[] = { 4, 4, };
744static const int mt7623_i2c1_2_pins[] = { 85, 86, };
745static const int mt7623_i2c1_2_funcs[] = { 3, 3, };
746static const int mt7623_i2c1_3_pins[] = { 105, 106, };
747static const int mt7623_i2c1_3_funcs[] = { 3, 3, };
748static const int mt7623_i2c1_4_pins[] = { 124, 125, };
749static const int mt7623_i2c1_4_funcs[] = { 4, 4, };
750static const int mt7623_i2c2_0_pins[] = { 77, 78, };
751static const int mt7623_i2c2_0_funcs[] = { 1, 1, };
752static const int mt7623_i2c2_1_pins[] = { 89, 90, };
753static const int mt7623_i2c2_1_funcs[] = { 3, 3, };
754static const int mt7623_i2c2_2_pins[] = { 109, 110, };
755static const int mt7623_i2c2_2_funcs[] = { 3, 3, };
756static const int mt7623_i2c2_3_pins[] = { 122, 123, };
757static const int mt7623_i2c2_3_funcs[] = { 4, 4, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]758
759/* I2S */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]760static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
761static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
762static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
763static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
764static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
765static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
766static const int mt7623_i2s2_data_in_pins[] = { 51, };
767static const int mt7623_i2s2_data_in_funcs[] = { 1, };
768static const int mt7623_i2s2_data_0_pins[] = { 203, };
769static const int mt7623_i2s2_data_0_funcs[] = { 9, };
770static const int mt7623_i2s2_data_1_pins[] = { 38, };
771static const int mt7623_i2s2_data_1_funcs[] = { 4, };
772static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
773static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
774static const int mt7623_i2s3_data_in_pins[] = { 190, };
775static const int mt7623_i2s3_data_in_funcs[] = { 1, };
776static const int mt7623_i2s3_data_0_pins[] = { 204, };
777static const int mt7623_i2s3_data_0_funcs[] = { 9, };
778static const int mt7623_i2s3_data_1_pins[] = { 2, };
779static const int mt7623_i2s3_data_1_funcs[] = { 0, };
780static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
781static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
782static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
783static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]784
785/* IR */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]786static const int mt7623_ir_pins[] = { 46, };
787static const int mt7623_ir_funcs[] = { 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]788
789/* LCD */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]790static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
791 99, 100, };
792static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
793static const int mt7623_dsi_te_pins[] = { 84, };
794static const int mt7623_dsi_te_funcs[] = { 1, };
795static const int mt7623_lcm_rst_pins[] = { 83, };
796static const int mt7623_lcm_rst_funcs[] = { 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]797
798/* MDC/MDIO */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]799static const int mt7623_mdc_mdio_pins[] = { 275, 276, };
800static const int mt7623_mdc_mdio_funcs[] = { 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]801
802/* MSDC */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]803static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
804 119, 120, 121, };
805static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
806static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
807static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
808static const int mt7623_msdc1_ins_pins[] = { 261, };
809static const int mt7623_msdc1_ins_funcs[] = { 1, };
810static const int mt7623_msdc1_wp_0_pins[] = { 29, };
811static const int mt7623_msdc1_wp_0_funcs[] = { 1, };
812static const int mt7623_msdc1_wp_1_pins[] = { 55, };
813static const int mt7623_msdc1_wp_1_funcs[] = { 3, };
814static const int mt7623_msdc1_wp_2_pins[] = { 209, };
815static const int mt7623_msdc1_wp_2_funcs[] = { 2, };
816static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
817static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
818static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
819 257, 258, 259, 260, };
820static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]821
822/* NAND */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]823static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
824 116, 117, 118, 119, 120, 121, };
825static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
826 4, 4, };
827static const int mt7623_nandc_ceb0_pins[] = { 45, };
828static const int mt7623_nandc_ceb0_funcs[] = { 1, };
829static const int mt7623_nandc_ceb1_pins[] = { 44, };
830static const int mt7623_nandc_ceb1_funcs[] = { 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]831
832/* RTC */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]833static const int mt7623_rtc_pins[] = { 10, };
834static const int mt7623_rtc_funcs[] = { 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]835
836/* OTG */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]837static const int mt7623_otg_iddig0_0_pins[] = { 29, };
838static const int mt7623_otg_iddig0_0_funcs[] = { 1, };
839static const int mt7623_otg_iddig0_1_pins[] = { 44, };
840static const int mt7623_otg_iddig0_1_funcs[] = { 2, };
841static const int mt7623_otg_iddig0_2_pins[] = { 236, };
842static const int mt7623_otg_iddig0_2_funcs[] = { 2, };
843static const int mt7623_otg_iddig1_0_pins[] = { 27, };
844static const int mt7623_otg_iddig1_0_funcs[] = { 2, };
845static const int mt7623_otg_iddig1_1_pins[] = { 47, };
846static const int mt7623_otg_iddig1_1_funcs[] = { 2, };
847static const int mt7623_otg_iddig1_2_pins[] = { 238, };
848static const int mt7623_otg_iddig1_2_funcs[] = { 2, };
849static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
850static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
851static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
852static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
853static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
854static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
855static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
856static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
857static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
858static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
859static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
860static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]861
862/* PCIE */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]863static const int mt7623_pcie0_0_perst_pins[] = { 208, };
864static const int mt7623_pcie0_0_perst_funcs[] = { 3, };
865static const int mt7623_pcie0_1_perst_pins[] = { 22, };
866static const int mt7623_pcie0_1_perst_funcs[] = { 2, };
867static const int mt7623_pcie1_0_perst_pins[] = { 209, };
868static const int mt7623_pcie1_0_perst_funcs[] = { 3, };
869static const int mt7623_pcie1_1_perst_pins[] = { 23, };
870static const int mt7623_pcie1_1_perst_funcs[] = { 2, };
871static const int mt7623_pcie2_0_perst_pins[] = { 24, };
872static const int mt7623_pcie2_0_perst_funcs[] = { 2, };
873static const int mt7623_pcie2_1_perst_pins[] = { 29, };
874static const int mt7623_pcie2_1_perst_funcs[] = { 6, };
875static const int mt7623_pcie0_0_wake_pins[] = { 28, };
876static const int mt7623_pcie0_0_wake_funcs[] = { 6, };
877static const int mt7623_pcie0_1_wake_pins[] = { 251, };
878static const int mt7623_pcie0_1_wake_funcs[] = { 6, };
879static const int mt7623_pcie1_0_wake_pins[] = { 27, };
880static const int mt7623_pcie1_0_wake_funcs[] = { 6, };
881static const int mt7623_pcie1_1_wake_pins[] = { 253, };
882static const int mt7623_pcie1_1_wake_funcs[] = { 6, };
883static const int mt7623_pcie2_0_wake_pins[] = { 26, };
884static const int mt7623_pcie2_0_wake_funcs[] = { 6, };
885static const int mt7623_pcie2_1_wake_pins[] = { 255, };
886static const int mt7623_pcie2_1_wake_funcs[] = { 6, };
887static const int mt7623_pcie0_clkreq_pins[] = { 250, };
888static const int mt7623_pcie0_clkreq_funcs[] = { 6, };
889static const int mt7623_pcie1_clkreq_pins[] = { 252, };
890static const int mt7623_pcie1_clkreq_funcs[] = { 6, };
891static const int mt7623_pcie2_clkreq_pins[] = { 254, };
892static const int mt7623_pcie2_clkreq_funcs[] = { 6, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]893/* the pcie_*_rev are only used for MT7623 */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]894static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
895static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
896static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
897static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
898static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
899static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
900static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
901static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
902static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
903static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
904static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
905static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]906
907/* PCM */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]908static const int mt7623_pcm_clk_0_pins[] = { 18, };
909static const int mt7623_pcm_clk_0_funcs[] = { 1, };
910static const int mt7623_pcm_clk_1_pins[] = { 17, };
911static const int mt7623_pcm_clk_1_funcs[] = { 3, };
912static const int mt7623_pcm_clk_2_pins[] = { 35, };
913static const int mt7623_pcm_clk_2_funcs[] = { 3, };
914static const int mt7623_pcm_clk_3_pins[] = { 50, };
915static const int mt7623_pcm_clk_3_funcs[] = { 3, };
916static const int mt7623_pcm_clk_4_pins[] = { 74, };
917static const int mt7623_pcm_clk_4_funcs[] = { 3, };
918static const int mt7623_pcm_clk_5_pins[] = { 191, };
919static const int mt7623_pcm_clk_5_funcs[] = { 3, };
920static const int mt7623_pcm_clk_6_pins[] = { 196, };
921static const int mt7623_pcm_clk_6_funcs[] = { 3, };
922static const int mt7623_pcm_sync_0_pins[] = { 19, };
923static const int mt7623_pcm_sync_0_funcs[] = { 1, };
924static const int mt7623_pcm_sync_1_pins[] = { 30, };
925static const int mt7623_pcm_sync_1_funcs[] = { 3, };
926static const int mt7623_pcm_sync_2_pins[] = { 36, };
927static const int mt7623_pcm_sync_2_funcs[] = { 3, };
928static const int mt7623_pcm_sync_3_pins[] = { 52, };
929static const int mt7623_pcm_sync_3_funcs[] = { 31, };
930static const int mt7623_pcm_sync_4_pins[] = { 73, };
931static const int mt7623_pcm_sync_4_funcs[] = { 3, };
932static const int mt7623_pcm_sync_5_pins[] = { 192, };
933static const int mt7623_pcm_sync_5_funcs[] = { 3, };
934static const int mt7623_pcm_sync_6_pins[] = { 197, };
935static const int mt7623_pcm_sync_6_funcs[] = { 3, };
936static const int mt7623_pcm_rx_0_pins[] = { 20, };
937static const int mt7623_pcm_rx_0_funcs[] = { 1, };
938static const int mt7623_pcm_rx_1_pins[] = { 16, };
939static const int mt7623_pcm_rx_1_funcs[] = { 3, };
940static const int mt7623_pcm_rx_2_pins[] = { 34, };
941static const int mt7623_pcm_rx_2_funcs[] = { 3, };
942static const int mt7623_pcm_rx_3_pins[] = { 51, };
943static const int mt7623_pcm_rx_3_funcs[] = { 3, };
944static const int mt7623_pcm_rx_4_pins[] = { 72, };
945static const int mt7623_pcm_rx_4_funcs[] = { 3, };
946static const int mt7623_pcm_rx_5_pins[] = { 190, };
947static const int mt7623_pcm_rx_5_funcs[] = { 3, };
948static const int mt7623_pcm_rx_6_pins[] = { 195, };
949static const int mt7623_pcm_rx_6_funcs[] = { 3, };
950static const int mt7623_pcm_tx_0_pins[] = { 21, };
951static const int mt7623_pcm_tx_0_funcs[] = { 1, };
952static const int mt7623_pcm_tx_1_pins[] = { 32, };
953static const int mt7623_pcm_tx_1_funcs[] = { 3, };
954static const int mt7623_pcm_tx_2_pins[] = { 33, };
955static const int mt7623_pcm_tx_2_funcs[] = { 3, };
956static const int mt7623_pcm_tx_3_pins[] = { 38, };
957static const int mt7623_pcm_tx_3_funcs[] = { 3, };
958static const int mt7623_pcm_tx_4_pins[] = { 49, };
959static const int mt7623_pcm_tx_4_funcs[] = { 3, };
960static const int mt7623_pcm_tx_5_pins[] = { 189, };
961static const int mt7623_pcm_tx_5_funcs[] = { 3, };
962static const int mt7623_pcm_tx_6_pins[] = { 194, };
963static const int mt7623_pcm_tx_6_funcs[] = { 3, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]964
965/* PWM */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]966static const int mt7623_pwm_ch1_0_pins[] = { 203, };
967static const int mt7623_pwm_ch1_0_funcs[] = { 1, };
968static const int mt7623_pwm_ch1_1_pins[] = { 208, };
969static const int mt7623_pwm_ch1_1_funcs[] = { 2, };
970static const int mt7623_pwm_ch1_2_pins[] = { 72, };
971static const int mt7623_pwm_ch1_2_funcs[] = { 4, };
972static const int mt7623_pwm_ch1_3_pins[] = { 88, };
973static const int mt7623_pwm_ch1_3_funcs[] = { 3, };
974static const int mt7623_pwm_ch1_4_pins[] = { 108, };
975static const int mt7623_pwm_ch1_4_funcs[] = { 3, };
976static const int mt7623_pwm_ch2_0_pins[] = { 204, };
977static const int mt7623_pwm_ch2_0_funcs[] = { 1, };
978static const int mt7623_pwm_ch2_1_pins[] = { 53, };
979static const int mt7623_pwm_ch2_1_funcs[] = { 5, };
980static const int mt7623_pwm_ch2_2_pins[] = { 88, };
981static const int mt7623_pwm_ch2_2_funcs[] = { 6, };
982static const int mt7623_pwm_ch2_3_pins[] = { 108, };
983static const int mt7623_pwm_ch2_3_funcs[] = { 6, };
984static const int mt7623_pwm_ch2_4_pins[] = { 209, };
985static const int mt7623_pwm_ch2_4_funcs[] = { 5, };
986static const int mt7623_pwm_ch3_0_pins[] = { 205, };
987static const int mt7623_pwm_ch3_0_funcs[] = { 1, };
988static const int mt7623_pwm_ch3_1_pins[] = { 55, };
989static const int mt7623_pwm_ch3_1_funcs[] = { 5, };
990static const int mt7623_pwm_ch3_2_pins[] = { 89, };
991static const int mt7623_pwm_ch3_2_funcs[] = { 6, };
992static const int mt7623_pwm_ch3_3_pins[] = { 109, };
993static const int mt7623_pwm_ch3_3_funcs[] = { 6, };
994static const int mt7623_pwm_ch4_0_pins[] = { 206, };
995static const int mt7623_pwm_ch4_0_funcs[] = { 1, };
996static const int mt7623_pwm_ch4_1_pins[] = { 90, };
997static const int mt7623_pwm_ch4_1_funcs[] = { 6, };
998static const int mt7623_pwm_ch4_2_pins[] = { 110, };
999static const int mt7623_pwm_ch4_2_funcs[] = { 6, };
1000static const int mt7623_pwm_ch4_3_pins[] = { 124, };
1001static const int mt7623_pwm_ch4_3_funcs[] = { 5, };
1002static const int mt7623_pwm_ch5_0_pins[] = { 207, };
1003static const int mt7623_pwm_ch5_0_funcs[] = { 1, };
1004static const int mt7623_pwm_ch5_1_pins[] = { 125, };
1005static const int mt7623_pwm_ch5_1_funcs[] = { 5, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1006
1007/* PWRAP */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]1008static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
1009static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1010
1011/* SPDIF */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]1012static const int mt7623_spdif_in0_0_pins[] = { 56, };
1013static const int mt7623_spdif_in0_0_funcs[] = { 3, };
1014static const int mt7623_spdif_in0_1_pins[] = { 201, };
1015static const int mt7623_spdif_in0_1_funcs[] = { 1, };
1016static const int mt7623_spdif_in1_0_pins[] = { 54, };
1017static const int mt7623_spdif_in1_0_funcs[] = { 3, };
1018static const int mt7623_spdif_in1_1_pins[] = { 202, };
1019static const int mt7623_spdif_in1_1_funcs[] = { 1, };
1020static const int mt7623_spdif_out_pins[] = { 202, };
1021static const int mt7623_spdif_out_funcs[] = { 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1022
1023/* SPI */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]1024static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
1025static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
1026static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
1027static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
1028static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
1029static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1030
1031/* UART */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]1032static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
1033static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
1034static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
1035static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
1036static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
1037static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
1038static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
1039static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
1040static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
1041static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
1042static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
1043static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
1044static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
1045static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
1046static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
1047static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
1048static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
1049static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
1050static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
1051static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
1052static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
1053static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
1054static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
1055static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
1056static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
1057static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
1058static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
1059static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1060
1061/* Watchdog */
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]1062static const int mt7623_watchdog_0_pins[] = { 11, };
1063static const int mt7623_watchdog_0_funcs[] = { 1, };
1064static const int mt7623_watchdog_1_pins[] = { 121, };
1065static const int mt7623_watchdog_1_funcs[] = { 5, };
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1066
1067static const struct mtk_group_desc mt7623_groups[] = {
1068 PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
1069 PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1),
1070 PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te),
1071 PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0),
1072 PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1),
1073 PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2),
1074 PINCTRL_PIN_GROUP("ephy", mt7623_ephy),
1075 PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int),
1076 PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst),
1077 PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio),
1078 PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec),
1079 PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg),
1080 PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c),
1081 PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx),
1082 PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c),
1083 PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0),
1084 PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0),
1085 PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1),
1086 PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2),
1087 PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3),
1088 PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4),
1089 PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0),
1090 PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1),
1091 PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2),
1092 PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3),
1093 PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0),
1094 PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1),
1095 PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4),
1096 PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5),
1097 PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk),
1098 PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk),
1099 PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in),
1100 PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in),
1101 PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0),
1102 PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1),
1103 PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0),
1104 PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1),
1105 PINCTRL_PIN_GROUP("ir", mt7623_ir),
1106 PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst),
1107 PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio),
1108 PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx),
1109 PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0),
1110 PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1),
1111 PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins),
1112 PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0),
1113 PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1),
1114 PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2),
1115 PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2),
1116 PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3),
1117 PINCTRL_PIN_GROUP("nandc", mt7623_nandc),
1118 PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0),
1119 PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1),
1120 PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0),
1121 PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1),
1122 PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2),
1123 PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0),
1124 PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1),
1125 PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2),
1126 PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0),
1127 PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1),
1128 PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2),
1129 PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0),
1130 PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1),
1131 PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2),
1132 PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst),
1133 PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst),
1134 PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst),
1135 PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
1136 PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
1137 PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst),
1138 PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst),
1139 PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst),
1140 PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst),
1141 PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst),
1142 PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst),
1143 PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst),
1144 PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst),
1145 PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake),
1146 PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake),
1147 PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake),
1148 PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake),
1149 PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake),
1150 PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake),
1151 PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq),
1152 PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq),
1153 PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq),
1154 PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0),
1155 PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1),
1156 PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2),
1157 PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3),
1158 PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4),
1159 PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5),
1160 PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6),
1161 PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0),
1162 PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1),
1163 PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2),
1164 PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3),
1165 PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4),
1166 PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5),
1167 PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6),
1168 PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0),
1169 PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1),
1170 PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2),
1171 PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3),
1172 PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4),
1173 PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5),
1174 PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6),
1175 PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0),
1176 PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1),
1177 PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2),
1178 PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3),
1179 PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4),
1180 PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5),
1181 PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6),
1182 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0),
1183 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1),
1184 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2),
1185 PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3),
1186 PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4),
1187 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0),
1188 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1),
1189 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2),
1190 PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3),
1191 PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4),
1192 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0),
1193 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1),
1194 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2),
1195 PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3),
1196 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0),
1197 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1),
1198 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2),
1199 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3),
1200 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0),
1201 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1),
1202 PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap),
1203 PINCTRL_PIN_GROUP("rtc", mt7623_rtc),
1204 PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0),
1205 PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1),
1206 PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0),
1207 PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1),
1208 PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out),
1209 PINCTRL_PIN_GROUP("spi0", mt7623_spi0),
1210 PINCTRL_PIN_GROUP("spi1", mt7623_spi1),
1211 PINCTRL_PIN_GROUP("spi2", mt7623_spi2),
1212 PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd),
1213 PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd),
1214 PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd),
1215 PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd),
1216 PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd),
1217 PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd),
1218 PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd),
1219 PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd),
1220 PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd),
1221 PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd),
1222 PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts),
1223 PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts),
1224 PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts),
1225 PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts),
1226 PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0),
1227 PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1),
1228};
1229
1230/* Joint those groups owning the same capability in user point of view which
1231 * allows that people tend to use through the device tree.
1232 */
1233
1234static const char *const mt7623_aud_clk_groups[] = { "aud_ext_clk0",
1235 "aud_ext_clk1", };
1236static const char *const mt7623_disp_pwm_groups[] = { "disp_pwm_0",
1237 "disp_pwm_1",
1238 "disp_pwm_2", };
1239static const char *const mt7623_ethernet_groups[] = { "esw_int", "esw_rst",
1240 "ephy", "mdc_mdio", };
1241static const char *const mt7623_ext_sdio_groups[] = { "ext_sdio", };
1242static const char *const mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg",
1243 "hdmi_i2c", "hdmi_rx",
1244 "hdmi_rx_i2c", };
1245static const char *const mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
1246 "i2c1_2", "i2c1_3", "i2c1_4",
1247 "i2c2_0", "i2c2_1", "i2c2_2",
1248 "i2c2_3", };
1249static const char *const mt7623_i2s_groups[] = { "i2s0", "i2s1",
1250 "i2s2_bclk_lrclk_mclk",
1251 "i2s3_bclk_lrclk_mclk",
1252 "i2s4", "i2s5",
1253 "i2s2_data_in", "i2s3_data_in",
1254 "i2s2_data_0", "i2s2_data_1",
1255 "i2s3_data_0", "i2s3_data_1",};
1256static const char *const mt7623_ir_groups[] = { "ir", };
1257static const char *const mt7623_lcd_groups[] = { "dsi_te", "lcm_rst",
1258 "mipi_tx", };
1259static const char *const mt7623_msdc_groups[] = { "msdc0", "msdc1",
1260 "msdc1_ins", "msdc1_wp_0",
1261 "msdc1_wp_1", "msdc1_wp_2",
1262 "msdc2", "msdc3", };
1263static const char *const mt7623_nandc_groups[] = { "nandc", "nandc_ceb0",
1264 "nandc_ceb1", };
1265static const char *const mt7623_otg_groups[] = { "otg_iddig0_0",
1266 "otg_iddig0_1",
1267 "otg_iddig0_2",
1268 "otg_iddig1_0",
1269 "otg_iddig1_1",
1270 "otg_iddig1_2",
1271 "otg_drv_vbus0_0",
1272 "otg_drv_vbus0_1",
1273 "otg_drv_vbus0_2",
1274 "otg_drv_vbus1_0",
1275 "otg_drv_vbus1_1",
1276 "otg_drv_vbus1_2", };
1277static const char *const mt7623_pcie_groups[] = { "pcie0_0_perst",
1278 "pcie0_1_perst",
1279 "pcie1_0_perst",
1280 "pcie1_1_perst",
1281 "pcie2_0_perst",
1282 "pcie2_1_perst",
1283 "pcie0_0_rev_perst",
1284 "pcie0_1_rev_perst",
1285 "pcie1_0_rev_perst",
1286 "pcie1_1_rev_perst",
1287 "pcie2_0_rev_perst",
1288 "pcie2_1_rev_perst",
1289 "pcie0_0_wake", "pcie0_1_wake",
1290 "pcie2_0_wake", "pcie2_1_wake",
1291 "pcie0_clkreq", "pcie1_clkreq",
1292 "pcie2_clkreq", };
1293static const char *const mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1",
1294 "pcm_clk_2", "pcm_clk_3",
1295 "pcm_clk_4", "pcm_clk_5",
1296 "pcm_clk_6", "pcm_sync_0",
1297 "pcm_sync_1", "pcm_sync_2",
1298 "pcm_sync_3", "pcm_sync_4",
1299 "pcm_sync_5", "pcm_sync_6",
1300 "pcm_rx_0", "pcm_rx_1",
1301 "pcm_rx_2", "pcm_rx_3",
1302 "pcm_rx_4", "pcm_rx_5",
1303 "pcm_rx_6", "pcm_tx_0",
1304 "pcm_tx_1", "pcm_tx_2",
1305 "pcm_tx_3", "pcm_tx_4",
1306 "pcm_tx_5", "pcm_tx_6", };
1307static const char *const mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
1308 "pwm_ch1_2", "pwm_ch2_0",
1309 "pwm_ch2_1", "pwm_ch2_2",
1310 "pwm_ch3_0", "pwm_ch3_1",
1311 "pwm_ch3_2", "pwm_ch4_0",
1312 "pwm_ch4_1", "pwm_ch4_2",
1313 "pwm_ch4_3", "pwm_ch5_0",
1314 "pwm_ch5_1", "pwm_ch5_2",
1315 "pwm_ch6_0", "pwm_ch6_1",
1316 "pwm_ch6_2", "pwm_ch6_3",
1317 "pwm_ch7_0", "pwm_ch7_1",
1318 "pwm_ch7_2", };
1319static const char *const mt7623_pwrap_groups[] = { "pwrap", };
1320static const char *const mt7623_rtc_groups[] = { "rtc", };
1321static const char *const mt7623_spi_groups[] = { "spi0", "spi2", "spi2", };
1322static const char *const mt7623_spdif_groups[] = { "spdif_in0_0",
1323 "spdif_in0_1", "spdif_in1_0",
1324 "spdif_in1_1", "spdif_out", };
1325static const char *const mt7623_uart_groups[] = { "uart0_0_txd_rxd",
1326 "uart0_1_txd_rxd",
1327 "uart0_2_txd_rxd",
1328 "uart0_3_txd_rxd",
1329 "uart1_0_txd_rxd",
1330 "uart1_1_txd_rxd",
1331 "uart1_2_txd_rxd",
1332 "uart2_0_txd_rxd",
1333 "uart2_1_txd_rxd",
1334 "uart3_txd_rxd",
1335 "uart0_rts_cts",
1336 "uart1_rts_cts",
1337 "uart2_rts_cts",
1338 "uart3_rts_cts", };
1339static const char *const mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
1340
1341static const struct mtk_function_desc mt7623_functions[] = {
1342 {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
1343 {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
1344 {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
1345 {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
1346 {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
1347 {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
1348 {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
1349 {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
1350 {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
1351 {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
1352 {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
1353 {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
1354 {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
1355 {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
1356 {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
1357 {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
1358 {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
1359 {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
1360 {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
1361 {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
1362 {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
1363};
1364
developer67873bd2023-07-19 17:16:37 +0800[diff] [blame]1365static const struct mtk_pinctrl_soc mt7623_data = {
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1366 .name = "mt7623_pinctrl",
1367 .reg_cal = mt7623_reg_cals,
1368 .pins = mt7623_pins,
1369 .npins = ARRAY_SIZE(mt7623_pins),
1370 .grps = mt7623_groups,
1371 .ngrps = ARRAY_SIZE(mt7623_groups),
1372 .funcs = mt7623_functions,
1373 .nfuncs = ARRAY_SIZE(mt7623_functions),
developer74d69012020-01-10 16:30:28 +0800[diff] [blame]1374 .gpio_mode = 0,
1375 .rev = MTK_PINCTRL_V1,
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1376};
1377
1378/*
1379 * There are some specific pins have mux functions greater than 8,
1380 * and if we want to switch thees high modes we need to disable
1381 * bonding constraints firstly.
1382 */
1383static void mt7623_bonding_disable(struct udevice *dev)
1384{
1385 mtk_rmw(dev, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
1386 mtk_rmw(dev, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
1387 mtk_rmw(dev, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
1388}
1389
1390static int mtk_pinctrl_mt7623_probe(struct udevice *dev)
1391{
1392 int err;
1393
1394 err = mtk_pinctrl_common_probe(dev, &mt7623_data);
1395 if (err)
1396 return err;
1397
1398 mt7623_bonding_disable(dev);
1399
1400 return 0;
1401}
1402
1403static const struct udevice_id mt7623_pctrl_match[] = {
1404 { .compatible = "mediatek,mt7623-pinctrl", },
1405 { /* sentinel */ }
1406};
1407
1408U_BOOT_DRIVER(mt7623_pinctrl) = {
1409 .name = "mt7623_pinctrl",
1410 .id = UCLASS_PINCTRL,
1411 .of_match = mt7623_pctrl_match,
1412 .ops = &mtk_pinctrl_ops,
1413 .probe = mtk_pinctrl_mt7623_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]1414 .priv_auto = sizeof(struct mtk_pinctrl_priv),
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame]1415};