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git01.mediatek.com / filogic / uboot / 5c1111c7e595a2034f40941de88a03dfebc62356 / . / drivers / pinctrl / mediatek / pinctrl-mt7623.c
blob: fd37dfa442959c1a1e12cc826190cfef61c75659 [file] [log] [blame]
developer5c1111c2018-11-15 10:07:59 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 */
6
7#include <dm.h>
8
9#include "pinctrl-mtk-common.h"
10
11#define PIN_BOND_REG0 0xb10
12#define PIN_BOND_REG1 0xf20
13#define PIN_BOND_REG2 0xef0
14#define BOND_PCIE_CLR (0x77 << 3)
15#define BOND_I2S_CLR 0x3
16#define BOND_MSDC0E_CLR 0x1
17
18#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
19 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
20 _x_bits, 15, false)
21
22#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
23 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
24 _x_bits, 16, false)
25
26#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
27 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
28 _x_bits, 16, true)
29
30static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
31 PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
32};
33
34static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
35 PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
36 PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
37};
38
39static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
40 PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
41};
42
43static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
44 PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
45};
46
47static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
48 PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
49 PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
50 PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
51 PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
52 PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
53 PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
54 PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
55 PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
56 PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
57 PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
58 PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
59 PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
60 PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
61 PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
62 PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
63 PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
64 PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
65 PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
66 PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
67 PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
68 PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
69 PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
70 PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
71 PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
72 PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
73 PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
74 PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
75 PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
76 PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
77 PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
78 PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
79 PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
80 PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
81 PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
82 PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
83 PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1),
84 PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1),
85 PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1),
86 PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1),
87 PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1),
88 PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1),
89 PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1),
90 PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1),
91 PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1),
92 PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1),
93 PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1),
94 PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1),
95 PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1),
96 PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1),
97 PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1),
98 PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1),
99 PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1),
100 PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1),
101 PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1),
102 PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1),
103 PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1),
104 PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1),
105 PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1),
106 PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1),
107 PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1),
108 PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1),
109 PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1),
110 PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1),
111 PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1),
112};
113
114static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = {
115 PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1),
116 PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1),
117 PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1),
118 PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1),
119 PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1),
120 PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1),
121 PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1),
122 PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1),
123 PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1),
124 PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1),
125 PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1),
126 PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1),
127 PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1),
128 PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1),
129 PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1),
130 PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1),
131 PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1),
132 PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1),
133 PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1),
134 PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1),
135 PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1),
136 PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1),
137 PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1),
138 PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1),
139 PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1),
140 PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1),
141 PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1),
142 PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1),
143 PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1),
144 PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1),
145 PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1),
146 PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1),
147 PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1),
148 PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1),
149 PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1),
150 PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1),
151 PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1),
152 PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1),
153 PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1),
154 PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1),
155 PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1),
156 PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1),
157 PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1),
158 PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1),
159 PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1),
160 PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1),
161 PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1),
162 PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1),
163 PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1),
164 PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1),
165 PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1),
166 PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1),
167 PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1),
168 PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1),
169 PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1),
170 PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1),
171 PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1),
172 PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1),
173 PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1),
174 PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1),
175 PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1),
176 PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1),
177 PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1),
178 PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1),
179 PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1),
180 PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1),
181 PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1),
182 PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1),
183 PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1),
184 PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10),
185 PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1),
186 PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1),
187 PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1),
188 PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1),
189 PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1),
190 PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1),
191 PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1),
192 PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1),
193 PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1),
194 PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1),
195 PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1),
196 PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1),
197 PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1),
198 PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1),
199 PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1),
200};
201
202static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = {
203 PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1),
204};
205
206static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = {
207 PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1),
208};
209
210static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {
211 PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4),
212 PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4),
213 PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4),
214 PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4),
215 PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4),
216 PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4),
217 PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4),
218 PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4),
219 PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4),
220 PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4),
221 PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4),
222 PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4),
223 PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4),
224 PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4),
225 PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4),
226 PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4),
227 PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4),
228 PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4),
229 PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4),
230 PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4),
231 PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4),
232 PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4),
233 PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4),
234 PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4),
235 PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4),
236 PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4),
237 PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4),
238 PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4),
239 PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4),
240 PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4),
241 PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4),
242 PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4),
243 PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4),
244 PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4),
245 PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4),
246 PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4),
247 PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4),
248 PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4),
249 PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4),
250 PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4),
251 PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4),
252 PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4),
253 PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4),
254 PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4),
255 PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4),
256 PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4),
257 PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4),
258 PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4),
259 PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4),
260 PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4),
261 PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4),
262 PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4),
263};
264
265static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
266 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
267 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
268 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),
269 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range),
270 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range),
271 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range),
272 [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range),
273 [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range),
274 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range),
275};
276
277static const struct mtk_pin_desc mt7623_pins[] = {
278 MTK_PIN(0, "PWRAP_SPI0_MI", DRV_GRP3),
279 MTK_PIN(1, "PWRAP_SPI0_MO", DRV_GRP3),
280 MTK_PIN(2, "PWRAP_INT", DRV_GRP3),
281 MTK_PIN(3, "PWRAP_SPI0_CK", DRV_GRP3),
282 MTK_PIN(4, "PWRAP_SPI0_CSN", DRV_GRP3),
283 MTK_PIN(5, "PWRAP_SPI0_CK2", DRV_GRP3),
284 MTK_PIN(6, "PWRAP_SPI0_CSN2", DRV_GRP3),
285 MTK_PIN(7, "SPI1_CSN", DRV_GRP3),
286 MTK_PIN(8, "SPI1_MI", DRV_GRP3),
287 MTK_PIN(9, "SPI1_MO", DRV_GRP3),
288 MTK_PIN(10, "RTC32K_CK", DRV_GRP3),
289 MTK_PIN(11, "WATCHDOG", DRV_GRP3),
290 MTK_PIN(12, "SRCLKENA", DRV_GRP3),
291 MTK_PIN(13, "SRCLKENAI", DRV_GRP3),
292 MTK_PIN(14, "URXD2", DRV_GRP1),
293 MTK_PIN(15, "UTXD2", DRV_GRP1),
294 MTK_PIN(16, "I2S5_DATA_IN", DRV_GRP1),
295 MTK_PIN(17, "I2S5_BCK", DRV_GRP1),
296 MTK_PIN(18, "PCM_CLK", DRV_GRP1),
297 MTK_PIN(19, "PCM_SYNC", DRV_GRP1),
298 MTK_PIN(20, "PCM_RX", DRV_GRP1),
299 MTK_PIN(21, "PCM_TX", DRV_GRP1),
300 MTK_PIN(22, "EINT0", DRV_GRP1),
301 MTK_PIN(23, "EINT1", DRV_GRP1),
302 MTK_PIN(24, "EINT2", DRV_GRP1),
303 MTK_PIN(25, "EINT3", DRV_GRP1),
304 MTK_PIN(26, "EINT4", DRV_GRP1),
305 MTK_PIN(27, "EINT5", DRV_GRP1),
306 MTK_PIN(28, "EINT6", DRV_GRP1),
307 MTK_PIN(29, "EINT7", DRV_GRP1),
308 MTK_PIN(30, "I2S5_LRCK", DRV_GRP1),
309 MTK_PIN(31, "I2S5_MCLK", DRV_GRP1),
310 MTK_PIN(32, "I2S5_DATA", DRV_GRP1),
311 MTK_PIN(33, "I2S1_DATA", DRV_GRP1),
312 MTK_PIN(34, "I2S1_DATA_IN", DRV_GRP1),
313 MTK_PIN(35, "I2S1_BCK", DRV_GRP1),
314 MTK_PIN(36, "I2S1_LRCK", DRV_GRP1),
315 MTK_PIN(37, "I2S1_MCLK", DRV_GRP1),
316 MTK_PIN(38, "I2S2_DATA", DRV_GRP1),
317 MTK_PIN(39, "JTMS", DRV_GRP3),
318 MTK_PIN(40, "JTCK", DRV_GRP3),
319 MTK_PIN(41, "JTDI", DRV_GRP3),
320 MTK_PIN(42, "JTDO", DRV_GRP3),
321 MTK_PIN(43, "NCLE", DRV_GRP1),
322 MTK_PIN(44, "NCEB1", DRV_GRP1),
323 MTK_PIN(45, "NCEB0", DRV_GRP1),
324 MTK_PIN(46, "IR", DRV_FIXED),
325 MTK_PIN(47, "NREB", DRV_GRP1),
326 MTK_PIN(48, "NRNB", DRV_GRP1),
327 MTK_PIN(49, "I2S0_DATA", DRV_GRP1),
328 MTK_PIN(50, "I2S2_BCK", DRV_GRP1),
329 MTK_PIN(51, "I2S2_DATA_IN", DRV_GRP1),
330 MTK_PIN(52, "I2S2_LRCK", DRV_GRP1),
331 MTK_PIN(53, "SPI0_CSN", DRV_GRP1),
332 MTK_PIN(54, "SPI0_CK", DRV_GRP1),
333 MTK_PIN(55, "SPI0_MI", DRV_GRP1),
334 MTK_PIN(56, "SPI0_MO", DRV_GRP1),
335 MTK_PIN(57, "SDA1", DRV_FIXED),
336 MTK_PIN(58, "SCL1", DRV_FIXED),
337 MTK_PIN(59, "RAMBUF_I_CLK", DRV_FIXED),
338 MTK_PIN(60, "WB_RSTB", DRV_GRP3),
339 MTK_PIN(61, "F2W_DATA", DRV_GRP3),
340 MTK_PIN(62, "F2W_CLK", DRV_GRP3),
341 MTK_PIN(63, "WB_SCLK", DRV_GRP3),
342 MTK_PIN(64, "WB_SDATA", DRV_GRP3),
343 MTK_PIN(65, "WB_SEN", DRV_GRP3),
344 MTK_PIN(66, "WB_CRTL0", DRV_GRP3),
345 MTK_PIN(67, "WB_CRTL1", DRV_GRP3),
346 MTK_PIN(68, "WB_CRTL2", DRV_GRP3),
347 MTK_PIN(69, "WB_CRTL3", DRV_GRP3),
348 MTK_PIN(70, "WB_CRTL4", DRV_GRP3),
349 MTK_PIN(71, "WB_CRTL5", DRV_GRP3),
350 MTK_PIN(72, "I2S0_DATA_IN", DRV_GRP1),
351 MTK_PIN(73, "I2S0_LRCK", DRV_GRP1),
352 MTK_PIN(74, "I2S0_BCK", DRV_GRP1),
353 MTK_PIN(75, "SDA0", DRV_FIXED),
354 MTK_PIN(76, "SCL0", DRV_FIXED),
355 MTK_PIN(77, "SDA2", DRV_FIXED),
356 MTK_PIN(78, "SCL2", DRV_FIXED),
357 MTK_PIN(79, "URXD0", DRV_FIXED),
358 MTK_PIN(80, "UTXD0", DRV_FIXED),
359 MTK_PIN(81, "URXD1", DRV_FIXED),
360 MTK_PIN(82, "UTXD1", DRV_FIXED),
361 MTK_PIN(83, "LCM_RST", DRV_FIXED),
362 MTK_PIN(84, "DSI_TE", DRV_FIXED),
363 MTK_PIN(85, "MSDC2_CMD", DRV_GRP4),
364 MTK_PIN(86, "MSDC2_CLK", DRV_GRP4),
365 MTK_PIN(87, "MSDC2_DAT0", DRV_GRP4),
366 MTK_PIN(88, "MSDC2_DAT1", DRV_GRP4),
367 MTK_PIN(89, "MSDC2_DAT2", DRV_GRP4),
368 MTK_PIN(90, "MSDC2_DAT3", DRV_GRP4),
369 MTK_PIN(91, "TDN3", DRV_FIXED),
370 MTK_PIN(92, "TDP3", DRV_FIXED),
371 MTK_PIN(93, "TDN2", DRV_FIXED),
372 MTK_PIN(94, "TDP2", DRV_FIXED),
373 MTK_PIN(95, "TCN", DRV_FIXED),
374 MTK_PIN(96, "TCP", DRV_FIXED),
375 MTK_PIN(97, "TDN1", DRV_FIXED),
376 MTK_PIN(98, "TDP1", DRV_FIXED),
377 MTK_PIN(99, "TDN0", DRV_FIXED),
378 MTK_PIN(100, "TDP0", DRV_FIXED),
379 MTK_PIN(101, "SPI2_CSN", DRV_FIXED),
380 MTK_PIN(102, "SPI2_MI", DRV_FIXED),
381 MTK_PIN(103, "SPI2_MO", DRV_FIXED),
382 MTK_PIN(104, "SPI2_CLK", DRV_FIXED),
383 MTK_PIN(105, "MSDC1_CMD", DRV_GRP4),
384 MTK_PIN(106, "MSDC1_CLK", DRV_GRP4),
385 MTK_PIN(107, "MSDC1_DAT0", DRV_GRP4),
386 MTK_PIN(108, "MSDC1_DAT1", DRV_GRP4),
387 MTK_PIN(109, "MSDC1_DAT2", DRV_GRP4),
388 MTK_PIN(110, "MSDC1_DAT3", DRV_GRP4),
389 MTK_PIN(111, "MSDC0_DAT7", DRV_GRP4),
390 MTK_PIN(112, "MSDC0_DAT6", DRV_GRP4),
391 MTK_PIN(113, "MSDC0_DAT5", DRV_GRP4),
392 MTK_PIN(114, "MSDC0_DAT4", DRV_GRP4),
393 MTK_PIN(115, "MSDC0_RSTB", DRV_GRP4),
394 MTK_PIN(116, "MSDC0_CMD", DRV_GRP4),
395 MTK_PIN(117, "MSDC0_CLK", DRV_GRP4),
396 MTK_PIN(118, "MSDC0_DAT3", DRV_GRP4),
397 MTK_PIN(119, "MSDC0_DAT2", DRV_GRP4),
398 MTK_PIN(120, "MSDC0_DAT1", DRV_GRP4),
399 MTK_PIN(121, "MSDC0_DAT0", DRV_GRP4),
400 MTK_PIN(122, "CEC", DRV_FIXED),
401 MTK_PIN(123, "HTPLG", DRV_FIXED),
402 MTK_PIN(124, "HDMISCK", DRV_FIXED),
403 MTK_PIN(125, "HDMISD", DRV_FIXED),
404 MTK_PIN(126, "I2S0_MCLK", DRV_GRP1),
405 MTK_PIN(127, "RAMBUF_IDATA0", DRV_FIXED),
406 MTK_PIN(128, "RAMBUF_IDATA1", DRV_FIXED),
407 MTK_PIN(129, "RAMBUF_IDATA2", DRV_FIXED),
408 MTK_PIN(130, "RAMBUF_IDATA3", DRV_FIXED),
409 MTK_PIN(131, "RAMBUF_IDATA4", DRV_FIXED),
410 MTK_PIN(132, "RAMBUF_IDATA5", DRV_FIXED),
411 MTK_PIN(133, "RAMBUF_IDATA6", DRV_FIXED),
412 MTK_PIN(134, "RAMBUF_IDATA7", DRV_FIXED),
413 MTK_PIN(135, "RAMBUF_IDATA8", DRV_FIXED),
414 MTK_PIN(136, "RAMBUF_IDATA9", DRV_FIXED),
415 MTK_PIN(137, "RAMBUF_IDATA10", DRV_FIXED),
416 MTK_PIN(138, "RAMBUF_IDATA11", DRV_FIXED),
417 MTK_PIN(139, "RAMBUF_IDATA12", DRV_FIXED),
418 MTK_PIN(140, "RAMBUF_IDATA13", DRV_FIXED),
419 MTK_PIN(141, "RAMBUF_IDATA14", DRV_FIXED),
420 MTK_PIN(142, "RAMBUF_IDATA15", DRV_FIXED),
421 MTK_PIN(143, "RAMBUF_ODATA0", DRV_FIXED),
422 MTK_PIN(144, "RAMBUF_ODATA1", DRV_FIXED),
423 MTK_PIN(145, "RAMBUF_ODATA2", DRV_FIXED),
424 MTK_PIN(146, "RAMBUF_ODATA3", DRV_FIXED),
425 MTK_PIN(147, "RAMBUF_ODATA4", DRV_FIXED),
426 MTK_PIN(148, "RAMBUF_ODATA5", DRV_FIXED),
427 MTK_PIN(149, "RAMBUF_ODATA6", DRV_FIXED),
428 MTK_PIN(150, "RAMBUF_ODATA7", DRV_FIXED),
429 MTK_PIN(151, "RAMBUF_ODATA8", DRV_FIXED),
430 MTK_PIN(152, "RAMBUF_ODATA9", DRV_FIXED),
431 MTK_PIN(153, "RAMBUF_ODATA10", DRV_FIXED),
432 MTK_PIN(154, "RAMBUF_ODATA11", DRV_FIXED),
433 MTK_PIN(155, "RAMBUF_ODATA12", DRV_FIXED),
434 MTK_PIN(156, "RAMBUF_ODATA13", DRV_FIXED),
435 MTK_PIN(157, "RAMBUF_ODATA14", DRV_FIXED),
436 MTK_PIN(158, "RAMBUF_ODATA15", DRV_FIXED),
437 MTK_PIN(159, "RAMBUF_BE0", DRV_FIXED),
438 MTK_PIN(160, "RAMBUF_BE1", DRV_FIXED),
439 MTK_PIN(161, "AP2PT_INT", DRV_FIXED),
440 MTK_PIN(162, "AP2PT_INT_CLR", DRV_FIXED),
441 MTK_PIN(163, "PT2AP_INT", DRV_FIXED),
442 MTK_PIN(164, "PT2AP_INT_CLR", DRV_FIXED),
443 MTK_PIN(165, "AP2UP_INT", DRV_FIXED),
444 MTK_PIN(166, "AP2UP_INT_CLR", DRV_FIXED),
445 MTK_PIN(167, "UP2AP_INT", DRV_FIXED),
446 MTK_PIN(168, "UP2AP_INT_CLR", DRV_FIXED),
447 MTK_PIN(169, "RAMBUF_ADDR0", DRV_FIXED),
448 MTK_PIN(170, "RAMBUF_ADDR1", DRV_FIXED),
449 MTK_PIN(171, "RAMBUF_ADDR2", DRV_FIXED),
450 MTK_PIN(172, "RAMBUF_ADDR3", DRV_FIXED),
451 MTK_PIN(173, "RAMBUF_ADDR4", DRV_FIXED),
452 MTK_PIN(174, "RAMBUF_ADDR5", DRV_FIXED),
453 MTK_PIN(175, "RAMBUF_ADDR6", DRV_FIXED),
454 MTK_PIN(176, "RAMBUF_ADDR7", DRV_FIXED),
455 MTK_PIN(177, "RAMBUF_ADDR8", DRV_FIXED),
456 MTK_PIN(178, "RAMBUF_ADDR9", DRV_FIXED),
457 MTK_PIN(179, "RAMBUF_ADDR10", DRV_FIXED),
458 MTK_PIN(180, "RAMBUF_RW", DRV_FIXED),
459 MTK_PIN(181, "RAMBUF_LAST", DRV_FIXED),
460 MTK_PIN(182, "RAMBUF_HP", DRV_FIXED),
461 MTK_PIN(183, "RAMBUF_REQ", DRV_FIXED),
462 MTK_PIN(184, "RAMBUF_ALE", DRV_FIXED),
463 MTK_PIN(185, "RAMBUF_DLE", DRV_FIXED),
464 MTK_PIN(186, "RAMBUF_WDLE", DRV_FIXED),
465 MTK_PIN(187, "RAMBUF_O_CLK", DRV_FIXED),
466 MTK_PIN(188, "I2S2_MCLK", DRV_GRP1),
467 MTK_PIN(189, "I2S3_DATA", DRV_GRP1),
468 MTK_PIN(190, "I2S3_DATA_IN", DRV_GRP1),
469 MTK_PIN(191, "I2S3_BCK", DRV_GRP1),
470 MTK_PIN(192, "I2S3_LRCK", DRV_GRP1),
471 MTK_PIN(193, "I2S3_MCLK", DRV_GRP1),
472 MTK_PIN(194, "I2S4_DATA", DRV_GRP1),
473 MTK_PIN(195, "I2S4_DATA_IN", DRV_GRP1),
474 MTK_PIN(196, "I2S4_BCK", DRV_GRP1),
475 MTK_PIN(197, "I2S4_LRCK", DRV_GRP1),
476 MTK_PIN(198, "I2S4_MCLK", DRV_GRP1),
477 MTK_PIN(199, "SPI1_CLK", DRV_GRP3),
478 MTK_PIN(200, "SPDIF_OUT", DRV_GRP1),
479 MTK_PIN(201, "SPDIF_IN0", DRV_GRP1),
480 MTK_PIN(202, "SPDIF_IN1", DRV_GRP1),
481 MTK_PIN(203, "PWM0", DRV_GRP1),
482 MTK_PIN(204, "PWM1", DRV_GRP1),
483 MTK_PIN(205, "PWM2", DRV_GRP1),
484 MTK_PIN(206, "PWM3", DRV_GRP1),
485 MTK_PIN(207, "PWM4", DRV_GRP1),
486 MTK_PIN(208, "AUD_EXT_CK1", DRV_GRP1),
487 MTK_PIN(209, "AUD_EXT_CK2", DRV_GRP1),
488 MTK_PIN(210, "AUD_CLOCK", DRV_GRP3),
489 MTK_PIN(211, "DVP_RESET", DRV_GRP3),
490 MTK_PIN(212, "DVP_CLOCK", DRV_GRP3),
491 MTK_PIN(213, "DVP_CS", DRV_GRP3),
492 MTK_PIN(214, "DVP_CK", DRV_GRP3),
493 MTK_PIN(215, "DVP_DI", DRV_GRP3),
494 MTK_PIN(216, "DVP_DO", DRV_GRP3),
495 MTK_PIN(217, "AP_CS", DRV_GRP3),
496 MTK_PIN(218, "AP_CK", DRV_GRP3),
497 MTK_PIN(219, "AP_DI", DRV_GRP3),
498 MTK_PIN(220, "AP_DO", DRV_GRP3),
499 MTK_PIN(221, "DVD_BCLK", DRV_GRP3),
500 MTK_PIN(222, "T8032_CLK", DRV_GRP3),
501 MTK_PIN(223, "AP_BCLK", DRV_GRP3),
502 MTK_PIN(224, "HOST_CS", DRV_GRP3),
503 MTK_PIN(225, "HOST_CK", DRV_GRP3),
504 MTK_PIN(226, "HOST_DO0", DRV_GRP3),
505 MTK_PIN(227, "HOST_DO1", DRV_GRP3),
506 MTK_PIN(228, "SLV_CS", DRV_GRP3),
507 MTK_PIN(229, "SLV_CK", DRV_GRP3),
508 MTK_PIN(230, "SLV_DI0", DRV_GRP3),
509 MTK_PIN(231, "SLV_DI1", DRV_GRP3),
510 MTK_PIN(232, "AP2DSP_INT", DRV_GRP3),
511 MTK_PIN(233, "AP2DSP_INT_CLR", DRV_GRP3),
512 MTK_PIN(234, "DSP2AP_INT", DRV_GRP3),
513 MTK_PIN(235, "DSP2AP_INT_CLR", DRV_GRP3),
514 MTK_PIN(236, "EXT_SDIO3", DRV_GRP1),
515 MTK_PIN(237, "EXT_SDIO2", DRV_GRP1),
516 MTK_PIN(238, "EXT_SDIO1", DRV_GRP1),
517 MTK_PIN(239, "EXT_SDIO0", DRV_GRP1),
518 MTK_PIN(240, "EXT_XCS", DRV_GRP1),
519 MTK_PIN(241, "EXT_SCK", DRV_GRP1),
520 MTK_PIN(242, "URTS2", DRV_GRP1),
521 MTK_PIN(243, "UCTS2", DRV_GRP1),
522 MTK_PIN(244, "HDMI_SDA_RX", DRV_FIXED),
523 MTK_PIN(245, "HDMI_SCL_RX", DRV_FIXED),
524 MTK_PIN(246, "MHL_SENCE", DRV_FIXED),
525 MTK_PIN(247, "HDMI_HPD_CBUS_RX", DRV_FIXED),
526 MTK_PIN(248, "HDMI_TESTOUTP_RX", DRV_GRP1),
527 MTK_PIN(249, "MSDC0E_RSTB", DRV_GRP4),
528 MTK_PIN(250, "MSDC0E_DAT7", DRV_GRP4),
529 MTK_PIN(251, "MSDC0E_DAT6", DRV_GRP4),
530 MTK_PIN(252, "MSDC0E_DAT5", DRV_GRP4),
531 MTK_PIN(253, "MSDC0E_DAT4", DRV_GRP4),
532 MTK_PIN(254, "MSDC0E_DAT3", DRV_GRP4),
533 MTK_PIN(255, "MSDC0E_DAT2", DRV_GRP4),
534 MTK_PIN(256, "MSDC0E_DAT1", DRV_GRP4),
535 MTK_PIN(257, "MSDC0E_DAT0", DRV_GRP4),
536 MTK_PIN(258, "MSDC0E_CMD", DRV_GRP4),
537 MTK_PIN(259, "MSDC0E_CLK", DRV_GRP4),
538 MTK_PIN(260, "MSDC0E_DSL", DRV_GRP4),
539 MTK_PIN(261, "MSDC1_INS", DRV_GRP4),
540 MTK_PIN(262, "G2_TXEN", DRV_GRP1),
541 MTK_PIN(263, "G2_TXD3", DRV_GRP1),
542 MTK_PIN(264, "G2_TXD2", DRV_GRP1),
543 MTK_PIN(265, "G2_TXD1", DRV_GRP1),
544 MTK_PIN(266, "G2_TXD0", DRV_GRP1),
545 MTK_PIN(267, "G2_TXC", DRV_GRP1),
546 MTK_PIN(268, "G2_RXC", DRV_GRP1),
547 MTK_PIN(269, "G2_RXD0", DRV_GRP1),
548 MTK_PIN(270, "G2_RXD1", DRV_GRP1),
549 MTK_PIN(271, "G2_RXD2", DRV_GRP1),
550 MTK_PIN(272, "G2_RXD3", DRV_GRP1),
551 MTK_PIN(273, "ESW_INT", DRV_GRP1),
552 MTK_PIN(274, "G2_RXDV", DRV_GRP1),
553 MTK_PIN(275, "MDC", DRV_GRP1),
554 MTK_PIN(276, "MDIO", DRV_GRP1),
555 MTK_PIN(277, "ESW_RST", DRV_GRP1),
556 MTK_PIN(278, "JTAG_RESET", DRV_GRP3),
557 MTK_PIN(279, "USB3_RES_BOND", DRV_GRP1),
558};
559
560/* List all groups consisting of these pins dedicated to the enablement of
561 * certain hardware block and the corresponding mode for all of the pins.
562 * The hardware probably has multiple combinations of these pinouts.
563 */
564
565/* AUDIO EXT CLK */
566static int mt7623_aud_ext_clk0_pins[] = { 208, };
567static int mt7623_aud_ext_clk0_funcs[] = { 1, };
568static int mt7623_aud_ext_clk1_pins[] = { 209, };
569static int mt7623_aud_ext_clk1_funcs[] = { 1, };
570
571/* DISP PWM */
572static int mt7623_disp_pwm_0_pins[] = { 72, };
573static int mt7623_disp_pwm_0_funcs[] = { 5, };
574static int mt7623_disp_pwm_1_pins[] = { 203, };
575static int mt7623_disp_pwm_1_funcs[] = { 2, };
576static int mt7623_disp_pwm_2_pins[] = { 208, };
577static int mt7623_disp_pwm_2_funcs[] = { 5, };
578
579/* ESW */
580static int mt7623_esw_int_pins[] = { 273, };
581static int mt7623_esw_int_funcs[] = { 1, };
582static int mt7623_esw_rst_pins[] = { 277, };
583static int mt7623_esw_rst_funcs[] = { 1, };
584
585/* EPHY */
586static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
587 269, 270, 271, 272, 274, };
588static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
589
590/* EXT_SDIO */
591static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
592static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
593
594/* HDMI RX */
595static int mt7623_hdmi_rx_pins[] = { 247, 248, };
596static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
597static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
598static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
599
600/* HDMI TX */
601static int mt7623_hdmi_cec_pins[] = { 122, };
602static int mt7623_hdmi_cec_funcs[] = { 1, };
603static int mt7623_hdmi_htplg_pins[] = { 123, };
604static int mt7623_hdmi_htplg_funcs[] = { 1, };
605static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
606static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
607
608/* I2C */
609static int mt7623_i2c0_pins[] = { 75, 76, };
610static int mt7623_i2c0_funcs[] = { 1, 1, };
611static int mt7623_i2c1_0_pins[] = { 57, 58, };
612static int mt7623_i2c1_0_funcs[] = { 1, 1, };
613static int mt7623_i2c1_1_pins[] = { 242, 243, };
614static int mt7623_i2c1_1_funcs[] = { 4, 4, };
615static int mt7623_i2c1_2_pins[] = { 85, 86, };
616static int mt7623_i2c1_2_funcs[] = { 3, 3, };
617static int mt7623_i2c1_3_pins[] = { 105, 106, };
618static int mt7623_i2c1_3_funcs[] = { 3, 3, };
619static int mt7623_i2c1_4_pins[] = { 124, 125, };
620static int mt7623_i2c1_4_funcs[] = { 4, 4, };
621static int mt7623_i2c2_0_pins[] = { 77, 78, };
622static int mt7623_i2c2_0_funcs[] = { 1, 1, };
623static int mt7623_i2c2_1_pins[] = { 89, 90, };
624static int mt7623_i2c2_1_funcs[] = { 3, 3, };
625static int mt7623_i2c2_2_pins[] = { 109, 110, };
626static int mt7623_i2c2_2_funcs[] = { 3, 3, };
627static int mt7623_i2c2_3_pins[] = { 122, 123, };
628static int mt7623_i2c2_3_funcs[] = { 4, 4, };
629
630/* I2S */
631static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
632static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
633static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
634static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
635static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
636static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
637static int mt7623_i2s2_data_in_pins[] = { 51, };
638static int mt7623_i2s2_data_in_funcs[] = { 1, };
639static int mt7623_i2s2_data_0_pins[] = { 203, };
640static int mt7623_i2s2_data_0_funcs[] = { 9, };
641static int mt7623_i2s2_data_1_pins[] = { 38, };
642static int mt7623_i2s2_data_1_funcs[] = { 4, };
643static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
644static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
645static int mt7623_i2s3_data_in_pins[] = { 190, };
646static int mt7623_i2s3_data_in_funcs[] = { 1, };
647static int mt7623_i2s3_data_0_pins[] = { 204, };
648static int mt7623_i2s3_data_0_funcs[] = { 9, };
649static int mt7623_i2s3_data_1_pins[] = { 2, };
650static int mt7623_i2s3_data_1_funcs[] = { 0, };
651static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
652static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
653static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
654static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
655
656/* IR */
657static int mt7623_ir_pins[] = { 46, };
658static int mt7623_ir_funcs[] = { 1, };
659
660/* LCD */
661static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
662 99, 100, };
663static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
664static int mt7623_dsi_te_pins[] = { 84, };
665static int mt7623_dsi_te_funcs[] = { 1, };
666static int mt7623_lcm_rst_pins[] = { 83, };
667static int mt7623_lcm_rst_funcs[] = { 1, };
668
669/* MDC/MDIO */
670static int mt7623_mdc_mdio_pins[] = { 275, 276, };
671static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
672
673/* MSDC */
674static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
675 119, 120, 121, };
676static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
677static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
678static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
679static int mt7623_msdc1_ins_pins[] = { 261, };
680static int mt7623_msdc1_ins_funcs[] = { 1, };
681static int mt7623_msdc1_wp_0_pins[] = { 29, };
682static int mt7623_msdc1_wp_0_funcs[] = { 1, };
683static int mt7623_msdc1_wp_1_pins[] = { 55, };
684static int mt7623_msdc1_wp_1_funcs[] = { 3, };
685static int mt7623_msdc1_wp_2_pins[] = { 209, };
686static int mt7623_msdc1_wp_2_funcs[] = { 2, };
687static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
688static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
689static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
690 257, 258, 259, 260, };
691static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
692
693/* NAND */
694static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
695 116, 117, 118, 119, 120, 121, };
696static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
697 4, 4, };
698static int mt7623_nandc_ceb0_pins[] = { 45, };
699static int mt7623_nandc_ceb0_funcs[] = { 1, };
700static int mt7623_nandc_ceb1_pins[] = { 44, };
701static int mt7623_nandc_ceb1_funcs[] = { 1, };
702
703/* RTC */
704static int mt7623_rtc_pins[] = { 10, };
705static int mt7623_rtc_funcs[] = { 1, };
706
707/* OTG */
708static int mt7623_otg_iddig0_0_pins[] = { 29, };
709static int mt7623_otg_iddig0_0_funcs[] = { 1, };
710static int mt7623_otg_iddig0_1_pins[] = { 44, };
711static int mt7623_otg_iddig0_1_funcs[] = { 2, };
712static int mt7623_otg_iddig0_2_pins[] = { 236, };
713static int mt7623_otg_iddig0_2_funcs[] = { 2, };
714static int mt7623_otg_iddig1_0_pins[] = { 27, };
715static int mt7623_otg_iddig1_0_funcs[] = { 2, };
716static int mt7623_otg_iddig1_1_pins[] = { 47, };
717static int mt7623_otg_iddig1_1_funcs[] = { 2, };
718static int mt7623_otg_iddig1_2_pins[] = { 238, };
719static int mt7623_otg_iddig1_2_funcs[] = { 2, };
720static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
721static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
722static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
723static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
724static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
725static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
726static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
727static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
728static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
729static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
730static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
731static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
732
733/* PCIE */
734static int mt7623_pcie0_0_perst_pins[] = { 208, };
735static int mt7623_pcie0_0_perst_funcs[] = { 3, };
736static int mt7623_pcie0_1_perst_pins[] = { 22, };
737static int mt7623_pcie0_1_perst_funcs[] = { 2, };
738static int mt7623_pcie1_0_perst_pins[] = { 209, };
739static int mt7623_pcie1_0_perst_funcs[] = { 3, };
740static int mt7623_pcie1_1_perst_pins[] = { 23, };
741static int mt7623_pcie1_1_perst_funcs[] = { 2, };
742static int mt7623_pcie2_0_perst_pins[] = { 24, };
743static int mt7623_pcie2_0_perst_funcs[] = { 2, };
744static int mt7623_pcie2_1_perst_pins[] = { 29, };
745static int mt7623_pcie2_1_perst_funcs[] = { 6, };
746static int mt7623_pcie0_0_wake_pins[] = { 28, };
747static int mt7623_pcie0_0_wake_funcs[] = { 6, };
748static int mt7623_pcie0_1_wake_pins[] = { 251, };
749static int mt7623_pcie0_1_wake_funcs[] = { 6, };
750static int mt7623_pcie1_0_wake_pins[] = { 27, };
751static int mt7623_pcie1_0_wake_funcs[] = { 6, };
752static int mt7623_pcie1_1_wake_pins[] = { 253, };
753static int mt7623_pcie1_1_wake_funcs[] = { 6, };
754static int mt7623_pcie2_0_wake_pins[] = { 26, };
755static int mt7623_pcie2_0_wake_funcs[] = { 6, };
756static int mt7623_pcie2_1_wake_pins[] = { 255, };
757static int mt7623_pcie2_1_wake_funcs[] = { 6, };
758static int mt7623_pcie0_clkreq_pins[] = { 250, };
759static int mt7623_pcie0_clkreq_funcs[] = { 6, };
760static int mt7623_pcie1_clkreq_pins[] = { 252, };
761static int mt7623_pcie1_clkreq_funcs[] = { 6, };
762static int mt7623_pcie2_clkreq_pins[] = { 254, };
763static int mt7623_pcie2_clkreq_funcs[] = { 6, };
764/* the pcie_*_rev are only used for MT7623 */
765static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
766static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
767static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
768static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
769static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
770static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
771static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
772static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
773static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
774static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
775static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
776static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
777
778/* PCM */
779static int mt7623_pcm_clk_0_pins[] = { 18, };
780static int mt7623_pcm_clk_0_funcs[] = { 1, };
781static int mt7623_pcm_clk_1_pins[] = { 17, };
782static int mt7623_pcm_clk_1_funcs[] = { 3, };
783static int mt7623_pcm_clk_2_pins[] = { 35, };
784static int mt7623_pcm_clk_2_funcs[] = { 3, };
785static int mt7623_pcm_clk_3_pins[] = { 50, };
786static int mt7623_pcm_clk_3_funcs[] = { 3, };
787static int mt7623_pcm_clk_4_pins[] = { 74, };
788static int mt7623_pcm_clk_4_funcs[] = { 3, };
789static int mt7623_pcm_clk_5_pins[] = { 191, };
790static int mt7623_pcm_clk_5_funcs[] = { 3, };
791static int mt7623_pcm_clk_6_pins[] = { 196, };
792static int mt7623_pcm_clk_6_funcs[] = { 3, };
793static int mt7623_pcm_sync_0_pins[] = { 19, };
794static int mt7623_pcm_sync_0_funcs[] = { 1, };
795static int mt7623_pcm_sync_1_pins[] = { 30, };
796static int mt7623_pcm_sync_1_funcs[] = { 3, };
797static int mt7623_pcm_sync_2_pins[] = { 36, };
798static int mt7623_pcm_sync_2_funcs[] = { 3, };
799static int mt7623_pcm_sync_3_pins[] = { 52, };
800static int mt7623_pcm_sync_3_funcs[] = { 31, };
801static int mt7623_pcm_sync_4_pins[] = { 73, };
802static int mt7623_pcm_sync_4_funcs[] = { 3, };
803static int mt7623_pcm_sync_5_pins[] = { 192, };
804static int mt7623_pcm_sync_5_funcs[] = { 3, };
805static int mt7623_pcm_sync_6_pins[] = { 197, };
806static int mt7623_pcm_sync_6_funcs[] = { 3, };
807static int mt7623_pcm_rx_0_pins[] = { 20, };
808static int mt7623_pcm_rx_0_funcs[] = { 1, };
809static int mt7623_pcm_rx_1_pins[] = { 16, };
810static int mt7623_pcm_rx_1_funcs[] = { 3, };
811static int mt7623_pcm_rx_2_pins[] = { 34, };
812static int mt7623_pcm_rx_2_funcs[] = { 3, };
813static int mt7623_pcm_rx_3_pins[] = { 51, };
814static int mt7623_pcm_rx_3_funcs[] = { 3, };
815static int mt7623_pcm_rx_4_pins[] = { 72, };
816static int mt7623_pcm_rx_4_funcs[] = { 3, };
817static int mt7623_pcm_rx_5_pins[] = { 190, };
818static int mt7623_pcm_rx_5_funcs[] = { 3, };
819static int mt7623_pcm_rx_6_pins[] = { 195, };
820static int mt7623_pcm_rx_6_funcs[] = { 3, };
821static int mt7623_pcm_tx_0_pins[] = { 21, };
822static int mt7623_pcm_tx_0_funcs[] = { 1, };
823static int mt7623_pcm_tx_1_pins[] = { 32, };
824static int mt7623_pcm_tx_1_funcs[] = { 3, };
825static int mt7623_pcm_tx_2_pins[] = { 33, };
826static int mt7623_pcm_tx_2_funcs[] = { 3, };
827static int mt7623_pcm_tx_3_pins[] = { 38, };
828static int mt7623_pcm_tx_3_funcs[] = { 3, };
829static int mt7623_pcm_tx_4_pins[] = { 49, };
830static int mt7623_pcm_tx_4_funcs[] = { 3, };
831static int mt7623_pcm_tx_5_pins[] = { 189, };
832static int mt7623_pcm_tx_5_funcs[] = { 3, };
833static int mt7623_pcm_tx_6_pins[] = { 194, };
834static int mt7623_pcm_tx_6_funcs[] = { 3, };
835
836/* PWM */
837static int mt7623_pwm_ch1_0_pins[] = { 203, };
838static int mt7623_pwm_ch1_0_funcs[] = { 1, };
839static int mt7623_pwm_ch1_1_pins[] = { 208, };
840static int mt7623_pwm_ch1_1_funcs[] = { 2, };
841static int mt7623_pwm_ch1_2_pins[] = { 72, };
842static int mt7623_pwm_ch1_2_funcs[] = { 4, };
843static int mt7623_pwm_ch1_3_pins[] = { 88, };
844static int mt7623_pwm_ch1_3_funcs[] = { 3, };
845static int mt7623_pwm_ch1_4_pins[] = { 108, };
846static int mt7623_pwm_ch1_4_funcs[] = { 3, };
847static int mt7623_pwm_ch2_0_pins[] = { 204, };
848static int mt7623_pwm_ch2_0_funcs[] = { 1, };
849static int mt7623_pwm_ch2_1_pins[] = { 53, };
850static int mt7623_pwm_ch2_1_funcs[] = { 5, };
851static int mt7623_pwm_ch2_2_pins[] = { 88, };
852static int mt7623_pwm_ch2_2_funcs[] = { 6, };
853static int mt7623_pwm_ch2_3_pins[] = { 108, };
854static int mt7623_pwm_ch2_3_funcs[] = { 6, };
855static int mt7623_pwm_ch2_4_pins[] = { 209, };
856static int mt7623_pwm_ch2_4_funcs[] = { 5, };
857static int mt7623_pwm_ch3_0_pins[] = { 205, };
858static int mt7623_pwm_ch3_0_funcs[] = { 1, };
859static int mt7623_pwm_ch3_1_pins[] = { 55, };
860static int mt7623_pwm_ch3_1_funcs[] = { 5, };
861static int mt7623_pwm_ch3_2_pins[] = { 89, };
862static int mt7623_pwm_ch3_2_funcs[] = { 6, };
863static int mt7623_pwm_ch3_3_pins[] = { 109, };
864static int mt7623_pwm_ch3_3_funcs[] = { 6, };
865static int mt7623_pwm_ch4_0_pins[] = { 206, };
866static int mt7623_pwm_ch4_0_funcs[] = { 1, };
867static int mt7623_pwm_ch4_1_pins[] = { 90, };
868static int mt7623_pwm_ch4_1_funcs[] = { 6, };
869static int mt7623_pwm_ch4_2_pins[] = { 110, };
870static int mt7623_pwm_ch4_2_funcs[] = { 6, };
871static int mt7623_pwm_ch4_3_pins[] = { 124, };
872static int mt7623_pwm_ch4_3_funcs[] = { 5, };
873static int mt7623_pwm_ch5_0_pins[] = { 207, };
874static int mt7623_pwm_ch5_0_funcs[] = { 1, };
875static int mt7623_pwm_ch5_1_pins[] = { 125, };
876static int mt7623_pwm_ch5_1_funcs[] = { 5, };
877
878/* PWRAP */
879static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
880static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
881
882/* SPDIF */
883static int mt7623_spdif_in0_0_pins[] = { 56, };
884static int mt7623_spdif_in0_0_funcs[] = { 3, };
885static int mt7623_spdif_in0_1_pins[] = { 201, };
886static int mt7623_spdif_in0_1_funcs[] = { 1, };
887static int mt7623_spdif_in1_0_pins[] = { 54, };
888static int mt7623_spdif_in1_0_funcs[] = { 3, };
889static int mt7623_spdif_in1_1_pins[] = { 202, };
890static int mt7623_spdif_in1_1_funcs[] = { 1, };
891static int mt7623_spdif_out_pins[] = { 202, };
892static int mt7623_spdif_out_funcs[] = { 1, };
893
894/* SPI */
895static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
896static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
897static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
898static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
899static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
900static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
901
902/* UART */
903static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
904static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
905static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
906static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
907static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
908static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
909static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
910static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
911static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
912static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
913static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
914static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
915static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
916static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
917static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
918static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
919static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
920static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
921static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
922static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
923static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
924static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
925static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
926static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
927static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
928static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
929static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
930static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
931
932/* Watchdog */
933static int mt7623_watchdog_0_pins[] = { 11, };
934static int mt7623_watchdog_0_funcs[] = { 1, };
935static int mt7623_watchdog_1_pins[] = { 121, };
936static int mt7623_watchdog_1_funcs[] = { 5, };
937
938static const struct mtk_group_desc mt7623_groups[] = {
939 PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
940 PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1),
941 PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te),
942 PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0),
943 PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1),
944 PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2),
945 PINCTRL_PIN_GROUP("ephy", mt7623_ephy),
946 PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int),
947 PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst),
948 PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio),
949 PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec),
950 PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg),
951 PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c),
952 PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx),
953 PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c),
954 PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0),
955 PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0),
956 PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1),
957 PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2),
958 PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3),
959 PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4),
960 PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0),
961 PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1),
962 PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2),
963 PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3),
964 PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0),
965 PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1),
966 PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4),
967 PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5),
968 PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk),
969 PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk),
970 PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in),
971 PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in),
972 PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0),
973 PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1),
974 PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0),
975 PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1),
976 PINCTRL_PIN_GROUP("ir", mt7623_ir),
977 PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst),
978 PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio),
979 PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx),
980 PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0),
981 PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1),
982 PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins),
983 PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0),
984 PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1),
985 PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2),
986 PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2),
987 PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3),
988 PINCTRL_PIN_GROUP("nandc", mt7623_nandc),
989 PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0),
990 PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1),
991 PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0),
992 PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1),
993 PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2),
994 PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0),
995 PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1),
996 PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2),
997 PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0),
998 PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1),
999 PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2),
1000 PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0),
1001 PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1),
1002 PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2),
1003 PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst),
1004 PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst),
1005 PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst),
1006 PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
1007 PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
1008 PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst),
1009 PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst),
1010 PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst),
1011 PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst),
1012 PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst),
1013 PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst),
1014 PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst),
1015 PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst),
1016 PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake),
1017 PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake),
1018 PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake),
1019 PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake),
1020 PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake),
1021 PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake),
1022 PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq),
1023 PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq),
1024 PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq),
1025 PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0),
1026 PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1),
1027 PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2),
1028 PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3),
1029 PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4),
1030 PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5),
1031 PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6),
1032 PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0),
1033 PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1),
1034 PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2),
1035 PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3),
1036 PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4),
1037 PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5),
1038 PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6),
1039 PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0),
1040 PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1),
1041 PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2),
1042 PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3),
1043 PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4),
1044 PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5),
1045 PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6),
1046 PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0),
1047 PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1),
1048 PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2),
1049 PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3),
1050 PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4),
1051 PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5),
1052 PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6),
1053 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0),
1054 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1),
1055 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2),
1056 PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3),
1057 PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4),
1058 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0),
1059 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1),
1060 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2),
1061 PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3),
1062 PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4),
1063 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0),
1064 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1),
1065 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2),
1066 PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3),
1067 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0),
1068 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1),
1069 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2),
1070 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3),
1071 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0),
1072 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1),
1073 PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap),
1074 PINCTRL_PIN_GROUP("rtc", mt7623_rtc),
1075 PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0),
1076 PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1),
1077 PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0),
1078 PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1),
1079 PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out),
1080 PINCTRL_PIN_GROUP("spi0", mt7623_spi0),
1081 PINCTRL_PIN_GROUP("spi1", mt7623_spi1),
1082 PINCTRL_PIN_GROUP("spi2", mt7623_spi2),
1083 PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd),
1084 PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd),
1085 PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd),
1086 PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd),
1087 PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd),
1088 PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd),
1089 PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd),
1090 PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd),
1091 PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd),
1092 PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd),
1093 PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts),
1094 PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts),
1095 PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts),
1096 PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts),
1097 PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0),
1098 PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1),
1099};
1100
1101/* Joint those groups owning the same capability in user point of view which
1102 * allows that people tend to use through the device tree.
1103 */
1104
1105static const char *const mt7623_aud_clk_groups[] = { "aud_ext_clk0",
1106 "aud_ext_clk1", };
1107static const char *const mt7623_disp_pwm_groups[] = { "disp_pwm_0",
1108 "disp_pwm_1",
1109 "disp_pwm_2", };
1110static const char *const mt7623_ethernet_groups[] = { "esw_int", "esw_rst",
1111 "ephy", "mdc_mdio", };
1112static const char *const mt7623_ext_sdio_groups[] = { "ext_sdio", };
1113static const char *const mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg",
1114 "hdmi_i2c", "hdmi_rx",
1115 "hdmi_rx_i2c", };
1116static const char *const mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
1117 "i2c1_2", "i2c1_3", "i2c1_4",
1118 "i2c2_0", "i2c2_1", "i2c2_2",
1119 "i2c2_3", };
1120static const char *const mt7623_i2s_groups[] = { "i2s0", "i2s1",
1121 "i2s2_bclk_lrclk_mclk",
1122 "i2s3_bclk_lrclk_mclk",
1123 "i2s4", "i2s5",
1124 "i2s2_data_in", "i2s3_data_in",
1125 "i2s2_data_0", "i2s2_data_1",
1126 "i2s3_data_0", "i2s3_data_1",};
1127static const char *const mt7623_ir_groups[] = { "ir", };
1128static const char *const mt7623_lcd_groups[] = { "dsi_te", "lcm_rst",
1129 "mipi_tx", };
1130static const char *const mt7623_msdc_groups[] = { "msdc0", "msdc1",
1131 "msdc1_ins", "msdc1_wp_0",
1132 "msdc1_wp_1", "msdc1_wp_2",
1133 "msdc2", "msdc3", };
1134static const char *const mt7623_nandc_groups[] = { "nandc", "nandc_ceb0",
1135 "nandc_ceb1", };
1136static const char *const mt7623_otg_groups[] = { "otg_iddig0_0",
1137 "otg_iddig0_1",
1138 "otg_iddig0_2",
1139 "otg_iddig1_0",
1140 "otg_iddig1_1",
1141 "otg_iddig1_2",
1142 "otg_drv_vbus0_0",
1143 "otg_drv_vbus0_1",
1144 "otg_drv_vbus0_2",
1145 "otg_drv_vbus1_0",
1146 "otg_drv_vbus1_1",
1147 "otg_drv_vbus1_2", };
1148static const char *const mt7623_pcie_groups[] = { "pcie0_0_perst",
1149 "pcie0_1_perst",
1150 "pcie1_0_perst",
1151 "pcie1_1_perst",
1152 "pcie2_0_perst",
1153 "pcie2_1_perst",
1154 "pcie0_0_rev_perst",
1155 "pcie0_1_rev_perst",
1156 "pcie1_0_rev_perst",
1157 "pcie1_1_rev_perst",
1158 "pcie2_0_rev_perst",
1159 "pcie2_1_rev_perst",
1160 "pcie0_0_wake", "pcie0_1_wake",
1161 "pcie2_0_wake", "pcie2_1_wake",
1162 "pcie0_clkreq", "pcie1_clkreq",
1163 "pcie2_clkreq", };
1164static const char *const mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1",
1165 "pcm_clk_2", "pcm_clk_3",
1166 "pcm_clk_4", "pcm_clk_5",
1167 "pcm_clk_6", "pcm_sync_0",
1168 "pcm_sync_1", "pcm_sync_2",
1169 "pcm_sync_3", "pcm_sync_4",
1170 "pcm_sync_5", "pcm_sync_6",
1171 "pcm_rx_0", "pcm_rx_1",
1172 "pcm_rx_2", "pcm_rx_3",
1173 "pcm_rx_4", "pcm_rx_5",
1174 "pcm_rx_6", "pcm_tx_0",
1175 "pcm_tx_1", "pcm_tx_2",
1176 "pcm_tx_3", "pcm_tx_4",
1177 "pcm_tx_5", "pcm_tx_6", };
1178static const char *const mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
1179 "pwm_ch1_2", "pwm_ch2_0",
1180 "pwm_ch2_1", "pwm_ch2_2",
1181 "pwm_ch3_0", "pwm_ch3_1",
1182 "pwm_ch3_2", "pwm_ch4_0",
1183 "pwm_ch4_1", "pwm_ch4_2",
1184 "pwm_ch4_3", "pwm_ch5_0",
1185 "pwm_ch5_1", "pwm_ch5_2",
1186 "pwm_ch6_0", "pwm_ch6_1",
1187 "pwm_ch6_2", "pwm_ch6_3",
1188 "pwm_ch7_0", "pwm_ch7_1",
1189 "pwm_ch7_2", };
1190static const char *const mt7623_pwrap_groups[] = { "pwrap", };
1191static const char *const mt7623_rtc_groups[] = { "rtc", };
1192static const char *const mt7623_spi_groups[] = { "spi0", "spi2", "spi2", };
1193static const char *const mt7623_spdif_groups[] = { "spdif_in0_0",
1194 "spdif_in0_1", "spdif_in1_0",
1195 "spdif_in1_1", "spdif_out", };
1196static const char *const mt7623_uart_groups[] = { "uart0_0_txd_rxd",
1197 "uart0_1_txd_rxd",
1198 "uart0_2_txd_rxd",
1199 "uart0_3_txd_rxd",
1200 "uart1_0_txd_rxd",
1201 "uart1_1_txd_rxd",
1202 "uart1_2_txd_rxd",
1203 "uart2_0_txd_rxd",
1204 "uart2_1_txd_rxd",
1205 "uart3_txd_rxd",
1206 "uart0_rts_cts",
1207 "uart1_rts_cts",
1208 "uart2_rts_cts",
1209 "uart3_rts_cts", };
1210static const char *const mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
1211
1212static const struct mtk_function_desc mt7623_functions[] = {
1213 {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
1214 {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
1215 {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
1216 {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
1217 {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
1218 {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
1219 {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
1220 {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
1221 {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
1222 {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
1223 {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
1224 {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
1225 {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
1226 {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
1227 {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
1228 {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
1229 {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
1230 {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
1231 {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
1232 {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
1233 {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
1234};
1235
1236static struct mtk_pinctrl_soc mt7623_data = {
1237 .name = "mt7623_pinctrl",
1238 .reg_cal = mt7623_reg_cals,
1239 .pins = mt7623_pins,
1240 .npins = ARRAY_SIZE(mt7623_pins),
1241 .grps = mt7623_groups,
1242 .ngrps = ARRAY_SIZE(mt7623_groups),
1243 .funcs = mt7623_functions,
1244 .nfuncs = ARRAY_SIZE(mt7623_functions),
1245};
1246
1247/*
1248 * There are some specific pins have mux functions greater than 8,
1249 * and if we want to switch thees high modes we need to disable
1250 * bonding constraints firstly.
1251 */
1252static void mt7623_bonding_disable(struct udevice *dev)
1253{
1254 mtk_rmw(dev, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
1255 mtk_rmw(dev, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
1256 mtk_rmw(dev, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
1257}
1258
1259static int mtk_pinctrl_mt7623_probe(struct udevice *dev)
1260{
1261 int err;
1262
1263 err = mtk_pinctrl_common_probe(dev, &mt7623_data);
1264 if (err)
1265 return err;
1266
1267 mt7623_bonding_disable(dev);
1268
1269 return 0;
1270}
1271
1272static const struct udevice_id mt7623_pctrl_match[] = {
1273 { .compatible = "mediatek,mt7623-pinctrl", },
1274 { /* sentinel */ }
1275};
1276
1277U_BOOT_DRIVER(mt7623_pinctrl) = {
1278 .name = "mt7623_pinctrl",
1279 .id = UCLASS_PINCTRL,
1280 .of_match = mt7623_pctrl_match,
1281 .ops = &mtk_pinctrl_ops,
1282 .probe = mtk_pinctrl_mt7623_probe,
1283 .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
1284};