Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 1 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 2 | menuconfig MTD_RAW_NAND |
Miquel Raynal | 8115c45 | 2018-08-16 17:30:08 +0200 | [diff] [blame] | 3 | bool "Raw NAND Device Support" |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 4 | if MTD_RAW_NAND |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 5 | |
| 6 | config SYS_NAND_SELF_INIT |
| 7 | bool |
| 8 | help |
| 9 | This option, if enabled, provides more flexible and linux-like |
| 10 | NAND initialization process. |
| 11 | |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 12 | config SPL_SYS_NAND_SELF_INIT |
| 13 | bool |
| 14 | depends on !SPL_NAND_SIMPLE |
| 15 | help |
| 16 | This option, if enabled, provides more flexible and linux-like |
| 17 | NAND initialization process, in SPL. |
| 18 | |
| 19 | config TPL_SYS_NAND_SELF_INIT |
| 20 | bool |
| 21 | depends on TPL_NAND_SUPPORT |
| 22 | help |
| 23 | This option, if enabled, provides more flexible and linux-like |
| 24 | NAND initialization process, in SPL. |
| 25 | |
Tom Rini | 1a9f23d | 2022-05-26 14:31:57 -0400 | [diff] [blame] | 26 | config TPL_NAND_INIT |
| 27 | bool |
| 28 | |
Stefan Agner | bd18614 | 2018-12-06 14:57:09 +0100 | [diff] [blame] | 29 | config SYS_NAND_DRIVER_ECC_LAYOUT |
Tom Rini | d03e14e | 2021-12-11 14:55:54 -0500 | [diff] [blame] | 30 | bool "Omit standard ECC layouts to save space" |
Stefan Agner | bd18614 | 2018-12-06 14:57:09 +0100 | [diff] [blame] | 31 | help |
Tom Rini | d03e14e | 2021-12-11 14:55:54 -0500 | [diff] [blame] | 32 | Omit standard ECC layouts to save space. Select this if your driver |
Stefan Agner | bd18614 | 2018-12-06 14:57:09 +0100 | [diff] [blame] | 33 | is known to provide its own ECC layout. |
| 34 | |
Stefan Roese | 23b37f9 | 2019-08-22 12:28:04 +0200 | [diff] [blame] | 35 | config SYS_NAND_USE_FLASH_BBT |
| 36 | bool "Enable BBT (Bad Block Table) support" |
| 37 | help |
| 38 | Enable the BBT (Bad Block Table) usage. |
| 39 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 40 | config NAND_ATMEL |
| 41 | bool "Support Atmel NAND controller" |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 42 | select SYS_NAND_SELF_INIT |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 43 | imply SYS_NAND_USE_FLASH_BBT |
| 44 | help |
| 45 | Enable this driver for NAND flash platforms using an Atmel NAND |
| 46 | controller. |
| 47 | |
Derald D. Woods | 7830fc5 | 2018-12-15 01:36:46 -0600 | [diff] [blame] | 48 | if NAND_ATMEL |
| 49 | |
| 50 | config ATMEL_NAND_HWECC |
| 51 | bool "Atmel Hardware ECC" |
Derald D. Woods | 7830fc5 | 2018-12-15 01:36:46 -0600 | [diff] [blame] | 52 | |
| 53 | config ATMEL_NAND_HW_PMECC |
| 54 | bool "Atmel Programmable Multibit ECC (PMECC)" |
| 55 | select ATMEL_NAND_HWECC |
Derald D. Woods | 7830fc5 | 2018-12-15 01:36:46 -0600 | [diff] [blame] | 56 | help |
| 57 | The Programmable Multibit ECC (PMECC) controller is a programmable |
| 58 | binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. |
| 59 | |
| 60 | config PMECC_CAP |
| 61 | int "PMECC Correctable ECC Bits" |
| 62 | depends on ATMEL_NAND_HW_PMECC |
| 63 | default 2 |
| 64 | help |
| 65 | Correctable ECC bits, can be 2, 4, 8, 12, and 24. |
| 66 | |
| 67 | config PMECC_SECTOR_SIZE |
| 68 | int "PMECC Sector Size" |
| 69 | depends on ATMEL_NAND_HW_PMECC |
| 70 | default 512 |
| 71 | help |
| 72 | Sector size, in bytes, can be 512 or 1024. |
| 73 | |
| 74 | config SPL_GENERATE_ATMEL_PMECC_HEADER |
| 75 | bool "Atmel PMECC Header Generation" |
Tom Rini | 0a83cc2 | 2022-06-10 23:03:09 -0400 | [diff] [blame] | 76 | depends on SPL |
Derald D. Woods | 7830fc5 | 2018-12-15 01:36:46 -0600 | [diff] [blame] | 77 | select ATMEL_NAND_HWECC |
| 78 | select ATMEL_NAND_HW_PMECC |
Derald D. Woods | 7830fc5 | 2018-12-15 01:36:46 -0600 | [diff] [blame] | 79 | help |
| 80 | Generate Programmable Multibit ECC (PMECC) header for SPL image. |
| 81 | |
| 82 | endif |
| 83 | |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 84 | config NAND_BRCMNAND |
| 85 | bool "Support Broadcom NAND controller" |
Miquel Raynal | a903be4 | 2019-10-03 19:50:04 +0200 | [diff] [blame] | 86 | depends on OF_CONTROL && DM && DM_MTD |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 87 | select SYS_NAND_SELF_INIT |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 88 | help |
| 89 | Enable the driver for NAND flash on platforms using a Broadcom NAND |
| 90 | controller. |
| 91 | |
Álvaro Fernández Rojas | d9f9bfc | 2019-08-28 19:12:15 +0200 | [diff] [blame] | 92 | config NAND_BRCMNAND_6368 |
| 93 | bool "Support Broadcom NAND controller on bcm6368" |
| 94 | depends on NAND_BRCMNAND && ARCH_BMIPS |
| 95 | help |
| 96 | Enable support for broadcom nand driver on bcm6368. |
| 97 | |
Philippe Reynes | e175c32 | 2022-02-11 19:18:36 +0100 | [diff] [blame] | 98 | config NAND_BRCMNAND_6753 |
| 99 | bool "Support Broadcom NAND controller on bcm6753" |
William Zhang | 3892182 | 2022-08-22 11:49:08 -0700 | [diff] [blame] | 100 | depends on NAND_BRCMNAND && BCM6855 |
Philippe Reynes | e175c32 | 2022-02-11 19:18:36 +0100 | [diff] [blame] | 101 | help |
| 102 | Enable support for broadcom nand driver on bcm6753. |
| 103 | |
Philippe Reynes | 74ead74 | 2020-01-07 20:14:13 +0100 | [diff] [blame] | 104 | config NAND_BRCMNAND_68360 |
| 105 | bool "Support Broadcom NAND controller on bcm68360" |
William Zhang | df0b5bb | 2022-08-22 11:31:43 -0700 | [diff] [blame] | 106 | depends on NAND_BRCMNAND && BCM6856 |
Philippe Reynes | 74ead74 | 2020-01-07 20:14:13 +0100 | [diff] [blame] | 107 | help |
| 108 | Enable support for broadcom nand driver on bcm68360. |
| 109 | |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 110 | config NAND_BRCMNAND_6838 |
| 111 | bool "Support Broadcom NAND controller on bcm6838" |
| 112 | depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 |
| 113 | help |
| 114 | Enable support for broadcom nand driver on bcm6838. |
| 115 | |
| 116 | config NAND_BRCMNAND_6858 |
| 117 | bool "Support Broadcom NAND controller on bcm6858" |
William Zhang | 6b45fa6 | 2022-08-22 11:39:45 -0700 | [diff] [blame] | 118 | depends on NAND_BRCMNAND && BCM6858 |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 119 | help |
| 120 | Enable support for broadcom nand driver on bcm6858. |
| 121 | |
| 122 | config NAND_BRCMNAND_63158 |
| 123 | bool "Support Broadcom NAND controller on bcm63158" |
William Zhang | 35a3ec1b | 2022-08-22 11:19:46 -0700 | [diff] [blame] | 124 | depends on NAND_BRCMNAND && BCM63158 |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 125 | help |
| 126 | Enable support for broadcom nand driver on bcm63158. |
| 127 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 128 | config NAND_DAVINCI |
| 129 | bool "Support TI Davinci NAND controller" |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 130 | select SYS_NAND_SELF_INIT if TARGET_DA850EVM |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 131 | help |
| 132 | Enable this driver for NAND flash controllers available in TI Davinci |
| 133 | and Keystone2 platforms |
| 134 | |
Tom Rini | dada0e3 | 2021-09-12 20:32:24 -0400 | [diff] [blame] | 135 | config KEYSTONE_RBL_NAND |
| 136 | depends on ARCH_KEYSTONE |
| 137 | def_bool y |
| 138 | |
Tom Rini | fae1dab | 2021-09-22 14:50:29 -0400 | [diff] [blame] | 139 | config SPL_NAND_LOAD |
| 140 | def_bool y |
| 141 | depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT |
| 142 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 143 | config NAND_DENALI |
| 144 | bool |
| 145 | select SYS_NAND_SELF_INIT |
| 146 | imply CMD_NAND |
| 147 | |
| 148 | config NAND_DENALI_DT |
| 149 | bool "Support Denali NAND controller as a DT device" |
| 150 | select NAND_DENALI |
Masahiro Yamada | 8fc5382 | 2020-01-30 22:07:59 +0900 | [diff] [blame] | 151 | depends on OF_CONTROL && DM_MTD |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 152 | help |
| 153 | Enable the driver for NAND flash on platforms using a Denali NAND |
| 154 | controller as a DT device. |
| 155 | |
Tom Rini | a73788c | 2021-09-22 14:50:37 -0400 | [diff] [blame] | 156 | config NAND_FSL_ELBC |
| 157 | bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver" |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 158 | select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT |
| 159 | select SPL_SYS_NAND_SELF_INIT |
| 160 | select SYS_NAND_SELF_INIT |
Tom Rini | a73788c | 2021-09-22 14:50:37 -0400 | [diff] [blame] | 161 | depends on FSL_ELBC |
| 162 | help |
| 163 | Enable the Freescale Enhanced Local Bus Controller FCM NAND driver. |
| 164 | |
Pali Rohár | bb834db | 2022-04-04 18:17:19 +0200 | [diff] [blame] | 165 | config NAND_FSL_ELBC_DT |
| 166 | bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)" |
| 167 | depends on NAND_FSL_ELBC |
| 168 | |
Tom Rini | a73788c | 2021-09-22 14:50:37 -0400 | [diff] [blame] | 169 | config NAND_FSL_IFC |
| 170 | bool "Support Freescale Integrated Flash Controller NAND driver" |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 171 | select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT |
Tom Rini | 1a9f23d | 2022-05-26 14:31:57 -0400 | [diff] [blame] | 172 | select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 173 | select SPL_SYS_NAND_SELF_INIT |
| 174 | select SYS_NAND_SELF_INIT |
Tom Rini | 05b419e | 2021-12-11 14:55:49 -0500 | [diff] [blame] | 175 | select FSL_IFC |
Tom Rini | a73788c | 2021-09-22 14:50:37 -0400 | [diff] [blame] | 176 | help |
| 177 | Enable the Freescale Integrated Flash Controller NAND driver. |
| 178 | |
Tom Rini | 0820427 | 2021-09-22 14:50:28 -0400 | [diff] [blame] | 179 | config NAND_LPC32XX_MLC |
| 180 | bool "Support LPC32XX_MLC controller" |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 181 | select SYS_NAND_SELF_INIT |
Tom Rini | 0820427 | 2021-09-22 14:50:28 -0400 | [diff] [blame] | 182 | help |
| 183 | Enable the LPC32XX MLC NAND controller. |
| 184 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 185 | config NAND_LPC32XX_SLC |
| 186 | bool "Support LPC32XX_SLC controller" |
| 187 | help |
| 188 | Enable the LPC32XX SLC NAND controller. |
| 189 | |
| 190 | config NAND_OMAP_GPMC |
| 191 | bool "Support OMAP GPMC NAND controller" |
| 192 | depends on ARCH_OMAP2PLUS |
| 193 | help |
| 194 | Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. |
| 195 | GPMC controller is used for parallel NAND flash devices, and can |
| 196 | do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 |
| 197 | and BCH16 ECC algorithms. |
| 198 | |
Tom Rini | f6d26d8 | 2021-09-22 14:50:39 -0400 | [diff] [blame] | 199 | if NAND_OMAP_GPMC |
| 200 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 201 | config NAND_OMAP_GPMC_PREFETCH |
| 202 | bool "Enable GPMC Prefetch" |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 203 | default y |
| 204 | help |
| 205 | On OMAP platforms that use the GPMC controller |
| 206 | (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that |
| 207 | uses the prefetch mode to speed up read operations. |
| 208 | |
| 209 | config NAND_OMAP_ELM |
| 210 | bool "Enable ELM driver for OMAPxx and AMxx platforms." |
Tom Rini | f6d26d8 | 2021-09-22 14:50:39 -0400 | [diff] [blame] | 211 | depends on !OMAP34XX |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 212 | help |
| 213 | ELM controller is used for ECC error detection (not ECC calculation) |
| 214 | of BCH4, BCH8 and BCH16 ECC algorithms. |
| 215 | Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, |
| 216 | thus such SoC platforms need to depend on software library for ECC error |
| 217 | detection. However ECC calculation on such plaforms would still be |
| 218 | done by GPMC controller. |
| 219 | |
Tom Rini | f6d26d8 | 2021-09-22 14:50:39 -0400 | [diff] [blame] | 220 | choice |
| 221 | prompt "ECC scheme" |
| 222 | default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW |
| 223 | help |
| 224 | On OMAP platforms, this CONFIG specifies NAND ECC scheme. |
| 225 | It can take following values: |
| 226 | OMAP_ECC_HAM1_CODE_SW |
| 227 | 1-bit Hamming code using software lib. |
| 228 | (for legacy devices only) |
| 229 | OMAP_ECC_HAM1_CODE_HW |
| 230 | 1-bit Hamming code using GPMC hardware. |
| 231 | (for legacy devices only) |
| 232 | OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |
| 233 | 4-bit BCH code (unsupported) |
| 234 | OMAP_ECC_BCH4_CODE_HW |
| 235 | 4-bit BCH code (unsupported) |
| 236 | OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |
| 237 | 8-bit BCH code with |
| 238 | - ecc calculation using GPMC hardware engine, |
| 239 | - error detection using software library. |
| 240 | - requires CONFIG_BCH to enable software BCH library |
| 241 | (For legacy device which do not have ELM h/w engine) |
| 242 | OMAP_ECC_BCH8_CODE_HW |
| 243 | 8-bit BCH code with |
| 244 | - ecc calculation using GPMC hardware engine, |
| 245 | - error detection using ELM hardware engine. |
| 246 | OMAP_ECC_BCH16_CODE_HW |
| 247 | 16-bit BCH code with |
| 248 | - ecc calculation using GPMC hardware engine, |
| 249 | - error detection using ELM hardware engine. |
| 250 | |
| 251 | How to select ECC scheme on OMAP and AMxx platforms ? |
| 252 | ----------------------------------------------------- |
| 253 | Though higher ECC schemes have more capability to detect and correct |
| 254 | bit-flips, but still selection of ECC scheme is dependent on following |
| 255 | - hardware engines present in SoC. |
| 256 | Some legacy OMAP SoC do not have ELM h/w engine thus such |
| 257 | SoC cannot support BCHx_HW ECC schemes. |
| 258 | - size of OOB/Spare region |
| 259 | With higher ECC schemes, more OOB/Spare area is required to |
| 260 | store ECC. So choice of ECC scheme is limited by NAND oobsize. |
| 261 | |
| 262 | In general following expression can help: |
| 263 | NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES |
| 264 | where |
| 265 | NAND_OOBSIZE = number of bytes available in |
| 266 | OOB/spare area per NAND page. |
| 267 | NAND_PAGESIZE = bytes in main-area of NAND page. |
| 268 | ECC_BYTES = number of ECC bytes generated to |
| 269 | protect 512 bytes of data, which is: |
| 270 | 3 for HAM1_xx ecc schemes |
| 271 | 7 for BCH4_xx ecc schemes |
| 272 | 14 for BCH8_xx ecc schemes |
| 273 | 26 for BCH16_xx ecc schemes |
| 274 | |
| 275 | example to check for BCH16 on 2K page NAND |
| 276 | NAND_PAGESIZE = 2048 |
| 277 | NAND_OOBSIZE = 64 |
| 278 | 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE |
| 279 | Thus BCH16 cannot be supported on 2K page NAND. |
| 280 | |
| 281 | However, for 4K pagesize NAND |
| 282 | NAND_PAGESIZE = 4096 |
| 283 | NAND_OOBSIZE = 224 |
| 284 | ECC_BYTES = 26 |
| 285 | 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE |
| 286 | Thus BCH16 can be supported on 4K page NAND. |
| 287 | |
| 288 | config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW |
| 289 | bool "1-bit Hamming code using software lib" |
| 290 | |
| 291 | config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW |
| 292 | bool "1-bit Hamming code using GPMC hardware" |
| 293 | |
| 294 | config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW |
| 295 | bool "8-bit BCH code with HW calculation SW error detection" |
| 296 | |
| 297 | config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW |
| 298 | bool "8-bit BCH code with HW calculation and error detection" |
| 299 | |
| 300 | config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW |
| 301 | bool "16-bit BCH code with HW calculation and error detection" |
| 302 | |
| 303 | endchoice |
| 304 | |
| 305 | config NAND_OMAP_ECCSCHEME |
| 306 | int |
| 307 | default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW |
| 308 | default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW |
| 309 | default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW |
| 310 | default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW |
| 311 | default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW |
| 312 | help |
| 313 | This must be kept in sync with the enum in |
| 314 | include/linux/mtd/omap_gpmc.h |
| 315 | |
| 316 | endif |
| 317 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 318 | config NAND_VF610_NFC |
| 319 | bool "Support for Freescale NFC for VF610" |
| 320 | select SYS_NAND_SELF_INIT |
Stefan Agner | bd18614 | 2018-12-06 14:57:09 +0100 | [diff] [blame] | 321 | select SYS_NAND_DRIVER_ECC_LAYOUT |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 322 | imply CMD_NAND |
| 323 | help |
| 324 | Enables support for NAND Flash Controller on some Freescale |
| 325 | processors like the VF610, MCF54418 or Kinetis K70. |
| 326 | The driver supports a maximum 2k page size. The driver |
| 327 | currently does not support hardware ECC. |
| 328 | |
Lukasz Majewski | f006cb3 | 2018-12-03 10:24:50 +0100 | [diff] [blame] | 329 | if NAND_VF610_NFC |
| 330 | |
| 331 | config NAND_VF610_NFC_DT |
| 332 | bool "Support Vybrid's vf610 NAND controller as a DT device" |
Miquel Raynal | a903be4 | 2019-10-03 19:50:04 +0200 | [diff] [blame] | 333 | depends on OF_CONTROL && DM_MTD |
Lukasz Majewski | f006cb3 | 2018-12-03 10:24:50 +0100 | [diff] [blame] | 334 | help |
| 335 | Enable the driver for Vybrid's vf610 NAND flash on platforms |
| 336 | using device tree. |
| 337 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 338 | choice |
| 339 | prompt "Hardware ECC strength" |
| 340 | depends on NAND_VF610_NFC |
| 341 | default SYS_NAND_VF610_NFC_45_ECC_BYTES |
| 342 | help |
| 343 | Select the ECC strength used in the hardware BCH ECC block. |
| 344 | |
| 345 | config SYS_NAND_VF610_NFC_45_ECC_BYTES |
| 346 | bool "24-error correction (45 ECC bytes)" |
| 347 | |
| 348 | config SYS_NAND_VF610_NFC_60_ECC_BYTES |
| 349 | bool "32-error correction (60 ECC bytes)" |
| 350 | |
| 351 | endchoice |
| 352 | |
Lukasz Majewski | f006cb3 | 2018-12-03 10:24:50 +0100 | [diff] [blame] | 353 | endif |
| 354 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 355 | config NAND_PXA3XX |
| 356 | bool "Support for NAND on PXA3xx and Armada 370/XP/38x" |
| 357 | select SYS_NAND_SELF_INIT |
Shmuel Hazan | 759349e | 2020-10-29 08:52:18 +0200 | [diff] [blame] | 358 | select DM_MTD |
Shmuel Hazan | 5898322 | 2020-10-29 08:52:20 +0200 | [diff] [blame] | 359 | select REGMAP |
| 360 | select SYSCON |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 361 | imply CMD_NAND |
| 362 | help |
| 363 | This enables the driver for the NAND flash device found on |
| 364 | PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). |
| 365 | |
| 366 | config NAND_SUNXI |
| 367 | bool "Support for NAND on Allwinner SoCs" |
| 368 | default ARCH_SUNXI |
| 369 | depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I |
| 370 | select SYS_NAND_SELF_INIT |
| 371 | select SYS_NAND_U_BOOT_LOCATIONS |
| 372 | select SPL_NAND_SUPPORT |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 373 | select SPL_SYS_NAND_SELF_INIT |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 374 | imply CMD_NAND |
| 375 | ---help--- |
| 376 | Enable support for NAND. This option enables the standard and |
| 377 | SPL drivers. |
| 378 | The SPL driver only supports reading from the NAND using DMA |
| 379 | transfers. |
| 380 | |
| 381 | if NAND_SUNXI |
| 382 | |
| 383 | config NAND_SUNXI_SPL_ECC_STRENGTH |
| 384 | int "Allwinner NAND SPL ECC Strength" |
| 385 | default 64 |
| 386 | |
| 387 | config NAND_SUNXI_SPL_ECC_SIZE |
| 388 | int "Allwinner NAND SPL ECC Step Size" |
| 389 | default 1024 |
| 390 | |
| 391 | config NAND_SUNXI_SPL_USABLE_PAGE_SIZE |
| 392 | int "Allwinner NAND SPL Usable Page Size" |
| 393 | default 1024 |
| 394 | |
| 395 | endif |
| 396 | |
| 397 | config NAND_ARASAN |
| 398 | bool "Configure Arasan Nand" |
| 399 | select SYS_NAND_SELF_INIT |
Michal Simek | c558783 | 2020-08-19 09:59:52 +0200 | [diff] [blame] | 400 | depends on DM_MTD |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 401 | imply CMD_NAND |
| 402 | help |
| 403 | This enables Nand driver support for Arasan nand flash |
| 404 | controller. This uses the hardware ECC for read and |
| 405 | write operations. |
| 406 | |
| 407 | config NAND_MXC |
| 408 | bool "MXC NAND support" |
| 409 | depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 |
| 410 | imply CMD_NAND |
| 411 | help |
| 412 | This enables the NAND driver for the NAND flash controller on the |
Haolin Li | e8df55b | 2021-07-18 10:13:39 +0800 | [diff] [blame] | 413 | i.MX27 / i.MX31 / i.MX5 processors. |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 414 | |
| 415 | config NAND_MXS |
| 416 | bool "MXS NAND support" |
Peng Fan | 128abf4 | 2020-05-04 22:09:00 +0800 | [diff] [blame] | 417 | depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 418 | select SPL_SYS_NAND_SELF_INIT |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 419 | select SYS_NAND_SELF_INIT |
| 420 | imply CMD_NAND |
| 421 | select APBH_DMA |
Peng Fan | 128abf4 | 2020-05-04 22:09:00 +0800 | [diff] [blame] | 422 | select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M |
| 423 | select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 424 | help |
| 425 | This enables NAND driver for the NAND flash controller on the |
| 426 | MXS processors. |
| 427 | |
| 428 | if NAND_MXS |
| 429 | |
| 430 | config NAND_MXS_DT |
| 431 | bool "Support MXS NAND controller as a DT device" |
Miquel Raynal | a903be4 | 2019-10-03 19:50:04 +0200 | [diff] [blame] | 432 | depends on OF_CONTROL && DM_MTD |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 433 | help |
| 434 | Enable the driver for MXS NAND flash on platforms using |
| 435 | device tree. |
| 436 | |
| 437 | config NAND_MXS_USE_MINIMUM_ECC |
| 438 | bool "Use minimum ECC strength supported by the controller" |
| 439 | default false |
| 440 | |
| 441 | endif |
| 442 | |
Zhengxun Li | 0155171 | 2021-09-14 13:43:51 +0800 | [diff] [blame] | 443 | config NAND_MXIC |
| 444 | bool "Macronix raw NAND controller" |
| 445 | select SYS_NAND_SELF_INIT |
| 446 | help |
| 447 | This selects the Macronix raw NAND controller driver. |
| 448 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 449 | config NAND_ZYNQ |
| 450 | bool "Support for Zynq Nand controller" |
Tom Rini | 9837245 | 2021-12-12 22:12:36 -0500 | [diff] [blame] | 451 | select SPL_SYS_NAND_SELF_INIT |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 452 | select SYS_NAND_SELF_INIT |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 453 | select DM_MTD |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 454 | imply CMD_NAND |
| 455 | help |
| 456 | This enables Nand driver support for Nand flash controller |
| 457 | found on Zynq SoC. |
| 458 | |
| 459 | config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS |
| 460 | bool "Enable use of 1st stage bootloader timing for NAND" |
| 461 | depends on NAND_ZYNQ |
| 462 | help |
| 463 | This flag prevent U-boot reconfigure NAND flash controller and reuse |
| 464 | the NAND timing from 1st stage bootloader. |
| 465 | |
Suneel Garapati | 9de7d2b | 2020-08-26 14:37:22 +0200 | [diff] [blame] | 466 | config NAND_OCTEONTX |
| 467 | bool "Support for OcteonTX NAND controller" |
| 468 | select SYS_NAND_SELF_INIT |
| 469 | imply CMD_NAND |
| 470 | help |
| 471 | This enables Nand flash controller hardware found on the OcteonTX |
| 472 | processors. |
| 473 | |
| 474 | config NAND_OCTEONTX_HW_ECC |
| 475 | bool "Support Hardware ECC for OcteonTX NAND controller" |
| 476 | depends on NAND_OCTEONTX |
| 477 | default y |
| 478 | help |
| 479 | This enables Hardware BCH engine found on the OcteonTX processors to |
| 480 | support ECC for NAND flash controller. |
| 481 | |
Christophe Kerello | da14168 | 2019-04-05 11:41:50 +0200 | [diff] [blame] | 482 | config NAND_STM32_FMC2 |
| 483 | bool "Support for NAND controller on STM32MP SoCs" |
| 484 | depends on ARCH_STM32MP |
| 485 | select SYS_NAND_SELF_INIT |
| 486 | imply CMD_NAND |
| 487 | help |
| 488 | Enables support for NAND Flash chips on SoCs containing the FMC2 |
| 489 | NAND controller. This controller is found on STM32MP SoCs. |
| 490 | The controller supports a maximum 8k page size and supports |
| 491 | a maximum 8-bit correction error per sector of 512 bytes. |
| 492 | |
Kate Liu | 41ccd2e | 2020-12-11 13:46:12 -0800 | [diff] [blame] | 493 | config CORTINA_NAND |
| 494 | bool "Support for NAND controller on Cortina-Access SoCs" |
| 495 | depends on CORTINA_PLATFORM |
| 496 | select SYS_NAND_SELF_INIT |
| 497 | select DM_MTD |
| 498 | imply CMD_NAND |
| 499 | help |
| 500 | Enables support for NAND Flash chips on Coartina-Access SoCs platform |
| 501 | This controller is found on Presidio/Venus SoCs. |
| 502 | The controller supports a maximum 8k page size and supports |
| 503 | a maximum 40-bit error correction per sector of 1024 bytes. |
| 504 | |
Yifeng Zhao | 9e9021e | 2021-06-07 16:40:29 +0800 | [diff] [blame] | 505 | config ROCKCHIP_NAND |
| 506 | bool "Support for NAND controller on Rockchip SoCs" |
| 507 | depends on ARCH_ROCKCHIP |
| 508 | select SYS_NAND_SELF_INIT |
| 509 | select DM_MTD |
| 510 | imply CMD_NAND |
| 511 | help |
| 512 | Enables support for NAND Flash chips on Rockchip SoCs platform. |
| 513 | This controller is found on Rockchip SoCs. |
| 514 | There are four different versions of NAND FLASH Controllers, |
| 515 | including: |
| 516 | NFC v600: RK2928, RK3066, RK3188 |
| 517 | NFC v622: RK3036, RK3128 |
| 518 | NFC v800: RK3308, RV1108 |
| 519 | NFC v900: PX30, RK3326 |
| 520 | |
Tom Rini | 8f37ac4 | 2021-12-12 22:12:35 -0500 | [diff] [blame] | 521 | config TEGRA_NAND |
| 522 | bool "Support for NAND controller on Tegra SoCs" |
| 523 | depends on ARCH_TEGRA |
| 524 | select SYS_NAND_SELF_INIT |
| 525 | imply CMD_NAND |
| 526 | help |
| 527 | Enables support for NAND Flash chips on Tegra SoCs platforms. |
| 528 | |
developer | 10a61df | 2022-05-20 11:23:47 +0800 | [diff] [blame] | 529 | config NAND_MT7621 |
| 530 | bool "Support for MediaTek MT7621 NAND flash controller" |
| 531 | depends on SOC_MT7621 |
| 532 | select SYS_NAND_SELF_INIT |
| 533 | select SPL_SYS_NAND_SELF_INIT |
| 534 | imply CMD_NAND |
| 535 | help |
| 536 | This enables NAND driver for the NAND flash controller on MediaTek |
| 537 | MT7621 platform. |
| 538 | The controller supports 4~12 bits correction per 512 bytes with a |
| 539 | maximum 4KB page size. |
| 540 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 541 | comment "Generic NAND options" |
| 542 | |
| 543 | config SYS_NAND_BLOCK_SIZE |
| 544 | hex "NAND chip eraseblock size" |
Tom Rini | fae1dab | 2021-09-22 14:50:29 -0400 | [diff] [blame] | 545 | depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT |
developer | 10a61df | 2022-05-20 11:23:47 +0800 | [diff] [blame] | 546 | depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \ |
| 547 | !NAND_FSL_IFC && !NAND_MT7621 |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 548 | help |
| 549 | Number of data bytes in one eraseblock for the NAND chip on the |
| 550 | board. This is the multiple of NAND_PAGE_SIZE and the number of |
| 551 | pages. |
| 552 | |
Tom Rini | fdae007 | 2021-09-22 14:50:34 -0400 | [diff] [blame] | 553 | config SYS_NAND_ONFI_DETECTION |
| 554 | bool "Enable detection of ONFI compliant devices during probe" |
| 555 | help |
| 556 | Enables detection of ONFI compliant devices during probe. |
| 557 | And fetching device parameters flashed on device, by parsing |
| 558 | ONFI parameter page. |
| 559 | |
Tom Rini | 2510a81 | 2021-09-22 14:50:30 -0400 | [diff] [blame] | 560 | config SYS_NAND_PAGE_COUNT |
| 561 | hex "NAND chip page count" |
| 562 | depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ |
| 563 | SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE) |
| 564 | help |
| 565 | Number of pages in the NAND chip. |
| 566 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 567 | config SYS_NAND_PAGE_SIZE |
| 568 | hex "NAND chip page size" |
Tom Rini | fae1dab | 2021-09-22 14:50:29 -0400 | [diff] [blame] | 569 | depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ |
| 570 | SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ |
| 571 | (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER |
developer | 10a61df | 2022-05-20 11:23:47 +0800 | [diff] [blame] | 572 | depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621 |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 573 | help |
| 574 | Number of data bytes in one page for the NAND chip on the |
| 575 | board, not including the OOB area. |
| 576 | |
| 577 | config SYS_NAND_OOBSIZE |
| 578 | hex "NAND chip OOB size" |
Tom Rini | fae1dab | 2021-09-22 14:50:29 -0400 | [diff] [blame] | 579 | depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ |
| 580 | SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ |
| 581 | (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER |
Tom Rini | d24700f | 2021-10-30 23:03:56 -0400 | [diff] [blame] | 582 | depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 583 | help |
| 584 | Number of bytes in the Out-Of-Band area for the NAND chip on |
| 585 | the board. |
| 586 | |
| 587 | # Enhance depends when converting drivers to Kconfig which use this config |
| 588 | # option (mxc_nand, ndfc, omap_gpmc). |
| 589 | config SYS_NAND_BUSWIDTH_16BIT |
| 590 | bool "Use 16-bit NAND interface" |
| 591 | depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI |
| 592 | help |
| 593 | Indicates that NAND device has 16-bit wide data-bus. In absence of this |
| 594 | config, bus-width of NAND device is assumed to be either 8-bit and later |
| 595 | determined by reading ONFI params. |
| 596 | Above config is useful when NAND device's bus-width information cannot |
| 597 | be determined from on-chip ONFI params, like in following scenarios: |
| 598 | - SPL boot does not support reading of ONFI parameters. This is done to |
| 599 | keep SPL code foot-print small. |
| 600 | - In current U-Boot flow using nand_init(), driver initialization |
| 601 | happens in board_nand_init() which is called before any device probe |
| 602 | (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are |
| 603 | not available while configuring controller. So a static CONFIG_NAND_xx |
| 604 | is needed to know the device's bus-width in advance. |
| 605 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 606 | if SPL |
| 607 | |
Tom Rini | 8e6d9c7 | 2021-09-22 14:50:33 -0400 | [diff] [blame] | 608 | config SYS_NAND_5_ADDR_CYCLE |
| 609 | bool "Wait 5 address cycles during NAND commands" |
| 610 | depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \ |
| 611 | (SPL_NAND_SUPPORT && NAND_ATMEL) |
| 612 | default y |
| 613 | help |
| 614 | Some controllers require waiting for 5 address cycles when issuing |
| 615 | some commands, on NAND chips larger than 128MiB. |
| 616 | |
Tom Rini | a2fbd4a | 2021-09-22 14:50:32 -0400 | [diff] [blame] | 617 | choice |
Tom Rini | fdae007 | 2021-09-22 14:50:34 -0400 | [diff] [blame] | 618 | prompt "NAND bad block marker/indicator position in the OOB" |
Tom Rini | a2fbd4a | 2021-09-22 14:50:32 -0400 | [diff] [blame] | 619 | depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \ |
| 620 | SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC) |
| 621 | default HAS_NAND_LARGE_BADBLOCK_POS |
| 622 | help |
| 623 | In the OOB, which position contains the badblock information. |
| 624 | |
| 625 | config HAS_NAND_LARGE_BADBLOCK_POS |
| 626 | bool "Set the bad block marker/indicator to the 'large' position" |
| 627 | |
| 628 | config HAS_NAND_SMALL_BADBLOCK_POS |
| 629 | bool "Set the bad block marker/indicator to the 'small' position" |
| 630 | |
| 631 | endchoice |
| 632 | |
| 633 | config SYS_NAND_BAD_BLOCK_POS |
| 634 | int |
| 635 | default 0 if HAS_NAND_LARGE_BADBLOCK_POS |
| 636 | default 5 if HAS_NAND_SMALL_BADBLOCK_POS |
| 637 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 638 | config SYS_NAND_U_BOOT_LOCATIONS |
| 639 | bool "Define U-boot binaries locations in NAND" |
| 640 | help |
| 641 | Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. |
| 642 | This option should not be enabled when compiling U-boot for boards |
| 643 | defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h |
| 644 | file. |
| 645 | |
| 646 | config SYS_NAND_U_BOOT_OFFS |
| 647 | hex "Location in NAND to read U-Boot from" |
| 648 | default 0x800000 if NAND_SUNXI |
| 649 | depends on SYS_NAND_U_BOOT_LOCATIONS |
| 650 | help |
| 651 | Set the offset from the start of the nand where u-boot should be |
| 652 | loaded from. |
| 653 | |
| 654 | config SYS_NAND_U_BOOT_OFFS_REDUND |
| 655 | hex "Location in NAND to read U-Boot from" |
| 656 | default SYS_NAND_U_BOOT_OFFS |
| 657 | depends on SYS_NAND_U_BOOT_LOCATIONS |
| 658 | help |
| 659 | Set the offset from the start of the nand where the redundant u-boot |
| 660 | should be loaded from. |
| 661 | |
| 662 | config SPL_NAND_AM33XX_BCH |
| 663 | bool "Enables SPL-NAND driver which supports ELM based" |
Tom Rini | 0a83cc2 | 2022-06-10 23:03:09 -0400 | [diff] [blame] | 664 | depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 665 | default y |
| 666 | help |
| 667 | Hardware ECC correction. This is useful for platforms which have ELM |
| 668 | hardware engine and use NAND boot mode. |
| 669 | Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, |
| 670 | so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling |
| 671 | SPL-NAND driver with software ECC correction support. |
| 672 | |
| 673 | config SPL_NAND_DENALI |
| 674 | bool "Support Denali NAND controller for SPL" |
Tom Rini | 0a83cc2 | 2022-06-10 23:03:09 -0400 | [diff] [blame] | 675 | depends on SPL_NAND_SUPPORT |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 676 | help |
| 677 | This is a small implementation of the Denali NAND controller |
| 678 | for use on SPL. |
| 679 | |
Masahiro Yamada | 64648cb | 2020-04-17 16:51:42 +0900 | [diff] [blame] | 680 | config NAND_DENALI_SPARE_AREA_SKIP_BYTES |
| 681 | int "Number of bytes skipped in OOB area" |
| 682 | depends on SPL_NAND_DENALI |
| 683 | range 0 63 |
| 684 | help |
| 685 | This option specifies the number of bytes to skip from the beginning |
| 686 | of OOB area before last ECC sector data starts. This is potentially |
| 687 | used to preserve the bad block marker in the OOB area. |
| 688 | |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 689 | config SPL_NAND_SIMPLE |
| 690 | bool "Use simple SPL NAND driver" |
Tom Rini | 0a83cc2 | 2022-06-10 23:03:09 -0400 | [diff] [blame] | 691 | depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT |
Miquel Raynal | 1f1ae15 | 2018-08-16 17:30:07 +0200 | [diff] [blame] | 692 | help |
| 693 | Support for NAND boot using simple NAND drivers that |
| 694 | expose the cmd_ctrl() interface. |
| 695 | endif |
| 696 | |
| 697 | endif # if NAND |