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Daniel Hellstrome045a4c2008-03-26 23:34:47 +01001/* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
4 * EP2S60.
5 *
6 * (C) Copyright 2003-2005
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * (C) Copyright 2008
10 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
11 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010013 */
14
15#ifndef __CONFIG_H__
16#define __CONFIG_H__
17
Francois Retief703d0242015-10-28 16:49:02 +020018#define CONFIG_DISPLAY_BOARDINFO
Francois Retiefb131cc52015-10-29 00:02:48 +020019
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010020/*
21 * High Level Configuration Options
22 * (easy to change)
23 */
24
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010025/* Altera NIOS Development board, Stratix II board */
Wolfgang Denka1be4762008-05-20 16:00:29 +020026#define CONFIG_GR_EP2S60 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010027
28/* CPU / AMBA BUS configuration */
Wolfgang Denka1be4762008-05-20 16:00:29 +020029#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010030
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010031/* Define this is the GR-2S60-MEZZ mezzanine is available and you
32 * want to use the USB and GRETH functionality of the board
33 */
34#undef GR_2S60_MEZZ
35
36#ifdef GR_2S60_MEZZ
37#define USE_GRETH 1
38#define USE_GRUSB 1
39#endif
40
41/*
42 * Serial console configuration
43 */
44#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010046
47/* Partitions */
48#define CONFIG_DOS_PARTITION
49#define CONFIG_MAC_PARTITION
50#define CONFIG_ISO_PARTITION
51
52/*
53 * Supported commands
54 */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010055#define CONFIG_CMD_REGINFO
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010056#define CONFIG_CMD_DIAG
57#define CONFIG_CMD_IRQ
58
59/* USB support */
60#if USE_GRUSB
61#define CONFIG_USB_UHCI
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010062#define CONFIG_USB_STORAGE
63/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD2a7a0312009-05-16 12:14:54 +020064#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010065#endif
66
67/*
68 * Autobooting
69 */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010070
71#define CONFIG_PREBOOT "echo;" \
72 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
73 "echo"
74
75#undef CONFIG_BOOTARGS
76
77#define CONFIG_EXTRA_ENV_SETTINGS \
78 "netdev=eth0\0" \
79 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
80 "nfsroot=${serverip}:${rootpath}\0" \
81 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
82 "addip=setenv bootargs ${bootargs} " \
83 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
84 ":${hostname}:${netdev}:off panic=1\0" \
85 "flash_nfs=run nfsargs addip;" \
86 "bootm ${kernel_addr}\0" \
87 "flash_self=run ramargs addip;" \
88 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
89 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
90 "scratch=40800000\0" \
Mike Frysingerc3c6bf12011-10-12 19:47:51 +000091 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010092 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
93 ""
94
95#define CONFIG_NETMASK 255.255.255.0
96#define CONFIG_GATEWAYIP 192.168.0.1
97#define CONFIG_SERVERIP 192.168.0.20
98#define CONFIG_IPADDR 192.168.0.207
Joe Hershberger257ff782011-10-13 13:03:47 +000099#define CONFIG_ROOTPATH "/export/rootfs"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100100#define CONFIG_HOSTNAME ml401
Joe Hershbergere4da2482011-10-13 13:03:48 +0000101#define CONFIG_BOOTFILE "/uImage"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100102
103#define CONFIG_BOOTCOMMAND "run flash_self"
104
105/* Memory MAP
106 *
107 * Flash:
108 * |--------------------------------|
109 * | 0x00000000 Text & Data & BSS | *
110 * | for Monitor | *
111 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
112 * | UNUSED / Growth | * 256kb
113 * |--------------------------------|
114 * | 0x00050000 Base custom area | *
115 * | kernel / FS | *
116 * | | * Rest of Flash
117 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
118 * | END-0x00008000 Environment | * 32kb
119 * |--------------------------------|
120 *
121 *
122 *
123 * Main Memory:
124 * |--------------------------------|
125 * | UNUSED / scratch area |
126 * | |
127 * | |
128 * | |
129 * | |
130 * |--------------------------------|
131 * | Monitor .Text / .DATA / .BSS | * 512kb
132 * | Relocated! | *
133 * |--------------------------------|
134 * | Monitor Malloc | * 128kb (contains relocated environment)
135 * |--------------------------------|
136 * | Monitor/kernel STACK | * 64kb
137 * |--------------------------------|
138 * | Page Table for MMU systems | * 2k
139 * |--------------------------------|
140 * | PROM Code accessed from Linux | * 6kb-128b
141 * |--------------------------------|
142 * | Global data (avail from kernel)| * 128b
143 * |--------------------------------|
144 *
145 */
146
147/*
148 * Flash configuration (8,16 or 32 MB)
149 * TEXT base always at 0xFFF00000
150 * ENV_ADDR always at 0xFFF40000
151 * FLASH_BASE at 0xFC000000 for 64 MB
152 * 0xFE000000 for 32 MB
153 * 0xFF000000 for 16 MB
154 * 0xFF800000 for 8 MB
155 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156/*#define CONFIG_SYS_NO_FLASH 1*/
157#define CONFIG_SYS_FLASH_BASE 0x00000000
158#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100159
160#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100163
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
165#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
166#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
167#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
168#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100169
170/*** CFI CONFIG ***/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200172#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_CFI
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100174/* Bypass cache when reading regs from flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100176/* Buffered writes (32byte/go) instead of single accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100178
179/*
180 * Environment settings
181 */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200182/*#define CONFIG_ENV_IS_NOWHERE 1*/
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200183#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200184/* CONFIG_ENV_ADDR need to be at sector boundary */
185#define CONFIG_ENV_SIZE 0x8000
186#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100188#define CONFIG_ENV_OVERWRITE 1
189
190/*
191 * Memory map
192 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_SDRAM_BASE 0x40000000
194#define CONFIG_SYS_SDRAM_SIZE 0x02000000
195#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100196
197/* no SRAM available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#undef CONFIG_SYS_SRAM_BASE
199#undef CONFIG_SYS_SRAM_SIZE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
202#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
203#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100204
Wolfgang Denk0191e472010-10-26 14:34:52 +0200205#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100206
Wolfgang Denk0191e472010-10-26 14:34:52 +0200207#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
211#define CONFIG_SYS_STACK_SIZE (0x10000-32)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100212
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200213#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
215# define CONFIG_SYS_RAMBOOT 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100216#endif
217
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
219#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
220#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100221
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
223#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100224
225/* relocated monitor area */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
227#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100228
229/* make un relocated address from relocated address */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200230#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100231
232/*
233 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
234 * with a PHY is attached the GRETH can be used on this board.
235 * Define USE_GRETH in order to use the mezzanine provided PHY with the
236 * onchip GRETH network MAC, note that this is not supported by the
237 * template design.
238 */
239#ifndef USE_GRETH
240
241/* USE SMC91C111 MAC */
Ben Warren0fd6aae2009-10-04 22:37:03 -0700242#define CONFIG_SMC91111 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100243#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
244#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
245#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
246/*#define CONFIG_SHOW_ACTIVITY*/
247#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
248
249#else
250
251/* USE GRETH Ethernet Driver */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100252#define CONFIG_GRETH 1
Masahiro Yamadacbafcdf2015-05-26 10:58:31 +0900253#endif
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100254
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100255#define CONFIG_PHY_ADDR 0x00
256
257/*
258 * Miscellaneous configurable options
259 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_LONGHELP /* undef to save memory */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100261#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100263#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100265#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
267#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
268#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100269
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
271#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100272
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100274
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100275/*-----------------------------------------------------------------------
276 * USB stuff
277 *-----------------------------------------------------------------------
278 */
279#define CONFIG_USB_CLOCK 0x0001BBBB
280#define CONFIG_USB_CONFIG 0x00005000
281
282/***** Gaisler GRLIB IP-Cores Config ********/
283
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284#define CONFIG_SYS_GRLIB_SDRAM 0
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100285
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100286/* No SDRAM Configuration */
287#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
288
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100289/* See, GRLIB Docs (grip.pdf) on how to set up
290 * These the memory controller registers.
291 */
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100292#define CONFIG_SYS_GRLIB_ESA_MCTRL1
293#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
294#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
295#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100296
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100297/* GRLIB FT-MCTRL configuration */
298#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
299#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
300#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
301#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100302
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100303/* DDR controller */
304#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
305#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100306
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100307/* no DDR2 Controller */
308#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100309
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100310/* Identification string */
Francois Retief703d0242015-10-28 16:49:02 +0200311#define CONFIG_IDENT_STRING " Gaisler LEON3 EP2S60"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100312
313/* default kernel command line */
314#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
315
316#endif /* __CONFIG_H */