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git01.mediatek.com / filogic / uboot / abb0f522e1fb1900030ab63f2dbddb1678c584ec / . / configs / socfpga_arria10_defconfig
blob: c3cd442d3744ed82df6666424891a6f255a3b3aa [file] [log] [blame]
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_SOCFPGA=y
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]3CONFIG_SYS_MALLOC_LEN=0x4000000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]4CONFIG_ENV_SIZE=0x2000
5CONFIG_ENV_OFFSET=0x4400
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]6CONFIG_DM_GPIO=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]7CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]8CONFIG_SPL_TEXT_BASE=0xFFE00000
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]9CONFIG_SPL_DRIVERS_MISC=y
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]10CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
11CONFIG_IDENT_STRING="socfpga_arria10"
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]12CONFIG_SPL_FS_FAT=y
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]13CONFIG_DISTRO_DEFAULTS=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]14CONFIG_FIT=y
Simon Glass65831d92021-12-18 11:27:50 -0700[diff] [blame]15CONFIG_TIMESTAMP=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]16CONFIG_SPL_FIT=y
Simon Glass5d144112020-07-19 13:56:10 -0600[diff] [blame]17# CONFIG_USE_SPL_FIT_GENERATOR is not set
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]18CONFIG_USE_BOOTARGS=y
19CONFIG_BOOTARGS="console=ttyS0,115200"
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]20# CONFIG_USE_BOOTCOMMAND is not set
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]21CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
Tien Fong Cheedf0544a2019-05-07 17:42:31 +0800[diff] [blame]22CONFIG_SYS_CONSOLE_IS_IN_ENV=y
23CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
24CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]25CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rini2bfc77a2022-03-23 17:20:08 -0400[diff] [blame]26CONFIG_CLOCKS=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame^]27CONFIG_SPL_PAD_TO=0x40000
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]28CONFIG_SPL_ENV_SUPPORT=y
Michal Simek1aab1142020-09-09 14:41:56 +0200[diff] [blame]29CONFIG_SPL_FPGA=y
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]30CONFIG_SYS_MAXARGS=32
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]31CONFIG_CMD_ASKENV=y
32CONFIG_CMD_GREPENV=y
33# CONFIG_CMD_FLASH is not set
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]34CONFIG_CMD_GPIO=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]35CONFIG_CMD_MMC=y
Ley Foon Tan0bf9acc2020-04-22 10:06:45 +0800[diff] [blame]36CONFIG_CMD_USB=y
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]37CONFIG_CMD_CACHE=y
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]38CONFIG_CMD_EXT4_WRITE=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]39CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]40CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]41CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]42CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]43CONFIG_VERSION_VARIABLE=y
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]44CONFIG_SPL_DM_SEQ_ALIAS=y
Ley Foon Tan10b69642017-04-26 02:44:46 +0800[diff] [blame]45CONFIG_DWAPB_GPIO=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]46CONFIG_FS_LOADER=y
Keerthyfe8f6092022-01-27 13:16:53 +0100[diff] [blame]47CONFIG_SPL_FS_LOADER=y
Tien Fong Cheedf0544a2019-05-07 17:42:31 +0800[diff] [blame]48CONFIG_MMC_DW=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]49CONFIG_MTD=y
Tien Fong Cheedf0544a2019-05-07 17:42:31 +0800[diff] [blame]50CONFIG_PHY_MICREL=y
51CONFIG_PHY_MICREL_KSZ90X1=y
Marek Vasutc5757c92018-08-13 21:02:54 +0200[diff] [blame]52CONFIG_DM_ETH=y
53CONFIG_ETH_DESIGNWARE=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]54CONFIG_MII=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]55CONFIG_SPI=y
Marek Vasutaaa40e72018-08-18 16:00:31 +0200[diff] [blame]56CONFIG_TIMER=y
57CONFIG_SPL_TIMER=y
58CONFIG_DESIGNWARE_APB_TIMER=y
Ley Foon Tan0bf9acc2020-04-22 10:06:45 +0800[diff] [blame]59CONFIG_USB=y
Ley Foon Tan0bf9acc2020-04-22 10:06:45 +0800[diff] [blame]60CONFIG_USB_DWC2=y
Simon Goldschmidtfe6275f2019-10-05 22:10:11 +0200[diff] [blame]61# CONFIG_SPL_WDT is not set