Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016 Google, Inc |
| 4 | * |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 5 | * Based on code from coreboot src/soc/intel/broadwell/cpu.c |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <dm.h> |
| 10 | #include <cpu.h> |
| 11 | #include <asm/cpu.h> |
| 12 | #include <asm/cpu_x86.h> |
| 13 | #include <asm/cpu_common.h> |
| 14 | #include <asm/intel_regs.h> |
Simon Glass | 412f11b | 2019-04-25 21:58:50 -0600 | [diff] [blame] | 15 | #include <asm/lpc_common.h> |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 16 | #include <asm/msr.h> |
Simon Glass | 412f11b | 2019-04-25 21:58:50 -0600 | [diff] [blame] | 17 | #include <asm/pci.h> |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 18 | #include <asm/post.h> |
| 19 | #include <asm/turbo.h> |
| 20 | #include <asm/arch/cpu.h> |
| 21 | #include <asm/arch/pch.h> |
| 22 | #include <asm/arch/rcb.h> |
| 23 | |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 24 | int arch_cpu_init_dm(void) |
| 25 | { |
| 26 | struct udevice *dev; |
| 27 | int ret; |
| 28 | |
| 29 | /* Start up the LPC so we have serial */ |
| 30 | ret = uclass_first_device(UCLASS_LPC, &dev); |
| 31 | if (ret) |
| 32 | return ret; |
| 33 | if (!dev) |
| 34 | return -ENODEV; |
| 35 | ret = cpu_set_flex_ratio_to_tdp_nominal(); |
| 36 | if (ret) |
| 37 | return ret; |
| 38 | |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | void set_max_freq(void) |
| 43 | { |
Simon Glass | b12689d | 2019-09-25 08:56:38 -0600 | [diff] [blame] | 44 | msr_t msr, perf_ctl; |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 45 | |
Simon Glass | b12689d | 2019-09-25 08:56:38 -0600 | [diff] [blame] | 46 | if (cpu_config_tdp_levels()) { |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 47 | /* Set to nominal TDP ratio */ |
| 48 | msr = msr_read(MSR_CONFIG_TDP_NOMINAL); |
| 49 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 50 | } else { |
| 51 | /* Platform Info bits 15:8 give max ratio */ |
| 52 | msr = msr_read(MSR_PLATFORM_INFO); |
| 53 | perf_ctl.lo = msr.lo & 0xff00; |
| 54 | } |
| 55 | |
| 56 | perf_ctl.hi = 0; |
Simon Glass | 76ae027 | 2019-09-25 08:56:35 -0600 | [diff] [blame] | 57 | msr_write(MSR_IA32_PERF_CTL, perf_ctl); |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 58 | |
| 59 | debug("CPU: frequency set to %d MHz\n", |
Simon Glass | 4347d83 | 2019-09-25 08:56:37 -0600 | [diff] [blame] | 60 | ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ); |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | int arch_cpu_init(void) |
| 64 | { |
| 65 | post_code(POST_CPU_INIT); |
| 66 | |
Simon Glass | 42bf3b9 | 2019-09-25 08:11:40 -0600 | [diff] [blame] | 67 | #ifdef CONFIG_TPL |
| 68 | /* Do a mini-init if TPL has already done the full init */ |
| 69 | return x86_cpu_reinit_f(); |
| 70 | #else |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 71 | return x86_cpu_init_f(); |
Simon Glass | 42bf3b9 | 2019-09-25 08:11:40 -0600 | [diff] [blame] | 72 | #endif |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 73 | } |
| 74 | |
Simon Glass | ee7c36f | 2017-03-28 10:27:30 -0600 | [diff] [blame] | 75 | int checkcpu(void) |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 76 | { |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 77 | int ret; |
| 78 | |
| 79 | set_max_freq(); |
| 80 | |
| 81 | ret = cpu_common_init(); |
| 82 | if (ret) |
| 83 | return ret; |
| 84 | gd->arch.pei_boot_mode = PEI_BOOT_NONE; |
| 85 | |
Simon Glass | ee7c36f | 2017-03-28 10:27:30 -0600 | [diff] [blame] | 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | int print_cpuinfo(void) |
| 90 | { |
| 91 | char processor_name[CPU_MAX_NAME_LEN]; |
| 92 | const char *name; |
| 93 | |
Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 94 | /* Print processor name */ |
| 95 | name = cpu_get_name(processor_name); |
| 96 | printf("CPU: %s\n", name); |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
Simon Glass | 412f11b | 2019-04-25 21:58:50 -0600 | [diff] [blame] | 101 | void board_debug_uart_init(void) |
| 102 | { |
Simon Glass | 412f11b | 2019-04-25 21:58:50 -0600 | [diff] [blame] | 103 | /* com1 / com2 decode range */ |
Simon Glass | a546458 | 2019-08-31 21:23:18 -0600 | [diff] [blame] | 104 | pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16); |
Simon Glass | 412f11b | 2019-04-25 21:58:50 -0600 | [diff] [blame] | 105 | |
Simon Glass | a546458 | 2019-08-31 21:23:18 -0600 | [diff] [blame] | 106 | pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16); |
Simon Glass | 412f11b | 2019-04-25 21:58:50 -0600 | [diff] [blame] | 107 | } |