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wdenk9b7f3842003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk9b7f3842003-10-09 20:09:04 +00006 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenk9b7f3842003-10-09 20:09:04 +000015#define CONFIG_DBAU1X00 1
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090016#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk9b7f3842003-10-09 20:09:04 +000017
Daniel Schwierzeck2bc7eeb2014-11-15 23:30:01 +010018#define CONFIG_DISPLAY_BOARDINFO
19
wdenk4ea537d2003-12-07 18:32:37 +000020#ifdef CONFIG_DBAU1000
wdenk9b7f3842003-10-09 20:09:04 +000021/* Also known as Merlot */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090022#define CONFIG_SOC_AU1000 1
wdenk4ea537d2003-12-07 18:32:37 +000023#else
24#ifdef CONFIG_DBAU1100
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090025#define CONFIG_SOC_AU1100 1
wdenk4ea537d2003-12-07 18:32:37 +000026#else
27#ifdef CONFIG_DBAU1500
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090028#define CONFIG_SOC_AU1500 1
wdenk1ebf41e2004-01-02 14:00:00 +000029#else
wdenk96c7a8c2005-01-09 22:28:56 +000030#ifdef CONFIG_DBAU1550
31/* Cabernet */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090032#define CONFIG_SOC_AU1550 1
wdenk96c7a8c2005-01-09 22:28:56 +000033#else
wdenk4ea537d2003-12-07 18:32:37 +000034#error "No valid board set"
35#endif
36#endif
37#endif
wdenk96c7a8c2005-01-09 22:28:56 +000038#endif
wdenk9b7f3842003-10-09 20:09:04 +000039
wdenk1ebf41e2004-01-02 14:00:00 +000040#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
wdenk9b7f3842003-10-09 20:09:04 +000041
42#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
43
44#define CONFIG_BAUDRATE 115200
45
46/* valid baudrates */
wdenk9b7f3842003-10-09 20:09:04 +000047
48#define CONFIG_TIMESTAMP /* Print image info with timestamp */
49#undef CONFIG_BOOTARGS
50
51#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010052 "addmisc=setenv bootargs ${bootargs} " \
53 "console=ttyS0,${baudrate} " \
wdenk9b7f3842003-10-09 20:09:04 +000054 "panic=1\0" \
55 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010056 "load=tftp 80500000 ${u-boot}\0" \
wdenk9b7f3842003-10-09 20:09:04 +000057 ""
wdenk96c7a8c2005-01-09 22:28:56 +000058
59#ifdef CONFIG_DBAU1550
60/* Boot from flash by default, revert to bootp */
61#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000062#else /* CONFIG_DBAU1550 */
Heiko Schocher65d4f8b2006-04-11 14:53:29 +020063#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000064#endif /* CONFIG_DBAU1550 */
65
Jon Loeligerb15a23b2007-07-04 22:32:03 -050066
67/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050068 * BOOTP options
69 */
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76/*
Jon Loeligerb15a23b2007-07-04 22:32:03 -050077 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80
81#undef CONFIG_CMD_BDI
82#undef CONFIG_CMD_BEDBUG
83#undef CONFIG_CMD_ELF
Mike Frysinger78dcaf42009-01-28 19:08:14 -050084#undef CONFIG_CMD_SAVEENV
Jon Loeligerb15a23b2007-07-04 22:32:03 -050085#undef CONFIG_CMD_FAT
86#undef CONFIG_CMD_FPGA
87#undef CONFIG_CMD_MII
88#undef CONFIG_CMD_RUN
89
90
91#ifdef CONFIG_DBAU1550
92
93#define CONFIG_CMD_FLASH
94#define CONFIG_CMD_LOADB
95#define CONFIG_CMD_NET
96
97#undef CONFIG_CMD_I2C
98#undef CONFIG_CMD_IDE
99#undef CONFIG_CMD_NFS
100#undef CONFIG_CMD_PCMCIA
101
102#else
103
104#define CONFIG_CMD_IDE
105#define CONFIG_CMD_DHCP
106
107#undef CONFIG_CMD_FLASH
108#undef CONFIG_CMD_LOADB
109#undef CONFIG_CMD_LOADS
110
111#endif
112
wdenk9b7f3842003-10-09 20:09:04 +0000113
114/*
115 * Miscellaneous configurable options
116 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk96c7a8c2005-01-09 22:28:56 +0000118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
wdenk96c7a8c2005-01-09 22:28:56 +0000120
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
122#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
123#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk9b7f3842003-10-09 20:09:04 +0000124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_MHZ 396
wdenk96c7a8c2005-01-09 22:28:56 +0000130
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#if (CONFIG_SYS_MHZ % 12) != 0
wdenk96c7a8c2005-01-09 22:28:56 +0000132#error "Invalid CPU frequency - must be multiple of 12!"
133#endif
134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashi5d374e02008-06-05 22:29:00 +0900136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk9b7f3842003-10-09 20:09:04 +0000138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk9b7f3842003-10-09 20:09:04 +0000140
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_MEMTEST_START 0x80100000
142#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk9b7f3842003-10-09 20:09:04 +0000143
144/*-----------------------------------------------------------------------
145 * FLASH and environment organization
146 */
wdenk96c7a8c2005-01-09 22:28:56 +0000147#ifdef CONFIG_DBAU1550
148
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
150#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenk96c7a8c2005-01-09 22:28:56 +0000151
152#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
153#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
154
wdenk96c7a8c2005-01-09 22:28:56 +0000155#else /* CONFIG_DBAU1550 */
156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
158#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk9b7f3842003-10-09 20:09:04 +0000159
160#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
161#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
162
wdenk96c7a8c2005-01-09 22:28:56 +0000163#endif /* CONFIG_DBAU1550 */
164
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocher65d4f8b2006-04-11 14:53:29 +0200166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200168#define CONFIG_FLASH_CFI_DRIVER 1
wdenk96c7a8c2005-01-09 22:28:56 +0000169
wdenk9b7f3842003-10-09 20:09:04 +0000170/* The following #defines are needed to get flash environment right */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk9b7f3842003-10-09 20:09:04 +0000173
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk9b7f3842003-10-09 20:09:04 +0000175
176/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk9b7f3842003-10-09 20:09:04 +0000178
179/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
181#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk9b7f3842003-10-09 20:09:04 +0000182
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200183#define CONFIG_ENV_IS_NOWHERE 1
wdenk9b7f3842003-10-09 20:09:04 +0000184
185/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200186#define CONFIG_ENV_ADDR 0xB0030000
187#define CONFIG_ENV_SIZE 0x10000
wdenk9b7f3842003-10-09 20:09:04 +0000188
189#define CONFIG_FLASH_16BIT
190
191#define CONFIG_NR_DRAM_BANKS 2
192
wdenk9b7f3842003-10-09 20:09:04 +0000193
wdenk96c7a8c2005-01-09 22:28:56 +0000194#ifdef CONFIG_DBAU1550
195#define MEM_SIZE 192
196#else
197#define MEM_SIZE 64
198#endif
199
wdenk9b7f3842003-10-09 20:09:04 +0000200#define CONFIG_MEMSIZE_IN_BYTES
201
wdenk96c7a8c2005-01-09 22:28:56 +0000202#ifndef CONFIG_DBAU1550
wdenk9b7f3842003-10-09 20:09:04 +0000203/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
205#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk9b7f3842003-10-09 20:09:04 +0000206#define CONFIG_PCMCIA_SLOT_A
207
208#define CONFIG_ATAPI 1
209#define CONFIG_MAC_PARTITION 1
210
211/* We run CF in "true ide" mode or a harddrive via pcmcia */
212#define CONFIG_IDE_PCMCIA 1
213
214/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
216#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk9b7f3842003-10-09 20:09:04 +0000217
218#undef CONFIG_IDE_LED /* LED for ide not supported */
219#undef CONFIG_IDE_RESET /* reset for ide not supported */
220
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk9b7f3842003-10-09 20:09:04 +0000222
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk9b7f3842003-10-09 20:09:04 +0000224
wdenk1ebf41e2004-01-02 14:00:00 +0000225/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk9b7f3842003-10-09 20:09:04 +0000227
228/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk9b7f3842003-10-09 20:09:04 +0000230
231/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk96c7a8c2005-01-09 22:28:56 +0000233#endif /* CONFIG_DBAU1550 */
wdenk9b7f3842003-10-09 20:09:04 +0000234
235/*-----------------------------------------------------------------------
236 * Cache Configuration
237 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_DCACHE_SIZE 16384
239#define CONFIG_SYS_ICACHE_SIZE 16384
240#define CONFIG_SYS_CACHELINE_SIZE 32
wdenk9b7f3842003-10-09 20:09:04 +0000241
wdenk9b7f3842003-10-09 20:09:04 +0000242#endif /* __CONFIG_H */