Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> |
| 4 | * |
| 5 | * Generic reset driver for x86 processor |
| 6 | */ |
| 7 | |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 8 | #include <dm.h> |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 9 | #include <efi_loader.h> |
| 10 | #include <pch.h> |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 11 | #include <sysreset.h> |
Simon Glass | 5046109 | 2020-04-08 16:57:35 -0600 | [diff] [blame] | 12 | #include <acpi/acpi_s3.h> |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 13 | #include <asm/io.h> |
| 14 | #include <asm/processor.h> |
Simon Glass | 71d5777 | 2020-12-19 10:40:04 -0700 | [diff] [blame] | 15 | #include <asm/sysreset.h> |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * Power down the machine by using the power management sleep control |
| 19 | * of the chipset. This will currently only work on Intel chipsets. |
| 20 | * However, adapting it to new chipsets is fairly simple. You will |
| 21 | * have to find the IO address of the power management register block |
| 22 | * in your southbridge, and look up the appropriate SLP_TYP_S5 value |
| 23 | * from your southbridge's data sheet. |
| 24 | * |
| 25 | * This function never returns. |
| 26 | */ |
| 27 | int pch_sysreset_power_off(struct udevice *dev) |
| 28 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 29 | struct x86_sysreset_plat *plat = dev_get_plat(dev); |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 30 | struct pch_pmbase_info pm; |
| 31 | u32 reg32; |
| 32 | int ret; |
| 33 | |
| 34 | if (!plat->pch) |
| 35 | return -ENOENT; |
| 36 | ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm)); |
| 37 | if (ret) |
| 38 | return ret; |
| 39 | |
| 40 | /* |
| 41 | * Mask interrupts or system might stay in a coma, not executing code |
| 42 | * anymore, but not powered off either. |
| 43 | */ |
| 44 | asm("cli"); |
| 45 | |
| 46 | /* |
| 47 | * Avoid any GPI waking the system from S5* or the system might stay in |
| 48 | * a coma |
| 49 | */ |
| 50 | outl(0x00000000, pm.base + pm.gpio0_en_ofs); |
| 51 | |
| 52 | /* Clear Power Button Status */ |
| 53 | outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs); |
| 54 | |
| 55 | /* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */ |
| 56 | reg32 = inl(pm.base + pm.pm1_cnt_ofs); |
| 57 | |
| 58 | /* Set Sleeping Type to S5 (poweroff) */ |
| 59 | reg32 &= ~(SLP_EN | SLP_TYP); |
| 60 | reg32 |= SLP_TYP_S5; |
| 61 | outl(reg32, pm.base + pm.pm1_cnt_ofs); |
| 62 | |
| 63 | /* Now set the Sleep Enable bit */ |
| 64 | reg32 |= SLP_EN; |
| 65 | outl(reg32, pm.base + pm.pm1_cnt_ofs); |
| 66 | |
| 67 | for (;;) |
| 68 | asm("hlt"); |
| 69 | } |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 70 | |
Simon Glass | a21dda9 | 2019-05-02 10:52:13 -0600 | [diff] [blame] | 71 | static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type) |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 72 | { |
| 73 | int value; |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 74 | int ret; |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 75 | |
| 76 | switch (type) { |
| 77 | case SYSRESET_WARM: |
| 78 | value = SYS_RST | RST_CPU; |
| 79 | break; |
| 80 | case SYSRESET_COLD: |
| 81 | value = SYS_RST | RST_CPU | FULL_RST; |
| 82 | break; |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 83 | case SYSRESET_POWER_OFF: |
| 84 | ret = pch_sysreset_power_off(dev); |
| 85 | if (ret) |
| 86 | return ret; |
| 87 | return -EINPROGRESS; |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 88 | default: |
Paul Barker | bdb3a3f | 2023-11-08 08:51:10 +0000 | [diff] [blame] | 89 | return -EPROTONOSUPPORT; |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | outb(value, IO_PORT_RESET); |
| 93 | |
| 94 | return -EINPROGRESS; |
| 95 | } |
| 96 | |
Simon Glass | 8ea4982 | 2019-05-02 10:52:15 -0600 | [diff] [blame] | 97 | static int x86_sysreset_get_last(struct udevice *dev) |
| 98 | { |
| 99 | return SYSRESET_POWER; |
| 100 | } |
| 101 | |
Alexander Graf | f6cc0db | 2019-01-30 11:46:34 +0100 | [diff] [blame] | 102 | #ifdef CONFIG_EFI_LOADER |
| 103 | void __efi_runtime EFIAPI efi_reset_system( |
| 104 | enum efi_reset_type reset_type, |
| 105 | efi_status_t reset_status, |
| 106 | unsigned long data_size, void *reset_data) |
| 107 | { |
Simon Glass | a21dda9 | 2019-05-02 10:52:13 -0600 | [diff] [blame] | 108 | int value; |
| 109 | |
| 110 | /* |
| 111 | * inline this code since we are not caused in the context of a |
| 112 | * udevice and passing NULL to x86_sysreset_request() is too horrible. |
| 113 | */ |
Alexander Graf | f6cc0db | 2019-01-30 11:46:34 +0100 | [diff] [blame] | 114 | if (reset_type == EFI_RESET_COLD || |
| 115 | reset_type == EFI_RESET_PLATFORM_SPECIFIC) |
Simon Glass | a21dda9 | 2019-05-02 10:52:13 -0600 | [diff] [blame] | 116 | value = SYS_RST | RST_CPU | FULL_RST; |
| 117 | else /* assume EFI_RESET_WARM since we cannot return an error */ |
| 118 | value = SYS_RST | RST_CPU; |
| 119 | outb(value, IO_PORT_RESET); |
Alexander Graf | f6cc0db | 2019-01-30 11:46:34 +0100 | [diff] [blame] | 120 | |
| 121 | /* TODO EFI_RESET_SHUTDOWN */ |
| 122 | |
| 123 | while (1) { } |
| 124 | } |
| 125 | #endif |
| 126 | |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 127 | static int x86_sysreset_probe(struct udevice *dev) |
| 128 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 129 | struct x86_sysreset_plat *plat = dev_get_plat(dev); |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 130 | |
Simon Glass | 6b31e61 | 2023-05-09 18:13:47 +0800 | [diff] [blame] | 131 | /* |
| 132 | * Locate the PCH if there is one. It isn't essential. Avoid this before |
| 133 | * relocation as we shouldn't need reset then and it needs a lot of |
| 134 | * memory for PCI enumeration. |
| 135 | */ |
| 136 | if (gd->flags & GD_FLG_RELOC) |
| 137 | uclass_first_device(UCLASS_PCH, &plat->pch); |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 138 | |
| 139 | return 0; |
| 140 | } |
Alexander Graf | f6cc0db | 2019-01-30 11:46:34 +0100 | [diff] [blame] | 141 | |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 142 | static const struct udevice_id x86_sysreset_ids[] = { |
| 143 | { .compatible = "x86,reset" }, |
| 144 | { } |
| 145 | }; |
| 146 | |
| 147 | static struct sysreset_ops x86_sysreset_ops = { |
| 148 | .request = x86_sysreset_request, |
Simon Glass | 8ea4982 | 2019-05-02 10:52:15 -0600 | [diff] [blame] | 149 | .get_last = x86_sysreset_get_last, |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 150 | }; |
| 151 | |
Simon Glass | a055da8 | 2020-10-05 05:27:01 -0600 | [diff] [blame] | 152 | U_BOOT_DRIVER(x86_reset) = { |
| 153 | .name = "x86_reset", |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 154 | .id = UCLASS_SYSRESET, |
| 155 | .of_match = x86_sysreset_ids, |
| 156 | .ops = &x86_sysreset_ops, |
Simon Glass | 90bf4d9 | 2019-05-02 10:52:14 -0600 | [diff] [blame] | 157 | .probe = x86_sysreset_probe, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 158 | .plat_auto = sizeof(struct x86_sysreset_plat), |
Bin Meng | d18cdd4 | 2018-07-03 02:48:40 -0700 | [diff] [blame] | 159 | }; |