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Bin Mengd18cdd42018-07-03 02:48:40 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * Generic reset driver for x86 processor
6 */
7
Bin Mengd18cdd42018-07-03 02:48:40 -07008#include <dm.h>
Simon Glass90bf4d92019-05-02 10:52:14 -06009#include <efi_loader.h>
10#include <pch.h>
Bin Mengd18cdd42018-07-03 02:48:40 -070011#include <sysreset.h>
Simon Glass50461092020-04-08 16:57:35 -060012#include <acpi/acpi_s3.h>
Bin Mengd18cdd42018-07-03 02:48:40 -070013#include <asm/io.h>
14#include <asm/processor.h>
Simon Glass71d57772020-12-19 10:40:04 -070015#include <asm/sysreset.h>
Simon Glass90bf4d92019-05-02 10:52:14 -060016
17/*
18 * Power down the machine by using the power management sleep control
19 * of the chipset. This will currently only work on Intel chipsets.
20 * However, adapting it to new chipsets is fairly simple. You will
21 * have to find the IO address of the power management register block
22 * in your southbridge, and look up the appropriate SLP_TYP_S5 value
23 * from your southbridge's data sheet.
24 *
25 * This function never returns.
26 */
27int pch_sysreset_power_off(struct udevice *dev)
28{
Simon Glassb75b15b2020-12-03 16:55:23 -070029 struct x86_sysreset_plat *plat = dev_get_plat(dev);
Simon Glass90bf4d92019-05-02 10:52:14 -060030 struct pch_pmbase_info pm;
31 u32 reg32;
32 int ret;
33
34 if (!plat->pch)
35 return -ENOENT;
36 ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm));
37 if (ret)
38 return ret;
39
40 /*
41 * Mask interrupts or system might stay in a coma, not executing code
42 * anymore, but not powered off either.
43 */
44 asm("cli");
45
46 /*
47 * Avoid any GPI waking the system from S5* or the system might stay in
48 * a coma
49 */
50 outl(0x00000000, pm.base + pm.gpio0_en_ofs);
51
52 /* Clear Power Button Status */
53 outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs);
54
55 /* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */
56 reg32 = inl(pm.base + pm.pm1_cnt_ofs);
57
58 /* Set Sleeping Type to S5 (poweroff) */
59 reg32 &= ~(SLP_EN | SLP_TYP);
60 reg32 |= SLP_TYP_S5;
61 outl(reg32, pm.base + pm.pm1_cnt_ofs);
62
63 /* Now set the Sleep Enable bit */
64 reg32 |= SLP_EN;
65 outl(reg32, pm.base + pm.pm1_cnt_ofs);
66
67 for (;;)
68 asm("hlt");
69}
Bin Mengd18cdd42018-07-03 02:48:40 -070070
Simon Glassa21dda92019-05-02 10:52:13 -060071static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
Bin Mengd18cdd42018-07-03 02:48:40 -070072{
73 int value;
Simon Glass90bf4d92019-05-02 10:52:14 -060074 int ret;
Bin Mengd18cdd42018-07-03 02:48:40 -070075
76 switch (type) {
77 case SYSRESET_WARM:
78 value = SYS_RST | RST_CPU;
79 break;
80 case SYSRESET_COLD:
81 value = SYS_RST | RST_CPU | FULL_RST;
82 break;
Simon Glass90bf4d92019-05-02 10:52:14 -060083 case SYSRESET_POWER_OFF:
84 ret = pch_sysreset_power_off(dev);
85 if (ret)
86 return ret;
87 return -EINPROGRESS;
Bin Mengd18cdd42018-07-03 02:48:40 -070088 default:
Paul Barkerbdb3a3f2023-11-08 08:51:10 +000089 return -EPROTONOSUPPORT;
Bin Mengd18cdd42018-07-03 02:48:40 -070090 }
91
92 outb(value, IO_PORT_RESET);
93
94 return -EINPROGRESS;
95}
96
Simon Glass8ea49822019-05-02 10:52:15 -060097static int x86_sysreset_get_last(struct udevice *dev)
98{
99 return SYSRESET_POWER;
100}
101
Alexander Graff6cc0db2019-01-30 11:46:34 +0100102#ifdef CONFIG_EFI_LOADER
103void __efi_runtime EFIAPI efi_reset_system(
104 enum efi_reset_type reset_type,
105 efi_status_t reset_status,
106 unsigned long data_size, void *reset_data)
107{
Simon Glassa21dda92019-05-02 10:52:13 -0600108 int value;
109
110 /*
111 * inline this code since we are not caused in the context of a
112 * udevice and passing NULL to x86_sysreset_request() is too horrible.
113 */
Alexander Graff6cc0db2019-01-30 11:46:34 +0100114 if (reset_type == EFI_RESET_COLD ||
115 reset_type == EFI_RESET_PLATFORM_SPECIFIC)
Simon Glassa21dda92019-05-02 10:52:13 -0600116 value = SYS_RST | RST_CPU | FULL_RST;
117 else /* assume EFI_RESET_WARM since we cannot return an error */
118 value = SYS_RST | RST_CPU;
119 outb(value, IO_PORT_RESET);
Alexander Graff6cc0db2019-01-30 11:46:34 +0100120
121 /* TODO EFI_RESET_SHUTDOWN */
122
123 while (1) { }
124}
125#endif
126
Simon Glass90bf4d92019-05-02 10:52:14 -0600127static int x86_sysreset_probe(struct udevice *dev)
128{
Simon Glassb75b15b2020-12-03 16:55:23 -0700129 struct x86_sysreset_plat *plat = dev_get_plat(dev);
Simon Glass90bf4d92019-05-02 10:52:14 -0600130
Simon Glass6b31e612023-05-09 18:13:47 +0800131 /*
132 * Locate the PCH if there is one. It isn't essential. Avoid this before
133 * relocation as we shouldn't need reset then and it needs a lot of
134 * memory for PCI enumeration.
135 */
136 if (gd->flags & GD_FLG_RELOC)
137 uclass_first_device(UCLASS_PCH, &plat->pch);
Simon Glass90bf4d92019-05-02 10:52:14 -0600138
139 return 0;
140}
Alexander Graff6cc0db2019-01-30 11:46:34 +0100141
Bin Mengd18cdd42018-07-03 02:48:40 -0700142static const struct udevice_id x86_sysreset_ids[] = {
143 { .compatible = "x86,reset" },
144 { }
145};
146
147static struct sysreset_ops x86_sysreset_ops = {
148 .request = x86_sysreset_request,
Simon Glass8ea49822019-05-02 10:52:15 -0600149 .get_last = x86_sysreset_get_last,
Bin Mengd18cdd42018-07-03 02:48:40 -0700150};
151
Simon Glassa055da82020-10-05 05:27:01 -0600152U_BOOT_DRIVER(x86_reset) = {
153 .name = "x86_reset",
Bin Mengd18cdd42018-07-03 02:48:40 -0700154 .id = UCLASS_SYSRESET,
155 .of_match = x86_sysreset_ids,
156 .ops = &x86_sysreset_ops,
Simon Glass90bf4d92019-05-02 10:52:14 -0600157 .probe = x86_sysreset_probe,
Simon Glassb75b15b2020-12-03 16:55:23 -0700158 .plat_auto = sizeof(struct x86_sysreset_plat),
Bin Mengd18cdd42018-07-03 02:48:40 -0700159};