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git01.mediatek.com / filogic / uboot / ab06a533f08effbbaa2de381e61b6b33778b4b5d / . / src / arm / nxp / imx / imx6sx.dtsi
blob: 5132b575b001564b9767605ae7ff044701516673 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2014 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/clock/imx6sx-clock.h>
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx6sx-pinfunc.h"
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 */
19 chosen {};
20
21 aliases {
22 can0 = &flexcan1;
23 can1 = &flexcan2;
24 ethernet0 = &fec1;
25 ethernet1 = &fec2;
26 gpio0 = &gpio1;
27 gpio1 = &gpio2;
28 gpio2 = &gpio3;
29 gpio3 = &gpio4;
30 gpio4 = &gpio5;
31 gpio5 = &gpio6;
32 gpio6 = &gpio7;
33 i2c0 = &i2c1;
34 i2c1 = &i2c2;
35 i2c2 = &i2c3;
36 i2c3 = &i2c4;
37 mmc0 = &usdhc1;
38 mmc1 = &usdhc2;
39 mmc2 = &usdhc3;
40 mmc3 = &usdhc4;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 spi0 = &ecspi1;
48 spi1 = &ecspi2;
49 spi2 = &ecspi3;
50 spi3 = &ecspi4;
51 spi4 = &ecspi5;
52 usb0 = &usbotg1;
53 usb1 = &usbotg2;
54 usb2 = &usbh;
55 usbphy0 = &usbphy1;
56 usbphy1 = &usbphy2;
57 };
58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 compatible = "arm,cortex-a9";
65 device_type = "cpu";
66 reg = <0>;
67 next-level-cache = <&L2>;
68 operating-points = <
69 /* kHz uV */
70 996000 1250000
71 792000 1175000
72 396000 1075000
73 198000 975000
74 >;
75 fsl,soc-operating-points = <
76 /* ARM kHz SOC uV */
77 996000 1175000
78 792000 1175000
79 396000 1175000
80 198000 1175000
81 >;
82 clock-latency = <61036>; /* two CLK32 periods */
83 #cooling-cells = <2>;
84 clocks = <&clks IMX6SX_CLK_ARM>,
85 <&clks IMX6SX_CLK_PLL2_PFD2>,
86 <&clks IMX6SX_CLK_STEP>,
87 <&clks IMX6SX_CLK_PLL1_SW>,
88 <&clks IMX6SX_CLK_PLL1_SYS>;
89 clock-names = "arm", "pll2_pfd2_396m", "step",
90 "pll1_sw", "pll1_sys";
91 arm-supply = <&reg_arm>;
92 soc-supply = <&reg_soc>;
93 nvmem-cells = <&cpu_speed_grade>;
94 nvmem-cell-names = "speed_grade";
95 };
96 };
97
98 ckil: clock-ckil {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
110 };
111
112 ipp_di0: clock-ipp-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
117 };
118
119 ipp_di1: clock-ipp-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
124 };
125
126 anaclk1: clock-anaclk1 {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 clock-output-names = "anaclk1";
131 };
132
133 anaclk2: clock-anaclk2 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <0>;
137 clock-output-names = "anaclk2";
138 };
139
140 mqs: mqs {
141 compatible = "fsl,imx6sx-mqs";
142 gpr = <&gpr>;
143 status = "disabled";
144 };
145
146 pmu {
147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>;
149 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 usbphynop1: usbphynop1 {
153 compatible = "usb-nop-xceiv";
154 #phy-cells = <0>;
155 };
156
157 soc: soc {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 interrupt-parent = <&gpc>;
162 ranges;
163
164 ocram_s: sram@8f8000 {
165 compatible = "mmio-sram";
166 reg = <0x008f8000 0x4000>;
167 ranges = <0 0x008f8000 0x4000>;
168 #address-cells = <1>;
169 #size-cells = <1>;
170 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
171 };
172
173 ocram: sram@900000 {
174 compatible = "mmio-sram";
175 reg = <0x00900000 0x20000>;
176 ranges = <0 0x00900000 0x20000>;
177 #address-cells = <1>;
178 #size-cells = <1>;
179 clocks = <&clks IMX6SX_CLK_OCRAM>;
180 };
181
182 intc: interrupt-controller@a01000 {
183 compatible = "arm,cortex-a9-gic";
184 #interrupt-cells = <3>;
185 interrupt-controller;
186 reg = <0x00a01000 0x1000>,
187 <0x00a00100 0x100>;
188 interrupt-parent = <&intc>;
189 };
190
191 L2: cache-controller@a02000 {
192 compatible = "arm,pl310-cache";
193 reg = <0x00a02000 0x1000>;
194 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
195 cache-unified;
196 cache-level = <2>;
197 arm,tag-latency = <4 2 3>;
198 arm,data-latency = <4 2 3>;
199 };
200
201 gpu: gpu@1800000 {
202 compatible = "vivante,gc";
203 reg = <0x01800000 0x4000>;
204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6SX_CLK_GPU>,
206 <&clks IMX6SX_CLK_GPU>,
207 <&clks IMX6SX_CLK_GPU>;
208 clock-names = "bus", "core", "shader";
209 power-domains = <&pd_pu>;
210 };
211
212 dma_apbh: dma-controller@1804000 {
213 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
214 reg = <0x01804000 0x2000>;
215 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
219 #dma-cells = <1>;
220 dma-channels = <4>;
221 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
222 };
223
224 gpmi: nand-controller@1806000 {
225 compatible = "fsl,imx6sx-gpmi-nand";
226 #address-cells = <1>;
227 #size-cells = <1>;
228 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
229 reg-names = "gpmi-nand", "bch";
230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "bch";
232 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
233 <&clks IMX6SX_CLK_GPMI_APB>,
234 <&clks IMX6SX_CLK_GPMI_BCH>,
235 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
236 <&clks IMX6SX_CLK_PER1_BCH>;
237 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
238 "gpmi_bch_apb", "per1_bch";
239 dmas = <&dma_apbh 0>;
240 dma-names = "rx-tx";
241 status = "disabled";
242 };
243
244 aips1: bus@2000000 {
245 compatible = "fsl,aips-bus", "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 reg = <0x02000000 0x100000>;
249 ranges;
250
251 spba-bus@2000000 {
252 compatible = "fsl,spba-bus", "simple-bus";
253 #address-cells = <1>;
254 #size-cells = <1>;
255 reg = <0x02000000 0x40000>;
256 ranges;
257
258 spdif: spdif@2004000 {
259 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
260 reg = <0x02004000 0x4000>;
261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
262 dmas = <&sdma 14 18 0>,
263 <&sdma 15 18 0>;
264 dma-names = "rx", "tx";
265 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
266 <&clks IMX6SX_CLK_OSC>,
267 <&clks IMX6SX_CLK_SPDIF>,
268 <&clks 0>, <&clks 0>, <&clks 0>,
269 <&clks IMX6SX_CLK_IPG>,
270 <&clks 0>, <&clks 0>,
271 <&clks IMX6SX_CLK_SPBA>;
272 clock-names = "core", "rxtx0",
273 "rxtx1", "rxtx2",
274 "rxtx3", "rxtx4",
275 "rxtx5", "rxtx6",
276 "rxtx7", "spba";
277 status = "disabled";
278 };
279
280 ecspi1: spi@2008000 {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
284 reg = <0x02008000 0x4000>;
285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks IMX6SX_CLK_ECSPI1>,
287 <&clks IMX6SX_CLK_ECSPI1>;
288 clock-names = "ipg", "per";
289 status = "disabled";
290 };
291
292 ecspi2: spi@200c000 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
296 reg = <0x0200c000 0x4000>;
297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clks IMX6SX_CLK_ECSPI2>,
299 <&clks IMX6SX_CLK_ECSPI2>;
300 clock-names = "ipg", "per";
301 status = "disabled";
302 };
303
304 ecspi3: spi@2010000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
308 reg = <0x02010000 0x4000>;
309 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX6SX_CLK_ECSPI3>,
311 <&clks IMX6SX_CLK_ECSPI3>;
312 clock-names = "ipg", "per";
313 status = "disabled";
314 };
315
316 ecspi4: spi@2014000 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
320 reg = <0x02014000 0x4000>;
321 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clks IMX6SX_CLK_ECSPI4>,
323 <&clks IMX6SX_CLK_ECSPI4>;
324 clock-names = "ipg", "per";
325 status = "disabled";
326 };
327
328 uart1: serial@2020000 {
329 compatible = "fsl,imx6sx-uart",
330 "fsl,imx6q-uart", "fsl,imx21-uart";
331 reg = <0x02020000 0x4000>;
332 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clks IMX6SX_CLK_UART_IPG>,
334 <&clks IMX6SX_CLK_UART_SERIAL>;
335 clock-names = "ipg", "per";
336 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
337 dma-names = "rx", "tx";
338 status = "disabled";
339 };
340
341 esai: esai@2024000 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]342 compatible = "fsl,imx35-esai";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]343 reg = <0x02024000 0x4000>;
344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]346 <&clks IMX6SX_CLK_ESAI_EXTAL>,
347 <&clks IMX6SX_CLK_ESAI_IPG>,
348 <&clks IMX6SX_CLK_SPBA>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]349 clock-names = "core", "extal",
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]350 "fsys", "spba";
351 dmas = <&sdma 23 21 0>,
352 <&sdma 24 21 0>;
353 dma-names = "rx", "tx";
354 status = "disabled";
355 };
356
357 ssi1: ssi@2028000 {
358 #sound-dai-cells = <0>;
359 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
360 reg = <0x02028000 0x4000>;
361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
363 <&clks IMX6SX_CLK_SSI1>;
364 clock-names = "ipg", "baud";
365 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
366 dma-names = "rx", "tx";
367 fsl,fifo-depth = <15>;
368 status = "disabled";
369 };
370
371 ssi2: ssi@202c000 {
372 #sound-dai-cells = <0>;
373 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
374 reg = <0x0202c000 0x4000>;
375 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
377 <&clks IMX6SX_CLK_SSI2>;
378 clock-names = "ipg", "baud";
379 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
380 dma-names = "rx", "tx";
381 fsl,fifo-depth = <15>;
382 status = "disabled";
383 };
384
385 ssi3: ssi@2030000 {
386 #sound-dai-cells = <0>;
387 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
388 reg = <0x02030000 0x4000>;
389 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
391 <&clks IMX6SX_CLK_SSI3>;
392 clock-names = "ipg", "baud";
393 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
394 dma-names = "rx", "tx";
395 fsl,fifo-depth = <15>;
396 status = "disabled";
397 };
398
399 asrc: asrc@2034000 {
400 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
401 reg = <0x02034000 0x4000>;
402 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
404 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
409 <&clks IMX6SX_CLK_SPBA>;
410 clock-names = "mem", "ipg", "asrck_0",
411 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
412 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
413 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
414 "asrck_d", "asrck_e", "asrck_f", "spba";
415 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
416 <&sdma 19 23 1>, <&sdma 20 23 1>,
417 <&sdma 21 23 1>, <&sdma 22 23 1>;
418 dma-names = "rxa", "rxb", "rxc",
419 "txa", "txb", "txc";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]420 fsl,asrc-rate = <48000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]421 fsl,asrc-width = <16>;
422 status = "okay";
423 };
424 };
425
426 pwm1: pwm@2080000 {
427 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
428 reg = <0x02080000 0x4000>;
429 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX6SX_CLK_PWM1>,
431 <&clks IMX6SX_CLK_PWM1>;
432 clock-names = "ipg", "per";
433 #pwm-cells = <3>;
434 };
435
436 pwm2: pwm@2084000 {
437 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
438 reg = <0x02084000 0x4000>;
439 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks IMX6SX_CLK_PWM2>,
441 <&clks IMX6SX_CLK_PWM2>;
442 clock-names = "ipg", "per";
443 #pwm-cells = <3>;
444 };
445
446 pwm3: pwm@2088000 {
447 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
448 reg = <0x02088000 0x4000>;
449 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6SX_CLK_PWM3>,
451 <&clks IMX6SX_CLK_PWM3>;
452 clock-names = "ipg", "per";
453 #pwm-cells = <3>;
454 };
455
456 pwm4: pwm@208c000 {
457 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
458 reg = <0x0208c000 0x4000>;
459 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clks IMX6SX_CLK_PWM4>,
461 <&clks IMX6SX_CLK_PWM4>;
462 clock-names = "ipg", "per";
463 #pwm-cells = <3>;
464 };
465
466 flexcan1: can@2090000 {
467 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
468 reg = <0x02090000 0x4000>;
469 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
471 <&clks IMX6SX_CLK_CAN1_SERIAL>;
472 clock-names = "ipg", "per";
473 fsl,stop-mode = <&gpr 0x10 1>;
474 status = "disabled";
475 };
476
477 flexcan2: can@2094000 {
478 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
479 reg = <0x02094000 0x4000>;
480 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
482 <&clks IMX6SX_CLK_CAN2_SERIAL>;
483 clock-names = "ipg", "per";
484 fsl,stop-mode = <&gpr 0x10 2>;
485 status = "disabled";
486 };
487
488 gpt: timer@2098000 {
489 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
490 reg = <0x02098000 0x4000>;
491 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
493 <&clks IMX6SX_CLK_GPT_3M>;
494 clock-names = "ipg", "per";
495 };
496
497 gpio1: gpio@209c000 {
498 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
499 reg = <0x0209c000 0x4000>;
500 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 gpio-ranges = <&iomuxc 0 5 26>;
507 };
508
509 gpio2: gpio@20a0000 {
510 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
511 reg = <0x020a0000 0x4000>;
512 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 gpio-ranges = <&iomuxc 0 31 20>;
519 };
520
521 gpio3: gpio@20a4000 {
522 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
523 reg = <0x020a4000 0x4000>;
524 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
526 gpio-controller;
527 #gpio-cells = <2>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 gpio-ranges = <&iomuxc 0 51 29>;
531 };
532
533 gpio4: gpio@20a8000 {
534 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
535 reg = <0x020a8000 0x4000>;
536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
538 gpio-controller;
539 #gpio-cells = <2>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 gpio-ranges = <&iomuxc 0 80 32>;
543 };
544
545 gpio5: gpio@20ac000 {
546 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
547 reg = <0x020ac000 0x4000>;
548 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 gpio-ranges = <&iomuxc 0 112 24>;
555 };
556
557 gpio6: gpio@20b0000 {
558 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
559 reg = <0x020b0000 0x4000>;
560 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
562 gpio-controller;
563 #gpio-cells = <2>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
567 };
568
569 gpio7: gpio@20b4000 {
570 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
571 reg = <0x020b4000 0x4000>;
572 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
578 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
579 };
580
581 kpp: keypad@20b8000 {
582 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
583 reg = <0x020b8000 0x4000>;
584 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&clks IMX6SX_CLK_IPG>;
586 status = "disabled";
587 };
588
589 wdog1: watchdog@20bc000 {
590 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
591 reg = <0x020bc000 0x4000>;
592 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clks IMX6SX_CLK_IPG>;
594 };
595
596 wdog2: watchdog@20c0000 {
597 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
598 reg = <0x020c0000 0x4000>;
599 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clks IMX6SX_CLK_IPG>;
601 status = "disabled";
602 };
603
604 clks: clock-controller@20c4000 {
605 compatible = "fsl,imx6sx-ccm";
606 reg = <0x020c4000 0x4000>;
607 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
609 #clock-cells = <1>;
610 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
611 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
612 };
613
614 anatop: anatop@20c8000 {
615 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
616 "syscon", "simple-mfd";
617 reg = <0x020c8000 0x1000>;
618 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
621
622 reg_vdd1p1: regulator-1p1 {
623 compatible = "fsl,anatop-regulator";
624 regulator-name = "vdd1p1";
625 regulator-min-microvolt = <1000000>;
626 regulator-max-microvolt = <1200000>;
627 regulator-always-on;
628 anatop-reg-offset = <0x110>;
629 anatop-vol-bit-shift = <8>;
630 anatop-vol-bit-width = <5>;
631 anatop-min-bit-val = <4>;
632 anatop-min-voltage = <800000>;
633 anatop-max-voltage = <1375000>;
634 anatop-enable-bit = <0>;
635 };
636
637 reg_vdd3p0: regulator-3p0 {
638 compatible = "fsl,anatop-regulator";
639 regulator-name = "vdd3p0";
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]640 regulator-min-microvolt = <2625000>;
641 regulator-max-microvolt = <3400000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]642 regulator-always-on;
643 anatop-reg-offset = <0x120>;
644 anatop-vol-bit-shift = <8>;
645 anatop-vol-bit-width = <5>;
646 anatop-min-bit-val = <0>;
647 anatop-min-voltage = <2625000>;
648 anatop-max-voltage = <3400000>;
649 anatop-enable-bit = <0>;
650 };
651
652 reg_vdd2p5: regulator-2p5 {
653 compatible = "fsl,anatop-regulator";
654 regulator-name = "vdd2p5";
655 regulator-min-microvolt = <2250000>;
656 regulator-max-microvolt = <2750000>;
657 regulator-always-on;
658 anatop-reg-offset = <0x130>;
659 anatop-vol-bit-shift = <8>;
660 anatop-vol-bit-width = <5>;
661 anatop-min-bit-val = <0>;
662 anatop-min-voltage = <2100000>;
663 anatop-max-voltage = <2875000>;
664 anatop-enable-bit = <0>;
665 };
666
667 reg_arm: regulator-vddcore {
668 compatible = "fsl,anatop-regulator";
669 regulator-name = "vddarm";
670 regulator-min-microvolt = <725000>;
671 regulator-max-microvolt = <1450000>;
672 regulator-always-on;
673 anatop-reg-offset = <0x140>;
674 anatop-vol-bit-shift = <0>;
675 anatop-vol-bit-width = <5>;
676 anatop-delay-reg-offset = <0x170>;
677 anatop-delay-bit-shift = <24>;
678 anatop-delay-bit-width = <2>;
679 anatop-min-bit-val = <1>;
680 anatop-min-voltage = <725000>;
681 anatop-max-voltage = <1450000>;
682 };
683
684 reg_pcie: regulator-vddpcie {
685 compatible = "fsl,anatop-regulator";
686 regulator-name = "vddpcie";
687 regulator-min-microvolt = <725000>;
688 regulator-max-microvolt = <1450000>;
689 anatop-reg-offset = <0x140>;
690 anatop-vol-bit-shift = <9>;
691 anatop-vol-bit-width = <5>;
692 anatop-delay-reg-offset = <0x170>;
693 anatop-delay-bit-shift = <26>;
694 anatop-delay-bit-width = <2>;
695 anatop-min-bit-val = <1>;
696 anatop-min-voltage = <725000>;
697 anatop-max-voltage = <1450000>;
698 };
699
700 reg_soc: regulator-vddsoc {
701 compatible = "fsl,anatop-regulator";
702 regulator-name = "vddsoc";
703 regulator-min-microvolt = <725000>;
704 regulator-max-microvolt = <1450000>;
705 regulator-always-on;
706 anatop-reg-offset = <0x140>;
707 anatop-vol-bit-shift = <18>;
708 anatop-vol-bit-width = <5>;
709 anatop-delay-reg-offset = <0x170>;
710 anatop-delay-bit-shift = <28>;
711 anatop-delay-bit-width = <2>;
712 anatop-min-bit-val = <1>;
713 anatop-min-voltage = <725000>;
714 anatop-max-voltage = <1450000>;
715 };
716
717 tempmon: tempmon {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]718 compatible = "fsl,imx6sx-tempmon";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]719 interrupt-parent = <&gpc>;
720 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
721 fsl,tempmon = <&anatop>;
722 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
723 nvmem-cell-names = "calib", "temp_grade";
724 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]725 #thermal-sensor-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]726 };
727 };
728
729 usbphy1: usbphy@20c9000 {
730 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
731 reg = <0x020c9000 0x1000>;
732 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clks IMX6SX_CLK_USBPHY1>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]734 phy-3p0-supply = <&reg_vdd3p0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]735 fsl,anatop = <&anatop>;
736 };
737
738 usbphy2: usbphy@20ca000 {
739 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
740 reg = <0x020ca000 0x1000>;
741 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&clks IMX6SX_CLK_USBPHY2>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]743 phy-3p0-supply = <&reg_vdd3p0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]744 fsl,anatop = <&anatop>;
745 };
746
747 snvs: snvs@20cc000 {
748 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
749 reg = <0x020cc000 0x4000>;
750
751 snvs_rtc: snvs-rtc-lp {
752 compatible = "fsl,sec-v4.0-mon-rtc-lp";
753 regmap = <&snvs>;
754 offset = <0x34>;
755 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
756 };
757
758 snvs_poweroff: snvs-poweroff {
759 compatible = "syscon-poweroff";
760 regmap = <&snvs>;
761 offset = <0x38>;
762 value = <0x60>;
763 mask = <0x60>;
764 status = "disabled";
765 };
766
767 snvs_pwrkey: snvs-powerkey {
768 compatible = "fsl,sec-v4.0-pwrkey";
769 regmap = <&snvs>;
770 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
771 linux,keycode = <KEY_POWER>;
772 wakeup-source;
773 status = "disabled";
774 };
775 };
776
777 epit1: epit@20d0000 {
778 reg = <0x020d0000 0x4000>;
779 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
780 };
781
782 epit2: epit@20d4000 {
783 reg = <0x020d4000 0x4000>;
784 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
785 };
786
787 src: reset-controller@20d8000 {
788 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
789 reg = <0x020d8000 0x4000>;
790 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
792 #reset-cells = <1>;
793 };
794
795 gpc: gpc@20dc000 {
796 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
797 reg = <0x020dc000 0x4000>;
798 interrupt-controller;
799 #interrupt-cells = <3>;
800 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
801 interrupt-parent = <&intc>;
802 clocks = <&clks IMX6SX_CLK_IPG>;
803 clock-names = "ipg";
804
805 pgc {
806 #address-cells = <1>;
807 #size-cells = <0>;
808
809 power-domain@0 {
810 reg = <0>;
811 #power-domain-cells = <0>;
812 };
813
814 pd_pu: power-domain@1 {
815 reg = <1>;
816 #power-domain-cells = <0>;
817 power-supply = <&reg_soc>;
818 clocks = <&clks IMX6SX_CLK_GPU>;
819 };
820
821 pd_disp: power-domain@2 {
822 reg = <2>;
823 #power-domain-cells = <0>;
824 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
825 <&clks IMX6SX_CLK_DISPLAY_AXI>,
826 <&clks IMX6SX_CLK_LCDIF1_PIX>,
827 <&clks IMX6SX_CLK_LCDIF_APB>,
828 <&clks IMX6SX_CLK_LCDIF2_PIX>,
829 <&clks IMX6SX_CLK_CSI>,
830 <&clks IMX6SX_CLK_VADC>;
831 };
832
833 pd_pci: power-domain@3 {
834 reg = <3>;
835 #power-domain-cells = <0>;
836 power-supply = <&reg_pcie>;
837 };
838 };
839 };
840
841 iomuxc: pinctrl@20e0000 {
842 compatible = "fsl,imx6sx-iomuxc";
843 reg = <0x020e0000 0x4000>;
844 };
845
846 gpr: syscon@20e4000 {
847 compatible = "fsl,imx6sx-iomuxc-gpr",
848 "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
849 #address-cells = <1>;
850 #size-cells = <1>;
851 reg = <0x020e4000 0x4000>;
852
853 lvds_bridge: bridge@18 {
854 compatible = "fsl,imx6sx-ldb";
855 reg = <0x18 0x4>;
856 clocks = <&clks IMX6SX_CLK_LDB_DI0>;
857 clock-names = "ldb";
858 status = "disabled";
859
860 ports {
861 #address-cells = <1>;
862 #size-cells = <0>;
863
864 port@0 {
865 reg = <0>;
866
867 ldb_from_lcdif1: endpoint {
868 };
869 };
870
871 port@1 {
872 reg = <1>;
873
874 ldb_lvds_ch0: endpoint {
875 };
876 };
877 };
878 };
879 };
880
881 sdma: dma-controller@20ec000 {
882 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
883 reg = <0x020ec000 0x4000>;
884 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6SX_CLK_IPG>,
886 <&clks IMX6SX_CLK_SDMA>;
887 clock-names = "ipg", "ahb";
888 #dma-cells = <3>;
889 /* imx6sx reuses imx6q sdma firmware */
890 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
891 };
892 };
893
894 aips2: bus@2100000 {
895 compatible = "fsl,aips-bus", "simple-bus";
896 #address-cells = <1>;
897 #size-cells = <1>;
898 reg = <0x02100000 0x100000>;
899 ranges;
900
901 crypto: crypto@2100000 {
902 compatible = "fsl,sec-v4.0";
903 #address-cells = <1>;
904 #size-cells = <1>;
905 reg = <0x2100000 0x10000>;
906 ranges = <0 0x2100000 0x10000>;
907 interrupt-parent = <&intc>;
908 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
909 <&clks IMX6SX_CLK_CAAM_ACLK>,
910 <&clks IMX6SX_CLK_CAAM_IPG>,
911 <&clks IMX6SX_CLK_EIM_SLOW>;
912 clock-names = "mem", "aclk", "ipg", "emi_slow";
913
914 sec_jr0: jr@1000 {
915 compatible = "fsl,sec-v4.0-job-ring";
916 reg = <0x1000 0x1000>;
917 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
918 };
919
920 sec_jr1: jr@2000 {
921 compatible = "fsl,sec-v4.0-job-ring";
922 reg = <0x2000 0x1000>;
923 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
924 };
925 };
926
927 usbotg1: usb@2184000 {
928 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
929 reg = <0x02184000 0x200>;
930 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6SX_CLK_USBOH3>;
932 fsl,usbphy = <&usbphy1>;
933 fsl,usbmisc = <&usbmisc 0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]934 ahb-burst-config = <0x0>;
935 tx-burst-size-dword = <0x10>;
936 rx-burst-size-dword = <0x10>;
937 status = "disabled";
938 };
939
940 usbotg2: usb@2184200 {
941 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
942 reg = <0x02184200 0x200>;
943 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clks IMX6SX_CLK_USBOH3>;
945 fsl,usbphy = <&usbphy2>;
946 fsl,usbmisc = <&usbmisc 1>;
947 ahb-burst-config = <0x0>;
948 tx-burst-size-dword = <0x10>;
949 rx-burst-size-dword = <0x10>;
950 status = "disabled";
951 };
952
953 usbh: usb@2184400 {
954 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
955 reg = <0x02184400 0x200>;
956 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clks IMX6SX_CLK_USBOH3>;
958 fsl,usbphy = <&usbphynop1>;
959 fsl,usbmisc = <&usbmisc 2>;
960 phy_type = "hsic";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]961 dr_mode = "host";
962 ahb-burst-config = <0x0>;
963 tx-burst-size-dword = <0x10>;
964 rx-burst-size-dword = <0x10>;
965 status = "disabled";
966 };
967
968 usbmisc: usbmisc@2184800 {
969 #index-cells = <1>;
970 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
971 reg = <0x02184800 0x200>;
972 clocks = <&clks IMX6SX_CLK_USBOH3>;
973 };
974
975 fec1: ethernet@2188000 {
976 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
977 reg = <0x02188000 0x4000>;
978 interrupt-names = "int0", "pps";
979 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clks IMX6SX_CLK_ENET>,
982 <&clks IMX6SX_CLK_ENET_AHB>,
983 <&clks IMX6SX_CLK_ENET_PTP>,
984 <&clks IMX6SX_CLK_ENET_REF>,
985 <&clks IMX6SX_CLK_ENET_PTP>;
986 clock-names = "ipg", "ahb", "ptp",
987 "enet_clk_ref", "enet_out";
988 fsl,num-tx-queues = <3>;
989 fsl,num-rx-queues = <3>;
990 fsl,stop-mode = <&gpr 0x10 3>;
991 status = "disabled";
992 };
993
994 mlb: mlb@218c000 {
995 reg = <0x0218c000 0x4000>;
996 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&clks IMX6SX_CLK_MLB>;
1000 status = "disabled";
1001 };
1002
1003 usdhc1: mmc@2190000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]1004 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1005 reg = <0x02190000 0x4000>;
1006 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&clks IMX6SX_CLK_USDHC1>,
1008 <&clks IMX6SX_CLK_USDHC1>,
1009 <&clks IMX6SX_CLK_USDHC1>;
1010 clock-names = "ipg", "ahb", "per";
1011 bus-width = <4>;
1012 fsl,tuning-start-tap = <20>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1013 fsl,tuning-step = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1014 status = "disabled";
1015 };
1016
1017 usdhc2: mmc@2194000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]1018 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1019 reg = <0x02194000 0x4000>;
1020 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX6SX_CLK_USDHC2>,
1022 <&clks IMX6SX_CLK_USDHC2>,
1023 <&clks IMX6SX_CLK_USDHC2>;
1024 clock-names = "ipg", "ahb", "per";
1025 bus-width = <4>;
1026 fsl,tuning-start-tap = <20>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1027 fsl,tuning-step = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1028 status = "disabled";
1029 };
1030
1031 usdhc3: mmc@2198000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]1032 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1033 reg = <0x02198000 0x4000>;
1034 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&clks IMX6SX_CLK_USDHC3>,
1036 <&clks IMX6SX_CLK_USDHC3>,
1037 <&clks IMX6SX_CLK_USDHC3>;
1038 clock-names = "ipg", "ahb", "per";
1039 bus-width = <4>;
1040 fsl,tuning-start-tap = <20>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1041 fsl,tuning-step = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1042 status = "disabled";
1043 };
1044
1045 usdhc4: mmc@219c000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]1046 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1047 reg = <0x0219c000 0x4000>;
1048 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&clks IMX6SX_CLK_USDHC4>,
1050 <&clks IMX6SX_CLK_USDHC4>,
1051 <&clks IMX6SX_CLK_USDHC4>;
1052 clock-names = "ipg", "ahb", "per";
1053 bus-width = <4>;
1054 status = "disabled";
1055 };
1056
1057 i2c1: i2c@21a0000 {
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1061 reg = <0x021a0000 0x4000>;
1062 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&clks IMX6SX_CLK_I2C1>;
1064 status = "disabled";
1065 };
1066
1067 i2c2: i2c@21a4000 {
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1070 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1071 reg = <0x021a4000 0x4000>;
1072 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clks IMX6SX_CLK_I2C2>;
1074 status = "disabled";
1075 };
1076
1077 i2c3: i2c@21a8000 {
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1080 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1081 reg = <0x021a8000 0x4000>;
1082 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&clks IMX6SX_CLK_I2C3>;
1084 status = "disabled";
1085 };
1086
1087 memory-controller@21b0000 {
1088 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1089 reg = <0x021b0000 0x4000>;
1090 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1091 };
1092
1093 fec2: ethernet@21b4000 {
1094 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1095 reg = <0x021b4000 0x4000>;
1096 interrupt-names = "int0", "pps";
1097 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&clks IMX6SX_CLK_ENET>,
1100 <&clks IMX6SX_CLK_ENET_AHB>,
1101 <&clks IMX6SX_CLK_ENET_PTP>,
1102 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1103 <&clks IMX6SX_CLK_ENET_PTP>;
1104 clock-names = "ipg", "ahb", "ptp",
1105 "enet_clk_ref", "enet_out";
1106 fsl,stop-mode = <&gpr 0x10 4>;
1107 status = "disabled";
1108 };
1109
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1110 weim: memory-controller@21b8000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1111 #address-cells = <2>;
1112 #size-cells = <1>;
1113 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1114 reg = <0x021b8000 0x4000>;
1115 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1117 fsl,weim-cs-gpr = <&gpr>;
1118 status = "disabled";
1119 };
1120
1121 ocotp: efuse@21bc000 {
1122 #address-cells = <1>;
1123 #size-cells = <1>;
1124 compatible = "fsl,imx6sx-ocotp", "syscon";
1125 reg = <0x021bc000 0x4000>;
1126 clocks = <&clks IMX6SX_CLK_OCOTP>;
1127
1128 cpu_speed_grade: speed-grade@10 {
1129 reg = <0x10 4>;
1130 };
1131
1132 tempmon_calib: calib@38 {
1133 reg = <0x38 4>;
1134 };
1135
1136 tempmon_temp_grade: temp-grade@20 {
1137 reg = <0x20 4>;
1138 };
1139 };
1140
1141 sai1: sai@21d4000 {
1142 compatible = "fsl,imx6sx-sai";
1143 reg = <0x021d4000 0x4000>;
1144 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1146 <&clks IMX6SX_CLK_SAI1>,
1147 <&clks 0>, <&clks 0>;
1148 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1149 dma-names = "rx", "tx";
1150 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1151 status = "disabled";
1152 };
1153
1154 audmux: audmux@21d8000 {
1155 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1156 reg = <0x021d8000 0x4000>;
1157 status = "disabled";
1158 };
1159
1160 sai2: sai@21dc000 {
1161 compatible = "fsl,imx6sx-sai";
1162 reg = <0x021dc000 0x4000>;
1163 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1165 <&clks IMX6SX_CLK_SAI2>,
1166 <&clks 0>, <&clks 0>;
1167 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1168 dma-names = "rx", "tx";
1169 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1170 status = "disabled";
1171 };
1172
1173 qspi1: spi@21e0000 {
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 compatible = "fsl,imx6sx-qspi";
1177 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1178 reg-names = "QuadSPI", "QuadSPI-memory";
1179 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&clks IMX6SX_CLK_QSPI1>,
1181 <&clks IMX6SX_CLK_QSPI1>;
1182 clock-names = "qspi_en", "qspi";
1183 status = "disabled";
1184 };
1185
1186 qspi2: spi@21e4000 {
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 compatible = "fsl,imx6sx-qspi";
1190 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1191 reg-names = "QuadSPI", "QuadSPI-memory";
1192 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_QSPI2>,
1194 <&clks IMX6SX_CLK_QSPI2>;
1195 clock-names = "qspi_en", "qspi";
1196 status = "disabled";
1197 };
1198
1199 uart2: serial@21e8000 {
1200 compatible = "fsl,imx6sx-uart",
1201 "fsl,imx6q-uart", "fsl,imx21-uart";
1202 reg = <0x021e8000 0x4000>;
1203 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1205 <&clks IMX6SX_CLK_UART_SERIAL>;
1206 clock-names = "ipg", "per";
1207 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1208 dma-names = "rx", "tx";
1209 status = "disabled";
1210 };
1211
1212 uart3: serial@21ec000 {
1213 compatible = "fsl,imx6sx-uart",
1214 "fsl,imx6q-uart", "fsl,imx21-uart";
1215 reg = <0x021ec000 0x4000>;
1216 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1218 <&clks IMX6SX_CLK_UART_SERIAL>;
1219 clock-names = "ipg", "per";
1220 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1221 dma-names = "rx", "tx";
1222 status = "disabled";
1223 };
1224
1225 uart4: serial@21f0000 {
1226 compatible = "fsl,imx6sx-uart",
1227 "fsl,imx6q-uart", "fsl,imx21-uart";
1228 reg = <0x021f0000 0x4000>;
1229 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1231 <&clks IMX6SX_CLK_UART_SERIAL>;
1232 clock-names = "ipg", "per";
1233 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1234 dma-names = "rx", "tx";
1235 status = "disabled";
1236 };
1237
1238 uart5: serial@21f4000 {
1239 compatible = "fsl,imx6sx-uart",
1240 "fsl,imx6q-uart", "fsl,imx21-uart";
1241 reg = <0x021f4000 0x4000>;
1242 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1244 <&clks IMX6SX_CLK_UART_SERIAL>;
1245 clock-names = "ipg", "per";
1246 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1247 dma-names = "rx", "tx";
1248 status = "disabled";
1249 };
1250
1251 i2c4: i2c@21f8000 {
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1255 reg = <0x021f8000 0x4000>;
1256 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clks IMX6SX_CLK_I2C4>;
1258 status = "disabled";
1259 };
1260 };
1261
1262 aips3: bus@2200000 {
1263 compatible = "fsl,aips-bus", "simple-bus";
1264 #address-cells = <1>;
1265 #size-cells = <1>;
1266 reg = <0x02200000 0x100000>;
1267 ranges;
1268
1269 spba-bus@2240000 {
1270 compatible = "fsl,spba-bus", "simple-bus";
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1273 reg = <0x02240000 0x40000>;
1274 ranges;
1275
1276 csi1: csi@2214000 {
1277 reg = <0x02214000 0x4000>;
1278 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1280 <&clks IMX6SX_CLK_CSI>,
1281 <&clks IMX6SX_CLK_DCIC1>;
1282 clock-names = "disp-axi", "csi_mclk", "dcic";
1283 status = "disabled";
1284 };
1285
1286 pxp: pxp@2218000 {
1287 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1288 reg = <0x02218000 0x4000>;
1289 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1290 clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1291 clock-names = "axi";
1292 power-domains = <&pd_disp>;
1293 status = "disabled";
1294 };
1295
1296 csi2: csi@221c000 {
1297 reg = <0x0221c000 0x4000>;
1298 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1300 <&clks IMX6SX_CLK_CSI>,
1301 <&clks IMX6SX_CLK_DCIC2>;
1302 clock-names = "disp-axi", "csi_mclk", "dcic";
1303 status = "disabled";
1304 };
1305
1306 lcdif1: lcdif@2220000 {
1307 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1308 reg = <0x02220000 0x4000>;
1309 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1310 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1311 <&clks IMX6SX_CLK_LCDIF_APB>,
1312 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1313 clock-names = "pix", "axi", "disp_axi";
1314 assigned-clocks = <&clks IMX6SX_CLK_LCDIF1_PRE_SEL>,
1315 <&clks IMX6SX_CLK_LCDIF1_SEL>;
1316 assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>,
1317 <&clks IMX6SX_CLK_LCDIF1_PODF>;
1318 power-domains = <&pd_disp>;
1319 status = "disabled";
1320
1321 port {
1322 lcdif1_to_ldb: endpoint {
1323 };
1324 };
1325 };
1326
1327 lcdif2: lcdif@2224000 {
1328 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1329 reg = <0x02224000 0x4000>;
1330 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1331 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1332 <&clks IMX6SX_CLK_LCDIF_APB>,
1333 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1334 clock-names = "pix", "axi", "disp_axi";
1335 power-domains = <&pd_disp>;
1336 status = "disabled";
1337 };
1338
1339 vadc: vadc@2228000 {
1340 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1341 reg-names = "vadc-vafe", "vadc-vdec";
1342 clocks = <&clks IMX6SX_CLK_VADC>,
1343 <&clks IMX6SX_CLK_CSI>;
1344 clock-names = "vadc", "csi";
1345 power-domains = <&pd_disp>;
1346 status = "disabled";
1347 };
1348 };
1349
1350 adc1: adc@2280000 {
1351 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1352 reg = <0x02280000 0x4000>;
1353 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1354 clocks = <&clks IMX6SX_CLK_IPG>;
1355 clock-names = "adc";
1356 fsl,adck-max-frequency = <30000000>, <40000000>,
1357 <20000000>;
1358 status = "disabled";
1359 };
1360
1361 adc2: adc@2284000 {
1362 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1363 reg = <0x02284000 0x4000>;
1364 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1365 clocks = <&clks IMX6SX_CLK_IPG>;
1366 clock-names = "adc";
1367 fsl,adck-max-frequency = <30000000>, <40000000>,
1368 <20000000>;
1369 status = "disabled";
1370 };
1371
1372 wdog3: watchdog@2288000 {
1373 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1374 reg = <0x02288000 0x4000>;
1375 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1376 clocks = <&clks IMX6SX_CLK_IPG>;
1377 status = "disabled";
1378 };
1379
1380 ecspi5: spi@228c000 {
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1383 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1384 reg = <0x0228c000 0x4000>;
1385 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1387 <&clks IMX6SX_CLK_ECSPI5>;
1388 clock-names = "ipg", "per";
1389 status = "disabled";
1390 };
1391
1392 uart6: serial@22a0000 {
1393 compatible = "fsl,imx6sx-uart",
1394 "fsl,imx6q-uart", "fsl,imx21-uart";
1395 reg = <0x022a0000 0x4000>;
1396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1398 <&clks IMX6SX_CLK_UART_SERIAL>;
1399 clock-names = "ipg", "per";
1400 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1401 dma-names = "rx", "tx";
1402 status = "disabled";
1403 };
1404
1405 pwm5: pwm@22a4000 {
1406 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1407 reg = <0x022a4000 0x4000>;
1408 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&clks IMX6SX_CLK_PWM5>,
1410 <&clks IMX6SX_CLK_PWM5>;
1411 clock-names = "ipg", "per";
1412 #pwm-cells = <3>;
1413 };
1414
1415 pwm6: pwm@22a8000 {
1416 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1417 reg = <0x022a8000 0x4000>;
1418 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&clks IMX6SX_CLK_PWM6>,
1420 <&clks IMX6SX_CLK_PWM6>;
1421 clock-names = "ipg", "per";
1422 #pwm-cells = <3>;
1423 };
1424
1425 pwm7: pwm@22ac000 {
1426 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1427 reg = <0x022ac000 0x4000>;
1428 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&clks IMX6SX_CLK_PWM7>,
1430 <&clks IMX6SX_CLK_PWM7>;
1431 clock-names = "ipg", "per";
1432 #pwm-cells = <3>;
1433 };
1434
1435 pwm8: pwm@22b0000 {
1436 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1437 reg = <0x022b0000 0x4000>;
1438 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1439 clocks = <&clks IMX6SX_CLK_PWM8>,
1440 <&clks IMX6SX_CLK_PWM8>;
1441 clock-names = "ipg", "per";
1442 #pwm-cells = <3>;
1443 };
1444 };
1445
1446 pcie: pcie@8ffc000 {
1447 compatible = "fsl,imx6sx-pcie";
1448 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1449 reg-names = "dbi", "config";
1450 #address-cells = <3>;
1451 #size-cells = <2>;
1452 device_type = "pci";
1453 bus-range = <0x00 0xff>;
1454 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1455 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1456 num-lanes = <1>;
1457 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1458 interrupt-names = "msi";
1459 #interrupt-cells = <1>;
1460 interrupt-map-mask = <0 0 0 0x7>;
1461 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1462 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1463 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1464 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1465 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1466 <&clks IMX6SX_CLK_LVDS1_OUT>,
1467 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1468 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1469 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1470 power-domains = <&pd_disp>, <&pd_pci>;
1471 power-domain-names = "pcie", "pcie_phy";
1472 status = "disabled";
1473 };
1474 };
1475};