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git01.mediatek.com / filogic / uboot / 844493d7e99cb795f3e28130ee09ba7a6441162f / . / src / arm / nxp / imx / imx6sx.dtsi
blob: a9550f115f82699336f62c33214c9a9bb04e79e0 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2014 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/clock/imx6sx-clock.h>
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx6sx-pinfunc.h"
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 */
19 chosen {};
20
21 aliases {
22 can0 = &flexcan1;
23 can1 = &flexcan2;
24 ethernet0 = &fec1;
25 ethernet1 = &fec2;
26 gpio0 = &gpio1;
27 gpio1 = &gpio2;
28 gpio2 = &gpio3;
29 gpio3 = &gpio4;
30 gpio4 = &gpio5;
31 gpio5 = &gpio6;
32 gpio6 = &gpio7;
33 i2c0 = &i2c1;
34 i2c1 = &i2c2;
35 i2c2 = &i2c3;
36 i2c3 = &i2c4;
37 mmc0 = &usdhc1;
38 mmc1 = &usdhc2;
39 mmc2 = &usdhc3;
40 mmc3 = &usdhc4;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 spi0 = &ecspi1;
48 spi1 = &ecspi2;
49 spi2 = &ecspi3;
50 spi3 = &ecspi4;
51 spi4 = &ecspi5;
52 usb0 = &usbotg1;
53 usb1 = &usbotg2;
54 usb2 = &usbh;
55 usbphy0 = &usbphy1;
56 usbphy1 = &usbphy2;
57 };
58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 compatible = "arm,cortex-a9";
65 device_type = "cpu";
66 reg = <0>;
67 next-level-cache = <&L2>;
68 operating-points = <
69 /* kHz uV */
70 996000 1250000
71 792000 1175000
72 396000 1075000
73 198000 975000
74 >;
75 fsl,soc-operating-points = <
76 /* ARM kHz SOC uV */
77 996000 1175000
78 792000 1175000
79 396000 1175000
80 198000 1175000
81 >;
82 clock-latency = <61036>; /* two CLK32 periods */
83 #cooling-cells = <2>;
84 clocks = <&clks IMX6SX_CLK_ARM>,
85 <&clks IMX6SX_CLK_PLL2_PFD2>,
86 <&clks IMX6SX_CLK_STEP>,
87 <&clks IMX6SX_CLK_PLL1_SW>,
88 <&clks IMX6SX_CLK_PLL1_SYS>;
89 clock-names = "arm", "pll2_pfd2_396m", "step",
90 "pll1_sw", "pll1_sys";
91 arm-supply = <&reg_arm>;
92 soc-supply = <&reg_soc>;
93 nvmem-cells = <&cpu_speed_grade>;
94 nvmem-cell-names = "speed_grade";
95 };
96 };
97
98 ckil: clock-ckil {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
110 };
111
112 ipp_di0: clock-ipp-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
117 };
118
119 ipp_di1: clock-ipp-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
124 };
125
126 anaclk1: clock-anaclk1 {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 clock-output-names = "anaclk1";
131 };
132
133 anaclk2: clock-anaclk2 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <0>;
137 clock-output-names = "anaclk2";
138 };
139
140 mqs: mqs {
141 compatible = "fsl,imx6sx-mqs";
142 gpr = <&gpr>;
143 status = "disabled";
144 };
145
146 pmu {
147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>;
149 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 usbphynop1: usbphynop1 {
153 compatible = "usb-nop-xceiv";
154 #phy-cells = <0>;
155 };
156
157 soc: soc {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 interrupt-parent = <&gpc>;
162 ranges;
163
164 ocram_s: sram@8f8000 {
165 compatible = "mmio-sram";
166 reg = <0x008f8000 0x4000>;
167 ranges = <0 0x008f8000 0x4000>;
168 #address-cells = <1>;
169 #size-cells = <1>;
170 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
171 };
172
173 ocram: sram@900000 {
174 compatible = "mmio-sram";
175 reg = <0x00900000 0x20000>;
176 ranges = <0 0x00900000 0x20000>;
177 #address-cells = <1>;
178 #size-cells = <1>;
179 clocks = <&clks IMX6SX_CLK_OCRAM>;
180 };
181
182 intc: interrupt-controller@a01000 {
183 compatible = "arm,cortex-a9-gic";
184 #interrupt-cells = <3>;
185 interrupt-controller;
186 reg = <0x00a01000 0x1000>,
187 <0x00a00100 0x100>;
188 interrupt-parent = <&intc>;
189 };
190
191 L2: cache-controller@a02000 {
192 compatible = "arm,pl310-cache";
193 reg = <0x00a02000 0x1000>;
194 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
195 cache-unified;
196 cache-level = <2>;
197 arm,tag-latency = <4 2 3>;
198 arm,data-latency = <4 2 3>;
199 };
200
201 gpu: gpu@1800000 {
202 compatible = "vivante,gc";
203 reg = <0x01800000 0x4000>;
204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6SX_CLK_GPU>,
206 <&clks IMX6SX_CLK_GPU>,
207 <&clks IMX6SX_CLK_GPU>;
208 clock-names = "bus", "core", "shader";
209 power-domains = <&pd_pu>;
210 };
211
212 dma_apbh: dma-controller@1804000 {
213 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
214 reg = <0x01804000 0x2000>;
215 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
219 #dma-cells = <1>;
220 dma-channels = <4>;
221 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
222 };
223
224 gpmi: nand-controller@1806000 {
225 compatible = "fsl,imx6sx-gpmi-nand";
226 #address-cells = <1>;
227 #size-cells = <1>;
228 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
229 reg-names = "gpmi-nand", "bch";
230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "bch";
232 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
233 <&clks IMX6SX_CLK_GPMI_APB>,
234 <&clks IMX6SX_CLK_GPMI_BCH>,
235 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
236 <&clks IMX6SX_CLK_PER1_BCH>;
237 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
238 "gpmi_bch_apb", "per1_bch";
239 dmas = <&dma_apbh 0>;
240 dma-names = "rx-tx";
241 status = "disabled";
242 };
243
244 aips1: bus@2000000 {
245 compatible = "fsl,aips-bus", "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 reg = <0x02000000 0x100000>;
249 ranges;
250
251 spba-bus@2000000 {
252 compatible = "fsl,spba-bus", "simple-bus";
253 #address-cells = <1>;
254 #size-cells = <1>;
255 reg = <0x02000000 0x40000>;
256 ranges;
257
258 spdif: spdif@2004000 {
259 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
260 reg = <0x02004000 0x4000>;
261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
262 dmas = <&sdma 14 18 0>,
263 <&sdma 15 18 0>;
264 dma-names = "rx", "tx";
265 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
266 <&clks IMX6SX_CLK_OSC>,
267 <&clks IMX6SX_CLK_SPDIF>,
268 <&clks 0>, <&clks 0>, <&clks 0>,
269 <&clks IMX6SX_CLK_IPG>,
270 <&clks 0>, <&clks 0>,
271 <&clks IMX6SX_CLK_SPBA>;
272 clock-names = "core", "rxtx0",
273 "rxtx1", "rxtx2",
274 "rxtx3", "rxtx4",
275 "rxtx5", "rxtx6",
276 "rxtx7", "spba";
277 status = "disabled";
278 };
279
280 ecspi1: spi@2008000 {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
284 reg = <0x02008000 0x4000>;
285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks IMX6SX_CLK_ECSPI1>,
287 <&clks IMX6SX_CLK_ECSPI1>;
288 clock-names = "ipg", "per";
289 status = "disabled";
290 };
291
292 ecspi2: spi@200c000 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
296 reg = <0x0200c000 0x4000>;
297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clks IMX6SX_CLK_ECSPI2>,
299 <&clks IMX6SX_CLK_ECSPI2>;
300 clock-names = "ipg", "per";
301 status = "disabled";
302 };
303
304 ecspi3: spi@2010000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
308 reg = <0x02010000 0x4000>;
309 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX6SX_CLK_ECSPI3>,
311 <&clks IMX6SX_CLK_ECSPI3>;
312 clock-names = "ipg", "per";
313 status = "disabled";
314 };
315
316 ecspi4: spi@2014000 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
320 reg = <0x02014000 0x4000>;
321 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clks IMX6SX_CLK_ECSPI4>,
323 <&clks IMX6SX_CLK_ECSPI4>;
324 clock-names = "ipg", "per";
325 status = "disabled";
326 };
327
328 uart1: serial@2020000 {
329 compatible = "fsl,imx6sx-uart",
330 "fsl,imx6q-uart", "fsl,imx21-uart";
331 reg = <0x02020000 0x4000>;
332 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clks IMX6SX_CLK_UART_IPG>,
334 <&clks IMX6SX_CLK_UART_SERIAL>;
335 clock-names = "ipg", "per";
336 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
337 dma-names = "rx", "tx";
338 status = "disabled";
339 };
340
341 esai: esai@2024000 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]342 compatible = "fsl,imx35-esai";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]343 reg = <0x02024000 0x4000>;
344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]346 <&clks IMX6SX_CLK_ESAI_EXTAL>,
347 <&clks IMX6SX_CLK_ESAI_IPG>,
348 <&clks IMX6SX_CLK_SPBA>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]349 clock-names = "core", "extal",
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]350 "fsys", "spba";
351 dmas = <&sdma 23 21 0>,
352 <&sdma 24 21 0>;
353 dma-names = "rx", "tx";
354 status = "disabled";
355 };
356
357 ssi1: ssi@2028000 {
358 #sound-dai-cells = <0>;
359 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
360 reg = <0x02028000 0x4000>;
361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
363 <&clks IMX6SX_CLK_SSI1>;
364 clock-names = "ipg", "baud";
365 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
366 dma-names = "rx", "tx";
367 fsl,fifo-depth = <15>;
368 status = "disabled";
369 };
370
371 ssi2: ssi@202c000 {
372 #sound-dai-cells = <0>;
373 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
374 reg = <0x0202c000 0x4000>;
375 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
377 <&clks IMX6SX_CLK_SSI2>;
378 clock-names = "ipg", "baud";
379 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
380 dma-names = "rx", "tx";
381 fsl,fifo-depth = <15>;
382 status = "disabled";
383 };
384
385 ssi3: ssi@2030000 {
386 #sound-dai-cells = <0>;
387 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
388 reg = <0x02030000 0x4000>;
389 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
391 <&clks IMX6SX_CLK_SSI3>;
392 clock-names = "ipg", "baud";
393 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
394 dma-names = "rx", "tx";
395 fsl,fifo-depth = <15>;
396 status = "disabled";
397 };
398
399 asrc: asrc@2034000 {
400 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
401 reg = <0x02034000 0x4000>;
402 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
404 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
409 <&clks IMX6SX_CLK_SPBA>;
410 clock-names = "mem", "ipg", "asrck_0",
411 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
412 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
413 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
414 "asrck_d", "asrck_e", "asrck_f", "spba";
415 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
416 <&sdma 19 23 1>, <&sdma 20 23 1>,
417 <&sdma 21 23 1>, <&sdma 22 23 1>;
418 dma-names = "rxa", "rxb", "rxc",
419 "txa", "txb", "txc";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]420 fsl,asrc-rate = <48000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]421 fsl,asrc-width = <16>;
422 status = "okay";
423 };
424 };
425
426 pwm1: pwm@2080000 {
427 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
428 reg = <0x02080000 0x4000>;
429 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX6SX_CLK_PWM1>,
431 <&clks IMX6SX_CLK_PWM1>;
432 clock-names = "ipg", "per";
433 #pwm-cells = <3>;
434 };
435
436 pwm2: pwm@2084000 {
437 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
438 reg = <0x02084000 0x4000>;
439 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks IMX6SX_CLK_PWM2>,
441 <&clks IMX6SX_CLK_PWM2>;
442 clock-names = "ipg", "per";
443 #pwm-cells = <3>;
444 };
445
446 pwm3: pwm@2088000 {
447 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
448 reg = <0x02088000 0x4000>;
449 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6SX_CLK_PWM3>,
451 <&clks IMX6SX_CLK_PWM3>;
452 clock-names = "ipg", "per";
453 #pwm-cells = <3>;
454 };
455
456 pwm4: pwm@208c000 {
457 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
458 reg = <0x0208c000 0x4000>;
459 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clks IMX6SX_CLK_PWM4>,
461 <&clks IMX6SX_CLK_PWM4>;
462 clock-names = "ipg", "per";
463 #pwm-cells = <3>;
464 };
465
466 flexcan1: can@2090000 {
467 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
468 reg = <0x02090000 0x4000>;
469 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
471 <&clks IMX6SX_CLK_CAN1_SERIAL>;
472 clock-names = "ipg", "per";
473 fsl,stop-mode = <&gpr 0x10 1>;
474 status = "disabled";
475 };
476
477 flexcan2: can@2094000 {
478 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
479 reg = <0x02094000 0x4000>;
480 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
482 <&clks IMX6SX_CLK_CAN2_SERIAL>;
483 clock-names = "ipg", "per";
484 fsl,stop-mode = <&gpr 0x10 2>;
485 status = "disabled";
486 };
487
488 gpt: timer@2098000 {
489 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
490 reg = <0x02098000 0x4000>;
491 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
493 <&clks IMX6SX_CLK_GPT_3M>;
494 clock-names = "ipg", "per";
495 };
496
497 gpio1: gpio@209c000 {
498 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
499 reg = <0x0209c000 0x4000>;
500 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 gpio-ranges = <&iomuxc 0 5 26>;
507 };
508
509 gpio2: gpio@20a0000 {
510 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
511 reg = <0x020a0000 0x4000>;
512 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 gpio-ranges = <&iomuxc 0 31 20>;
519 };
520
521 gpio3: gpio@20a4000 {
522 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
523 reg = <0x020a4000 0x4000>;
524 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
526 gpio-controller;
527 #gpio-cells = <2>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 gpio-ranges = <&iomuxc 0 51 29>;
531 };
532
533 gpio4: gpio@20a8000 {
534 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
535 reg = <0x020a8000 0x4000>;
536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
538 gpio-controller;
539 #gpio-cells = <2>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 gpio-ranges = <&iomuxc 0 80 32>;
543 };
544
545 gpio5: gpio@20ac000 {
546 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
547 reg = <0x020ac000 0x4000>;
548 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 gpio-ranges = <&iomuxc 0 112 24>;
555 };
556
557 gpio6: gpio@20b0000 {
558 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
559 reg = <0x020b0000 0x4000>;
560 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
562 gpio-controller;
563 #gpio-cells = <2>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
567 };
568
569 gpio7: gpio@20b4000 {
570 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
571 reg = <0x020b4000 0x4000>;
572 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
578 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
579 };
580
581 kpp: keypad@20b8000 {
582 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
583 reg = <0x020b8000 0x4000>;
584 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&clks IMX6SX_CLK_IPG>;
586 status = "disabled";
587 };
588
589 wdog1: watchdog@20bc000 {
590 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
591 reg = <0x020bc000 0x4000>;
592 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clks IMX6SX_CLK_IPG>;
594 };
595
596 wdog2: watchdog@20c0000 {
597 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
598 reg = <0x020c0000 0x4000>;
599 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clks IMX6SX_CLK_IPG>;
601 status = "disabled";
602 };
603
604 clks: clock-controller@20c4000 {
605 compatible = "fsl,imx6sx-ccm";
606 reg = <0x020c4000 0x4000>;
607 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
609 #clock-cells = <1>;
610 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
611 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
612 };
613
614 anatop: anatop@20c8000 {
615 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
616 "syscon", "simple-mfd";
617 reg = <0x020c8000 0x1000>;
618 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
621
622 reg_vdd1p1: regulator-1p1 {
623 compatible = "fsl,anatop-regulator";
624 regulator-name = "vdd1p1";
625 regulator-min-microvolt = <1000000>;
626 regulator-max-microvolt = <1200000>;
627 regulator-always-on;
628 anatop-reg-offset = <0x110>;
629 anatop-vol-bit-shift = <8>;
630 anatop-vol-bit-width = <5>;
631 anatop-min-bit-val = <4>;
632 anatop-min-voltage = <800000>;
633 anatop-max-voltage = <1375000>;
634 anatop-enable-bit = <0>;
635 };
636
637 reg_vdd3p0: regulator-3p0 {
638 compatible = "fsl,anatop-regulator";
639 regulator-name = "vdd3p0";
640 regulator-min-microvolt = <2800000>;
641 regulator-max-microvolt = <3150000>;
642 regulator-always-on;
643 anatop-reg-offset = <0x120>;
644 anatop-vol-bit-shift = <8>;
645 anatop-vol-bit-width = <5>;
646 anatop-min-bit-val = <0>;
647 anatop-min-voltage = <2625000>;
648 anatop-max-voltage = <3400000>;
649 anatop-enable-bit = <0>;
650 };
651
652 reg_vdd2p5: regulator-2p5 {
653 compatible = "fsl,anatop-regulator";
654 regulator-name = "vdd2p5";
655 regulator-min-microvolt = <2250000>;
656 regulator-max-microvolt = <2750000>;
657 regulator-always-on;
658 anatop-reg-offset = <0x130>;
659 anatop-vol-bit-shift = <8>;
660 anatop-vol-bit-width = <5>;
661 anatop-min-bit-val = <0>;
662 anatop-min-voltage = <2100000>;
663 anatop-max-voltage = <2875000>;
664 anatop-enable-bit = <0>;
665 };
666
667 reg_arm: regulator-vddcore {
668 compatible = "fsl,anatop-regulator";
669 regulator-name = "vddarm";
670 regulator-min-microvolt = <725000>;
671 regulator-max-microvolt = <1450000>;
672 regulator-always-on;
673 anatop-reg-offset = <0x140>;
674 anatop-vol-bit-shift = <0>;
675 anatop-vol-bit-width = <5>;
676 anatop-delay-reg-offset = <0x170>;
677 anatop-delay-bit-shift = <24>;
678 anatop-delay-bit-width = <2>;
679 anatop-min-bit-val = <1>;
680 anatop-min-voltage = <725000>;
681 anatop-max-voltage = <1450000>;
682 };
683
684 reg_pcie: regulator-vddpcie {
685 compatible = "fsl,anatop-regulator";
686 regulator-name = "vddpcie";
687 regulator-min-microvolt = <725000>;
688 regulator-max-microvolt = <1450000>;
689 anatop-reg-offset = <0x140>;
690 anatop-vol-bit-shift = <9>;
691 anatop-vol-bit-width = <5>;
692 anatop-delay-reg-offset = <0x170>;
693 anatop-delay-bit-shift = <26>;
694 anatop-delay-bit-width = <2>;
695 anatop-min-bit-val = <1>;
696 anatop-min-voltage = <725000>;
697 anatop-max-voltage = <1450000>;
698 };
699
700 reg_soc: regulator-vddsoc {
701 compatible = "fsl,anatop-regulator";
702 regulator-name = "vddsoc";
703 regulator-min-microvolt = <725000>;
704 regulator-max-microvolt = <1450000>;
705 regulator-always-on;
706 anatop-reg-offset = <0x140>;
707 anatop-vol-bit-shift = <18>;
708 anatop-vol-bit-width = <5>;
709 anatop-delay-reg-offset = <0x170>;
710 anatop-delay-bit-shift = <28>;
711 anatop-delay-bit-width = <2>;
712 anatop-min-bit-val = <1>;
713 anatop-min-voltage = <725000>;
714 anatop-max-voltage = <1450000>;
715 };
716
717 tempmon: tempmon {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]718 compatible = "fsl,imx6sx-tempmon";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]719 interrupt-parent = <&gpc>;
720 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
721 fsl,tempmon = <&anatop>;
722 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
723 nvmem-cell-names = "calib", "temp_grade";
724 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]725 #thermal-sensor-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]726 };
727 };
728
729 usbphy1: usbphy@20c9000 {
730 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
731 reg = <0x020c9000 0x1000>;
732 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clks IMX6SX_CLK_USBPHY1>;
734 fsl,anatop = <&anatop>;
735 };
736
737 usbphy2: usbphy@20ca000 {
738 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
739 reg = <0x020ca000 0x1000>;
740 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clks IMX6SX_CLK_USBPHY2>;
742 fsl,anatop = <&anatop>;
743 };
744
745 snvs: snvs@20cc000 {
746 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
747 reg = <0x020cc000 0x4000>;
748
749 snvs_rtc: snvs-rtc-lp {
750 compatible = "fsl,sec-v4.0-mon-rtc-lp";
751 regmap = <&snvs>;
752 offset = <0x34>;
753 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
754 };
755
756 snvs_poweroff: snvs-poweroff {
757 compatible = "syscon-poweroff";
758 regmap = <&snvs>;
759 offset = <0x38>;
760 value = <0x60>;
761 mask = <0x60>;
762 status = "disabled";
763 };
764
765 snvs_pwrkey: snvs-powerkey {
766 compatible = "fsl,sec-v4.0-pwrkey";
767 regmap = <&snvs>;
768 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
769 linux,keycode = <KEY_POWER>;
770 wakeup-source;
771 status = "disabled";
772 };
773 };
774
775 epit1: epit@20d0000 {
776 reg = <0x020d0000 0x4000>;
777 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
778 };
779
780 epit2: epit@20d4000 {
781 reg = <0x020d4000 0x4000>;
782 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
783 };
784
785 src: reset-controller@20d8000 {
786 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
787 reg = <0x020d8000 0x4000>;
788 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
790 #reset-cells = <1>;
791 };
792
793 gpc: gpc@20dc000 {
794 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
795 reg = <0x020dc000 0x4000>;
796 interrupt-controller;
797 #interrupt-cells = <3>;
798 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
799 interrupt-parent = <&intc>;
800 clocks = <&clks IMX6SX_CLK_IPG>;
801 clock-names = "ipg";
802
803 pgc {
804 #address-cells = <1>;
805 #size-cells = <0>;
806
807 power-domain@0 {
808 reg = <0>;
809 #power-domain-cells = <0>;
810 };
811
812 pd_pu: power-domain@1 {
813 reg = <1>;
814 #power-domain-cells = <0>;
815 power-supply = <&reg_soc>;
816 clocks = <&clks IMX6SX_CLK_GPU>;
817 };
818
819 pd_disp: power-domain@2 {
820 reg = <2>;
821 #power-domain-cells = <0>;
822 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
823 <&clks IMX6SX_CLK_DISPLAY_AXI>,
824 <&clks IMX6SX_CLK_LCDIF1_PIX>,
825 <&clks IMX6SX_CLK_LCDIF_APB>,
826 <&clks IMX6SX_CLK_LCDIF2_PIX>,
827 <&clks IMX6SX_CLK_CSI>,
828 <&clks IMX6SX_CLK_VADC>;
829 };
830
831 pd_pci: power-domain@3 {
832 reg = <3>;
833 #power-domain-cells = <0>;
834 power-supply = <&reg_pcie>;
835 };
836 };
837 };
838
839 iomuxc: pinctrl@20e0000 {
840 compatible = "fsl,imx6sx-iomuxc";
841 reg = <0x020e0000 0x4000>;
842 };
843
844 gpr: syscon@20e4000 {
845 compatible = "fsl,imx6sx-iomuxc-gpr",
846 "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
847 #address-cells = <1>;
848 #size-cells = <1>;
849 reg = <0x020e4000 0x4000>;
850
851 lvds_bridge: bridge@18 {
852 compatible = "fsl,imx6sx-ldb";
853 reg = <0x18 0x4>;
854 clocks = <&clks IMX6SX_CLK_LDB_DI0>;
855 clock-names = "ldb";
856 status = "disabled";
857
858 ports {
859 #address-cells = <1>;
860 #size-cells = <0>;
861
862 port@0 {
863 reg = <0>;
864
865 ldb_from_lcdif1: endpoint {
866 };
867 };
868
869 port@1 {
870 reg = <1>;
871
872 ldb_lvds_ch0: endpoint {
873 };
874 };
875 };
876 };
877 };
878
879 sdma: dma-controller@20ec000 {
880 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
881 reg = <0x020ec000 0x4000>;
882 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX6SX_CLK_IPG>,
884 <&clks IMX6SX_CLK_SDMA>;
885 clock-names = "ipg", "ahb";
886 #dma-cells = <3>;
887 /* imx6sx reuses imx6q sdma firmware */
888 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
889 };
890 };
891
892 aips2: bus@2100000 {
893 compatible = "fsl,aips-bus", "simple-bus";
894 #address-cells = <1>;
895 #size-cells = <1>;
896 reg = <0x02100000 0x100000>;
897 ranges;
898
899 crypto: crypto@2100000 {
900 compatible = "fsl,sec-v4.0";
901 #address-cells = <1>;
902 #size-cells = <1>;
903 reg = <0x2100000 0x10000>;
904 ranges = <0 0x2100000 0x10000>;
905 interrupt-parent = <&intc>;
906 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
907 <&clks IMX6SX_CLK_CAAM_ACLK>,
908 <&clks IMX6SX_CLK_CAAM_IPG>,
909 <&clks IMX6SX_CLK_EIM_SLOW>;
910 clock-names = "mem", "aclk", "ipg", "emi_slow";
911
912 sec_jr0: jr@1000 {
913 compatible = "fsl,sec-v4.0-job-ring";
914 reg = <0x1000 0x1000>;
915 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
916 };
917
918 sec_jr1: jr@2000 {
919 compatible = "fsl,sec-v4.0-job-ring";
920 reg = <0x2000 0x1000>;
921 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
922 };
923 };
924
925 usbotg1: usb@2184000 {
926 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
927 reg = <0x02184000 0x200>;
928 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX6SX_CLK_USBOH3>;
930 fsl,usbphy = <&usbphy1>;
931 fsl,usbmisc = <&usbmisc 0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]932 ahb-burst-config = <0x0>;
933 tx-burst-size-dword = <0x10>;
934 rx-burst-size-dword = <0x10>;
935 status = "disabled";
936 };
937
938 usbotg2: usb@2184200 {
939 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
940 reg = <0x02184200 0x200>;
941 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&clks IMX6SX_CLK_USBOH3>;
943 fsl,usbphy = <&usbphy2>;
944 fsl,usbmisc = <&usbmisc 1>;
945 ahb-burst-config = <0x0>;
946 tx-burst-size-dword = <0x10>;
947 rx-burst-size-dword = <0x10>;
948 status = "disabled";
949 };
950
951 usbh: usb@2184400 {
952 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
953 reg = <0x02184400 0x200>;
954 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&clks IMX6SX_CLK_USBOH3>;
956 fsl,usbphy = <&usbphynop1>;
957 fsl,usbmisc = <&usbmisc 2>;
958 phy_type = "hsic";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]959 dr_mode = "host";
960 ahb-burst-config = <0x0>;
961 tx-burst-size-dword = <0x10>;
962 rx-burst-size-dword = <0x10>;
963 status = "disabled";
964 };
965
966 usbmisc: usbmisc@2184800 {
967 #index-cells = <1>;
968 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
969 reg = <0x02184800 0x200>;
970 clocks = <&clks IMX6SX_CLK_USBOH3>;
971 };
972
973 fec1: ethernet@2188000 {
974 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
975 reg = <0x02188000 0x4000>;
976 interrupt-names = "int0", "pps";
977 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&clks IMX6SX_CLK_ENET>,
980 <&clks IMX6SX_CLK_ENET_AHB>,
981 <&clks IMX6SX_CLK_ENET_PTP>,
982 <&clks IMX6SX_CLK_ENET_REF>,
983 <&clks IMX6SX_CLK_ENET_PTP>;
984 clock-names = "ipg", "ahb", "ptp",
985 "enet_clk_ref", "enet_out";
986 fsl,num-tx-queues = <3>;
987 fsl,num-rx-queues = <3>;
988 fsl,stop-mode = <&gpr 0x10 3>;
989 status = "disabled";
990 };
991
992 mlb: mlb@218c000 {
993 reg = <0x0218c000 0x4000>;
994 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&clks IMX6SX_CLK_MLB>;
998 status = "disabled";
999 };
1000
1001 usdhc1: mmc@2190000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]1002 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1003 reg = <0x02190000 0x4000>;
1004 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&clks IMX6SX_CLK_USDHC1>,
1006 <&clks IMX6SX_CLK_USDHC1>,
1007 <&clks IMX6SX_CLK_USDHC1>;
1008 clock-names = "ipg", "ahb", "per";
1009 bus-width = <4>;
1010 fsl,tuning-start-tap = <20>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1011 fsl,tuning-step = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1012 status = "disabled";
1013 };
1014
1015 usdhc2: mmc@2194000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]1016 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1017 reg = <0x02194000 0x4000>;
1018 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&clks IMX6SX_CLK_USDHC2>,
1020 <&clks IMX6SX_CLK_USDHC2>,
1021 <&clks IMX6SX_CLK_USDHC2>;
1022 clock-names = "ipg", "ahb", "per";
1023 bus-width = <4>;
1024 fsl,tuning-start-tap = <20>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1025 fsl,tuning-step = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1026 status = "disabled";
1027 };
1028
1029 usdhc3: mmc@2198000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]1030 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1031 reg = <0x02198000 0x4000>;
1032 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&clks IMX6SX_CLK_USDHC3>,
1034 <&clks IMX6SX_CLK_USDHC3>,
1035 <&clks IMX6SX_CLK_USDHC3>;
1036 clock-names = "ipg", "ahb", "per";
1037 bus-width = <4>;
1038 fsl,tuning-start-tap = <20>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1039 fsl,tuning-step = <2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1040 status = "disabled";
1041 };
1042
1043 usdhc4: mmc@219c000 {
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]1044 compatible = "fsl,imx6sx-usdhc";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1045 reg = <0x0219c000 0x4000>;
1046 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&clks IMX6SX_CLK_USDHC4>,
1048 <&clks IMX6SX_CLK_USDHC4>,
1049 <&clks IMX6SX_CLK_USDHC4>;
1050 clock-names = "ipg", "ahb", "per";
1051 bus-width = <4>;
1052 status = "disabled";
1053 };
1054
1055 i2c1: i2c@21a0000 {
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1059 reg = <0x021a0000 0x4000>;
1060 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&clks IMX6SX_CLK_I2C1>;
1062 status = "disabled";
1063 };
1064
1065 i2c2: i2c@21a4000 {
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1069 reg = <0x021a4000 0x4000>;
1070 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&clks IMX6SX_CLK_I2C2>;
1072 status = "disabled";
1073 };
1074
1075 i2c3: i2c@21a8000 {
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1078 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1079 reg = <0x021a8000 0x4000>;
1080 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&clks IMX6SX_CLK_I2C3>;
1082 status = "disabled";
1083 };
1084
1085 memory-controller@21b0000 {
1086 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1087 reg = <0x021b0000 0x4000>;
1088 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1089 };
1090
1091 fec2: ethernet@21b4000 {
1092 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1093 reg = <0x021b4000 0x4000>;
1094 interrupt-names = "int0", "pps";
1095 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&clks IMX6SX_CLK_ENET>,
1098 <&clks IMX6SX_CLK_ENET_AHB>,
1099 <&clks IMX6SX_CLK_ENET_PTP>,
1100 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1101 <&clks IMX6SX_CLK_ENET_PTP>;
1102 clock-names = "ipg", "ahb", "ptp",
1103 "enet_clk_ref", "enet_out";
1104 fsl,stop-mode = <&gpr 0x10 4>;
1105 status = "disabled";
1106 };
1107
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1108 weim: memory-controller@21b8000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1109 #address-cells = <2>;
1110 #size-cells = <1>;
1111 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1112 reg = <0x021b8000 0x4000>;
1113 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1115 fsl,weim-cs-gpr = <&gpr>;
1116 status = "disabled";
1117 };
1118
1119 ocotp: efuse@21bc000 {
1120 #address-cells = <1>;
1121 #size-cells = <1>;
1122 compatible = "fsl,imx6sx-ocotp", "syscon";
1123 reg = <0x021bc000 0x4000>;
1124 clocks = <&clks IMX6SX_CLK_OCOTP>;
1125
1126 cpu_speed_grade: speed-grade@10 {
1127 reg = <0x10 4>;
1128 };
1129
1130 tempmon_calib: calib@38 {
1131 reg = <0x38 4>;
1132 };
1133
1134 tempmon_temp_grade: temp-grade@20 {
1135 reg = <0x20 4>;
1136 };
1137 };
1138
1139 sai1: sai@21d4000 {
1140 compatible = "fsl,imx6sx-sai";
1141 reg = <0x021d4000 0x4000>;
1142 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1144 <&clks IMX6SX_CLK_SAI1>,
1145 <&clks 0>, <&clks 0>;
1146 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1147 dma-names = "rx", "tx";
1148 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1149 status = "disabled";
1150 };
1151
1152 audmux: audmux@21d8000 {
1153 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1154 reg = <0x021d8000 0x4000>;
1155 status = "disabled";
1156 };
1157
1158 sai2: sai@21dc000 {
1159 compatible = "fsl,imx6sx-sai";
1160 reg = <0x021dc000 0x4000>;
1161 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1163 <&clks IMX6SX_CLK_SAI2>,
1164 <&clks 0>, <&clks 0>;
1165 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1166 dma-names = "rx", "tx";
1167 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1168 status = "disabled";
1169 };
1170
1171 qspi1: spi@21e0000 {
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 compatible = "fsl,imx6sx-qspi";
1175 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1176 reg-names = "QuadSPI", "QuadSPI-memory";
1177 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&clks IMX6SX_CLK_QSPI1>,
1179 <&clks IMX6SX_CLK_QSPI1>;
1180 clock-names = "qspi_en", "qspi";
1181 status = "disabled";
1182 };
1183
1184 qspi2: spi@21e4000 {
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 compatible = "fsl,imx6sx-qspi";
1188 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1189 reg-names = "QuadSPI", "QuadSPI-memory";
1190 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&clks IMX6SX_CLK_QSPI2>,
1192 <&clks IMX6SX_CLK_QSPI2>;
1193 clock-names = "qspi_en", "qspi";
1194 status = "disabled";
1195 };
1196
1197 uart2: serial@21e8000 {
1198 compatible = "fsl,imx6sx-uart",
1199 "fsl,imx6q-uart", "fsl,imx21-uart";
1200 reg = <0x021e8000 0x4000>;
1201 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1203 <&clks IMX6SX_CLK_UART_SERIAL>;
1204 clock-names = "ipg", "per";
1205 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1206 dma-names = "rx", "tx";
1207 status = "disabled";
1208 };
1209
1210 uart3: serial@21ec000 {
1211 compatible = "fsl,imx6sx-uart",
1212 "fsl,imx6q-uart", "fsl,imx21-uart";
1213 reg = <0x021ec000 0x4000>;
1214 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1216 <&clks IMX6SX_CLK_UART_SERIAL>;
1217 clock-names = "ipg", "per";
1218 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1219 dma-names = "rx", "tx";
1220 status = "disabled";
1221 };
1222
1223 uart4: serial@21f0000 {
1224 compatible = "fsl,imx6sx-uart",
1225 "fsl,imx6q-uart", "fsl,imx21-uart";
1226 reg = <0x021f0000 0x4000>;
1227 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1229 <&clks IMX6SX_CLK_UART_SERIAL>;
1230 clock-names = "ipg", "per";
1231 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1232 dma-names = "rx", "tx";
1233 status = "disabled";
1234 };
1235
1236 uart5: serial@21f4000 {
1237 compatible = "fsl,imx6sx-uart",
1238 "fsl,imx6q-uart", "fsl,imx21-uart";
1239 reg = <0x021f4000 0x4000>;
1240 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1242 <&clks IMX6SX_CLK_UART_SERIAL>;
1243 clock-names = "ipg", "per";
1244 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1245 dma-names = "rx", "tx";
1246 status = "disabled";
1247 };
1248
1249 i2c4: i2c@21f8000 {
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1252 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1253 reg = <0x021f8000 0x4000>;
1254 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1255 clocks = <&clks IMX6SX_CLK_I2C4>;
1256 status = "disabled";
1257 };
1258 };
1259
1260 aips3: bus@2200000 {
1261 compatible = "fsl,aips-bus", "simple-bus";
1262 #address-cells = <1>;
1263 #size-cells = <1>;
1264 reg = <0x02200000 0x100000>;
1265 ranges;
1266
1267 spba-bus@2240000 {
1268 compatible = "fsl,spba-bus", "simple-bus";
1269 #address-cells = <1>;
1270 #size-cells = <1>;
1271 reg = <0x02240000 0x40000>;
1272 ranges;
1273
1274 csi1: csi@2214000 {
1275 reg = <0x02214000 0x4000>;
1276 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1278 <&clks IMX6SX_CLK_CSI>,
1279 <&clks IMX6SX_CLK_DCIC1>;
1280 clock-names = "disp-axi", "csi_mclk", "dcic";
1281 status = "disabled";
1282 };
1283
1284 pxp: pxp@2218000 {
1285 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1286 reg = <0x02218000 0x4000>;
1287 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1289 clock-names = "axi";
1290 power-domains = <&pd_disp>;
1291 status = "disabled";
1292 };
1293
1294 csi2: csi@221c000 {
1295 reg = <0x0221c000 0x4000>;
1296 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1297 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1298 <&clks IMX6SX_CLK_CSI>,
1299 <&clks IMX6SX_CLK_DCIC2>;
1300 clock-names = "disp-axi", "csi_mclk", "dcic";
1301 status = "disabled";
1302 };
1303
1304 lcdif1: lcdif@2220000 {
1305 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1306 reg = <0x02220000 0x4000>;
1307 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1308 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1309 <&clks IMX6SX_CLK_LCDIF_APB>,
1310 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1311 clock-names = "pix", "axi", "disp_axi";
1312 assigned-clocks = <&clks IMX6SX_CLK_LCDIF1_PRE_SEL>,
1313 <&clks IMX6SX_CLK_LCDIF1_SEL>;
1314 assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>,
1315 <&clks IMX6SX_CLK_LCDIF1_PODF>;
1316 power-domains = <&pd_disp>;
1317 status = "disabled";
1318
1319 port {
1320 lcdif1_to_ldb: endpoint {
1321 };
1322 };
1323 };
1324
1325 lcdif2: lcdif@2224000 {
1326 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1327 reg = <0x02224000 0x4000>;
1328 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1329 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1330 <&clks IMX6SX_CLK_LCDIF_APB>,
1331 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1332 clock-names = "pix", "axi", "disp_axi";
1333 power-domains = <&pd_disp>;
1334 status = "disabled";
1335 };
1336
1337 vadc: vadc@2228000 {
1338 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1339 reg-names = "vadc-vafe", "vadc-vdec";
1340 clocks = <&clks IMX6SX_CLK_VADC>,
1341 <&clks IMX6SX_CLK_CSI>;
1342 clock-names = "vadc", "csi";
1343 power-domains = <&pd_disp>;
1344 status = "disabled";
1345 };
1346 };
1347
1348 adc1: adc@2280000 {
1349 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1350 reg = <0x02280000 0x4000>;
1351 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1352 clocks = <&clks IMX6SX_CLK_IPG>;
1353 clock-names = "adc";
1354 fsl,adck-max-frequency = <30000000>, <40000000>,
1355 <20000000>;
1356 status = "disabled";
1357 };
1358
1359 adc2: adc@2284000 {
1360 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1361 reg = <0x02284000 0x4000>;
1362 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1363 clocks = <&clks IMX6SX_CLK_IPG>;
1364 clock-names = "adc";
1365 fsl,adck-max-frequency = <30000000>, <40000000>,
1366 <20000000>;
1367 status = "disabled";
1368 };
1369
1370 wdog3: watchdog@2288000 {
1371 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1372 reg = <0x02288000 0x4000>;
1373 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&clks IMX6SX_CLK_IPG>;
1375 status = "disabled";
1376 };
1377
1378 ecspi5: spi@228c000 {
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1381 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1382 reg = <0x0228c000 0x4000>;
1383 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1384 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1385 <&clks IMX6SX_CLK_ECSPI5>;
1386 clock-names = "ipg", "per";
1387 status = "disabled";
1388 };
1389
1390 uart6: serial@22a0000 {
1391 compatible = "fsl,imx6sx-uart",
1392 "fsl,imx6q-uart", "fsl,imx21-uart";
1393 reg = <0x022a0000 0x4000>;
1394 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1396 <&clks IMX6SX_CLK_UART_SERIAL>;
1397 clock-names = "ipg", "per";
1398 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1399 dma-names = "rx", "tx";
1400 status = "disabled";
1401 };
1402
1403 pwm5: pwm@22a4000 {
1404 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1405 reg = <0x022a4000 0x4000>;
1406 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1407 clocks = <&clks IMX6SX_CLK_PWM5>,
1408 <&clks IMX6SX_CLK_PWM5>;
1409 clock-names = "ipg", "per";
1410 #pwm-cells = <3>;
1411 };
1412
1413 pwm6: pwm@22a8000 {
1414 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1415 reg = <0x022a8000 0x4000>;
1416 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1417 clocks = <&clks IMX6SX_CLK_PWM6>,
1418 <&clks IMX6SX_CLK_PWM6>;
1419 clock-names = "ipg", "per";
1420 #pwm-cells = <3>;
1421 };
1422
1423 pwm7: pwm@22ac000 {
1424 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1425 reg = <0x022ac000 0x4000>;
1426 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1427 clocks = <&clks IMX6SX_CLK_PWM7>,
1428 <&clks IMX6SX_CLK_PWM7>;
1429 clock-names = "ipg", "per";
1430 #pwm-cells = <3>;
1431 };
1432
1433 pwm8: pwm@22b0000 {
1434 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1435 reg = <0x022b0000 0x4000>;
1436 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1437 clocks = <&clks IMX6SX_CLK_PWM8>,
1438 <&clks IMX6SX_CLK_PWM8>;
1439 clock-names = "ipg", "per";
1440 #pwm-cells = <3>;
1441 };
1442 };
1443
1444 pcie: pcie@8ffc000 {
1445 compatible = "fsl,imx6sx-pcie";
1446 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1447 reg-names = "dbi", "config";
1448 #address-cells = <3>;
1449 #size-cells = <2>;
1450 device_type = "pci";
1451 bus-range = <0x00 0xff>;
1452 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1453 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1454 num-lanes = <1>;
1455 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1456 interrupt-names = "msi";
1457 #interrupt-cells = <1>;
1458 interrupt-map-mask = <0 0 0 0x7>;
1459 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1460 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1461 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1462 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1464 <&clks IMX6SX_CLK_LVDS1_OUT>,
1465 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1466 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1467 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1468 power-domains = <&pd_disp>, <&pd_pci>;
1469 power-domain-names = "pcie", "pcie_phy";
1470 status = "disabled";
1471 };
1472 };
1473};