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git01.mediatek.com / filogic / uboot / ab06a533f08effbbaa2de381e61b6b33778b4b5d / . / src / arm / aspeed / aspeed-bmc-facebook-minerva.dts
blob: ef96b17becb231a2d26c6794c3c087866f1c80bc [file] [log] [blame]
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2023 Facebook Inc.
3/dts-v1/;
4
5#include "aspeed-g6.dtsi"
6#include <dt-bindings/gpio/aspeed-gpio.h>
7#include <dt-bindings/i2c/i2c.h>
8
9/ {
10 model = "Facebook Minerva CMM";
11 compatible = "facebook,minerva-cmc", "aspeed,ast2600";
12
13 aliases {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]14 serial4 = &uart5;
15 serial5 = &uart6;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]16 /*
17 * PCA9548 (2-0077) provides 8 channels connecting to
18 * 6 pcs of FCB (Fan Controller Board).
19 */
20 i2c16 = &imux16;
21 i2c17 = &imux17;
22 i2c18 = &imux18;
23 i2c19 = &imux19;
24 i2c20 = &imux20;
25 i2c21 = &imux21;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]26 i2c22 = &imux22;
27 i2c23 = &imux23;
28 i2c24 = &imux24;
29 i2c25 = &imux25;
30 i2c26 = &imux26;
31 i2c27 = &imux27;
32 i2c28 = &imux28;
33 i2c29 = &imux29;
34 i2c30 = &imux30;
35 i2c31 = &imux31;
36 i2c32 = &imux32;
37 i2c33 = &imux33;
38 i2c34 = &imux34;
39 i2c35 = &imux35;
40 i2c36 = &imux36;
41 i2c37 = &imux37;
42 i2c38 = &imux38;
43 i2c39 = &imux39;
44 i2c40 = &imux40;
45 i2c41 = &imux41;
46 i2c42 = &imux42;
47 i2c43 = &imux43;
48 i2c44 = &imux44;
49 i2c45 = &imux45;
50 i2c46 = &imux46;
51 i2c47 = &imux47;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]52
53 spi1 = &spi_gpio;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]54 };
55
56 chosen {
57 stdout-path = "serial5:57600n8";
58 };
59
60 memory@80000000 {
61 device_type = "memory";
62 reg = <0x80000000 0x80000000>;
63 };
64
65 iio-hwmon {
66 compatible = "iio-hwmon";
67 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
68 <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
69 <&adc1 2>;
70 };
71
72 leds {
73 compatible = "gpio-leds";
74
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]75 led-0 {
76 label = "bmc_heartbeat_amber";
77 gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
78 linux,default-trigger = "heartbeat";
79 };
80
81 led-1 {
82 label = "fp_id_amber";
83 default-state = "off";
84 gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
85 };
86
87 led-2 {
88 label = "power_blue";
89 default-state = "off";
90 gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
91 };
92
93 led-3 {
94 label = "fan_status_led";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]95 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
96 default-state = "off";
97 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]98
99 led-4 {
100 label = "fan_fault_led_n";
101 gpios = <&leds_gpio 10 GPIO_ACTIVE_LOW>;
102 default-state = "off";
103 };
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]104
105 led-5 {
106 label = "bmc_ready_noled";
107 gpios = <&sgpiom0 141 (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>;
108 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]109 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]110
111 spi_gpio: spi {
112 status = "okay";
113 compatible = "spi-gpio";
114 #address-cells = <1>;
115 #size-cells = <0>;
116
117 sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
118 mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
119 miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
120 num-chipselects = <1>;
121 cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
122
123 tpm@0 {
124 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
125 spi-max-frequency = <33000000>;
126 reg = <0>;
127 };
128 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]129};
130
131&uart6 {
132 status = "okay";
133};
134
135&wdt1 {
136 status = "okay";
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_wdtrst1_default>;
139 aspeed,reset-type = "soc";
140 aspeed,external-signal;
141 aspeed,ext-push-pull;
142 aspeed,ext-active-high;
143 aspeed,ext-pulse-duration = <256>;
144};
145
146&mac3 {
147 status = "okay";
148 phy-mode = "rmii";
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_rmii4_default>;
151 fixed-link {
152 speed = <100>;
153 full-duplex;
154 };
155};
156
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]157&mdio3 {
158 status = "okay";
159};
160
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]161&fmc {
162 status = "okay";
163 flash@0 {
164 status = "okay";
165 m25p,fast-read;
166 label = "bmc";
167 spi-max-frequency = <50000000>;
168#include "openbmc-flash-layout-128.dtsi"
169 };
170 flash@1 {
171 status = "okay";
172 m25p,fast-read;
173 label = "alt-bmc";
174 spi-max-frequency = <50000000>;
175 };
176};
177
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]178&sgpiom0 {
179 status = "okay";
180 ngpios = <128>;
181 bus-frequency = <2000000>;
182};
183
184&i2c0 {
185 status = "okay";
186
187 power-monitor@40 {
188 compatible = "ti,ina230";
189 reg = <0x40>;
190 shunt-resistor = <1000>;
191 };
192
193 power-monitor@41 {
194 compatible = "ti,ina230";
195 reg = <0x41>;
196 shunt-resistor = <1000>;
197 };
198
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]199 power-monitor@44 {
200 compatible = "lltc,ltc4287";
201 reg = <0x44>;
202 shunt-resistor-micro-ohms = <2000>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]203 };
204
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]205 power-monitor@43 {
206 compatible = "infineon,xdp710";
207 reg = <0x43>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]208 };
209
210 leds_gpio: gpio@19 {
211 compatible = "nxp,pca9555";
212 reg = <0x19>;
213 gpio-controller;
214 #gpio-cells = <2>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]215 };
216
217 gpio@11 {
218 compatible = "nxp,pca9555";
219 reg = <0x11>;
220 gpio-controller;
221 #gpio-cells = <2>;
222 interrupt-parent = <&sgpiom0>;
223 interrupts = <238 IRQ_TYPE_LEVEL_LOW>;
224
225 gpio-line-names =
226 "PWRGD_P24V_SMPWROK", "P1V5_PWROK",
227 "P3V3_PWROK", "P5V_PWROK",
228 "P12V_SCM_PWROK", "P12V_PWROK",
229 "P24V_PWROK", "P48V_HSC_PWROK",
230 "ERR_GPIO_IRQ", "TMP75_ALERT_N",
231 "BMC_PWROK", "P12V_INA230_ALERT_N",
232 "P24V_INA230_ALERT_N","",
233 "P48V_HSC_ALERT_N", "P1V05_PWROK";
234 };
235
236 gpio@12 {
237 compatible = "nxp,pca9555";
238 reg = <0x12>;
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-parent = <&sgpiom0>;
242 interrupts = <240 IRQ_TYPE_LEVEL_LOW>;
243
244 gpio-line-names =
245 "P1V05_PWR_FAIL", "P1V5_PWR_FAIL",
246 "P24V_PWR_FAIL", "P24V_SM_PWR_FAIL",
247 "IRQ_NW0/1/2_N", "IRQ_NW3/4/5_N",
248 "RTC_INT_N_R", "ERR_GPIO_IRQ",
249 "", "",
250 "", "",
251 "", "",
252 "", "";
253 };
254
255 gpio@13 {
256 compatible = "nxp,pca9555";
257 reg = <0x13>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-parent = <&sgpiom0>;
261 interrupts = <242 IRQ_TYPE_LEVEL_LOW>;
262
263 gpio-line-names =
264 "", "",
265 "", "",
266 "", "",
267 "", "",
268 "RACKMON_A_1", "RACKMON_A_2",
269 "RACKMON_B_1", "RACKMON_B_2",
270 "", "",
271 "", "";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]272 };
273};
274
275&i2c1 {
276 status = "okay";
277
278 temperature-sensor@4b {
279 compatible = "ti,tmp75";
280 reg = <0x4b>;
281 };
282
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]283 temperature-sensor@4f {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]284 compatible = "ti,tmp75";
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]285 reg = <0x4f>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]286 };
287
288 eeprom@54 {
289 compatible = "atmel,24c128";
290 reg = <0x54>;
291 };
292};
293
294&i2c2 {
295 status = "okay";
296
297 i2c-mux@77 {
298 compatible = "nxp,pca9548";
299 reg = <0x77>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 i2c-mux-idle-disconnect;
303
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]304 // FCB 1
305 imux16: i2c@1 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]306 #address-cells = <1>;
307 #size-cells = <0>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]308 reg = <1>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]309
310 eeprom@50 {
311 compatible = "atmel,24c128";
312 reg = <0x50>;
313 };
314
315 pwm@5e{
316 compatible = "max31790";
317 reg = <0x5e>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]321
322 power-sensor@40 {
323 compatible = "ti,ina238";
324 reg = <0x40>;
325 shunt-resistor = <1000>;
326 };
327
328 power-sensor@41 {
329 compatible = "ti,ina238";
330 reg = <0x41>;
331 shunt-resistor = <1000>;
332 };
333
334 power-sensor@44 {
335 compatible = "ti,ina238";
336 reg = <0x44>;
337 shunt-resistor = <1000>;
338 };
339
340 power-sensor@45 {
341 compatible = "ti,ina238";
342 reg = <0x45>;
343 shunt-resistor = <1000>;
344 };
345
346 temperature-sensor@4b {
347 compatible = "ti,tmp75";
348 reg = <0x4b>;
349 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]350
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]351 gpio@11 {
352 compatible = "nxp,pca9555";
353 reg = <0x11>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 interrupt-parent = <&sgpiom0>;
357 interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
358
359 gpio-line-names =
360 "P48V_FAN1_PWRGD_R", "P48V_FAN2_PWRGD_R",
361 "P48V_FAN3_PWRGD_R", "P48V_FAN4_PWRGD_R",
362 "FCB_1_P48V_ZONE0_PWRGD_R", "FCB_1_P48V_ZONE1_PWRGD_R",
363 "FCB_1_PWRGD_P3V3_R", "",
364 "", "",
365 "", "",
366 "", "",
367 "", "";
368 };
369
370 gpio@12 {
371 compatible = "nxp,pca9555";
372 reg = <0x12>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 interrupt-parent = <&sgpiom0>;
376 interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
377
378 gpio-line-names =
379 "INA238_FAN1_ALERT_N", "INA238_FAN2_ALERT_N",
380 "INA238_FAN3_ALERT_N", "INA238_FAN4_ALERT_N",
381 "FCB_1_TMP75_ALERT_N", "",
382 "", "",
383 "FAN1_PRSNT", "FAN2_PRSNT",
384 "FAN3_PRSNT", "FAN4_PRSNT",
385 "", "",
386 "", "";
387 };
388
389 gpio@13 {
390 compatible = "nxp,pca9555";
391 reg = <0x13>;
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-parent = <&sgpiom0>;
395 interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
396
397 gpio-line-names =
398 "FAN1_IL_TACH_ALERT", "FAN1_OL_TACH_ALERT",
399 "FAN2_IL_TACH_ALERT", "FAN2_OL_TACH_ALERT",
400 "FAN3_IL_TACH_ALERT", "FAN3_OL_TACH_ALERT",
401 "FAN4_IL_TACH_ALERT", "FAN4_IL_TACH_ALERT",
402 "", "",
403 "", "",
404 "", "",
405 "", "";
406 };
407
408 gpio@17 {
409 compatible = "nxp,pca9555";
410 reg = <0x17>;
411 gpio-controller;
412 #gpio-cells = <2>;
413 interrupt-parent = <&sgpiom0>;
414 interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
415
416 gpio-line-names =
417 "FCB_1_P1V0_POWER_FAIL", "FCB_1_P1V8_POWER_FAIL",
418 "FCB_1_P48V_ZONE0_POWER_FAIL", "FAN1_POWER_FAIL",
419 "FAN2_POWER_FAIL", "FAN3_POWER_FAIL",
420 "FAN4_POWER_FAIL", "",
421 "", "",
422 "", "",
423 "", "",
424 "", "";
425 };
426 };
427 // FCB 2
428 imux17: i2c@0 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]429 #address-cells = <1>;
430 #size-cells = <0>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]431 reg = <0>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]432
433 eeprom@50 {
434 compatible = "atmel,24c128";
435 reg = <0x50>;
436 };
437
438 pwm@5e{
439 compatible = "max31790";
440 reg = <0x5e>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]444
445 power-sensor@40 {
446 compatible = "ti,ina238";
447 reg = <0x40>;
448 shunt-resistor = <1000>;
449 };
450
451 power-sensor@41 {
452 compatible = "ti,ina238";
453 reg = <0x41>;
454 shunt-resistor = <1000>;
455 };
456
457 power-sensor@44 {
458 compatible = "ti,ina238";
459 reg = <0x44>;
460 shunt-resistor = <1000>;
461 };
462
463 power-sensor@45 {
464 compatible = "ti,ina238";
465 reg = <0x45>;
466 shunt-resistor = <1000>;
467 };
468
469 temperature-sensor@4b {
470 compatible = "ti,tmp75";
471 reg = <0x4b>;
472 };
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]473
474 gpio@11 {
475 compatible = "nxp,pca9555";
476 reg = <0x11>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-parent = <&sgpiom0>;
480 interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
481
482 gpio-line-names =
483 "P48V_FAN5_PWRGD_R", "P48V_FAN6_PWRGD_R",
484 "P48V_FAN7_PWRGD_R", "P48V_FAN8_PWRGD_R",
485 "FCB_2_P48V_ZONE0_PWRGD_R", "FCB_2_P48V_ZONE1_PWRGD_R",
486 "FCB_2_PWRGD_P3V3_R", "",
487 "", "",
488 "", "",
489 "", "",
490 "", "";
491 };
492
493 gpio@12 {
494 compatible = "nxp,pca9555";
495 reg = <0x12>;
496 gpio-controller;
497 #gpio-cells = <2>;
498 interrupt-parent = <&sgpiom0>;
499 interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
500
501 gpio-line-names =
502 "INA238_FAN5_ALERT_N", "INA238_FAN6_ALERT_N",
503 "INA238_FAN7_ALERT_N", "INA238_FAN8_ALERT_N",
504 "FCB_2_TMP75_ALERT_N", "",
505 "", "",
506 "FAN5_PRSNT", "FAN6_PRSNT",
507 "FAN7_PRSNT", "FAN8_PRSNT",
508 "", "",
509 "", "";
510 };
511
512 gpio@13 {
513 compatible = "nxp,pca9555";
514 reg = <0x13>;
515 gpio-controller;
516 #gpio-cells = <2>;
517 interrupt-parent = <&sgpiom0>;
518 interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]519
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]520 gpio-line-names =
521 "FAN5_IL_TACH_ALERT", "FAN5_OL_TACH_ALERT",
522 "FAN6_IL_TACH_ALERT", "FAN6_OL_TACH_ALERT",
523 "FAN7_IL_TACH_ALERT", "FAN7_OL_TACH_ALERT",
524 "FAN8_IL_TACH_ALERT", "FAN8_IL_TACH_ALERT",
525 "", "",
526 "", "",
527 "", "",
528 "", "";
529 };
530
531 gpio@17 {
532 compatible = "nxp,pca9555";
533 reg = <0x17>;
534 gpio-controller;
535 #gpio-cells = <2>;
536 interrupt-parent = <&sgpiom0>;
537 interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
538
539 gpio-line-names =
540 "FCB_2_P1V0_POWER_FAIL", "FCB_2_P1V8_POWER_FAIL",
541 "FCB_2_P48V_ZONE0_POWER_FAIL", "FAN5_POWER_FAIL",
542 "FAN6_POWER_FAIL", "FAN7_POWER_FAIL",
543 "FAN8_POWER_FAIL", "",
544 "", "",
545 "", "",
546 "", "",
547 "", "";
548 };
549 };
550 // FCB 3
551 imux18: i2c@3 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]552 #address-cells = <1>;
553 #size-cells = <0>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]554 reg = <3>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]555
556 eeprom@50 {
557 compatible = "atmel,24c128";
558 reg = <0x50>;
559 };
560
561 pwm@5e{
562 compatible = "max31790";
563 reg = <0x5e>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]567
568 power-sensor@40 {
569 compatible = "ti,ina238";
570 reg = <0x40>;
571 shunt-resistor = <1000>;
572 };
573
574 power-sensor@41 {
575 compatible = "ti,ina238";
576 reg = <0x41>;
577 shunt-resistor = <1000>;
578 };
579
580 power-sensor@44 {
581 compatible = "ti,ina238";
582 reg = <0x44>;
583 shunt-resistor = <1000>;
584 };
585
586 power-sensor@45 {
587 compatible = "ti,ina238";
588 reg = <0x45>;
589 shunt-resistor = <1000>;
590 };
591
592 temperature-sensor@4b {
593 compatible = "ti,tmp75";
594 reg = <0x4b>;
595 };
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]596
597 gpio@11 {
598 compatible = "nxp,pca9555";
599 reg = <0x11>;
600 gpio-controller;
601 #gpio-cells = <2>;
602 interrupt-parent = <&sgpiom0>;
603 interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]604
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]605 gpio-line-names =
606 "P48V_FAN9_PWRGD_R", "P48V_FAN10_PWRGD_R",
607 "P48V_FAN11_PWRGD_R", "P48V_FAN12_PWRGD_R",
608 "FCB_3_P48V_ZONE0_PWRGD_R", "FCB_3_P48V_ZONE1_PWRGD_R",
609 "FCB_3_PWRGD_P3V3_R", "",
610 "", "",
611 "", "",
612 "", "",
613 "", "";
614 };
615
616 gpio@12 {
617 compatible = "nxp,pca9555";
618 reg = <0x12>;
619 gpio-controller;
620 #gpio-cells = <2>;
621 interrupt-parent = <&sgpiom0>;
622 interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
623
624 gpio-line-names =
625 "INA238_FAN9_ALERT_N", "INA238_FAN10_ALERT_N",
626 "INA238_FAN11_ALERT_N", "INA238_FAN12_ALERT_N",
627 "FCB_3_TMP75_ALERT_N", "",
628 "", "",
629 "FAN9_PRSNT", "FAN10_PRSNT",
630 "FAN11_PRSNT", "FAN12_PRSNT",
631 "", "",
632 "", "";
633 };
634
635 gpio@13 {
636 compatible = "nxp,pca9555";
637 reg = <0x13>;
638 gpio-controller;
639 #gpio-cells = <2>;
640 interrupt-parent = <&sgpiom0>;
641 interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
642
643 gpio-line-names =
644 "FAN9_IL_TACH_ALERT", "FAN9_OL_TACH_ALERT",
645 "FAN10_IL_TACH_ALERT", "FAN10_OL_TACH_ALERT",
646 "FAN11_IL_TACH_ALERT", "FAN11_OL_TACH_ALERT",
647 "FAN12_IL_TACH_ALERT", "FAN12_IL_TACH_ALERT",
648 "", "",
649 "", "",
650 "", "",
651 "", "";
652 };
653
654 gpio@17 {
655 compatible = "nxp,pca9555";
656 reg = <0x17>;
657 gpio-controller;
658 #gpio-cells = <2>;
659 interrupt-parent = <&sgpiom0>;
660 interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
661
662 gpio-line-names =
663 "FCB_3_P1V0_POWER_FAIL", "FCB_3_P1V8_POWER_FAIL",
664 "FCB_3_P48V_ZONE0_POWER_FAIL", "FAN9_POWER_FAIL",
665 "FAN10_POWER_FAIL", "FAN11_POWER_FAIL",
666 "FAN12_POWER_FAIL", "",
667 "", "",
668 "", "",
669 "", "",
670 "", "";
671 };
672 };
673 // FCB 4
674 imux19: i2c@2 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]675 #address-cells = <1>;
676 #size-cells = <0>;
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]677 reg = <2>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]678
679 eeprom@50 {
680 compatible = "atmel,24c128";
681 reg = <0x50>;
682 };
683
684 pwm@5e{
685 compatible = "max31790";
686 reg = <0x5e>;
687 #address-cells = <1>;
688 #size-cells = <0>;
689 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]690
691 power-sensor@40 {
692 compatible = "ti,ina238";
693 reg = <0x40>;
694 shunt-resistor = <1000>;
695 };
696
697 power-sensor@41 {
698 compatible = "ti,ina238";
699 reg = <0x41>;
700 shunt-resistor = <1000>;
701 };
702
703 power-sensor@44 {
704 compatible = "ti,ina238";
705 reg = <0x44>;
706 shunt-resistor = <1000>;
707 };
708
709 power-sensor@45 {
710 compatible = "ti,ina238";
711 reg = <0x45>;
712 shunt-resistor = <1000>;
713 };
714
715 temperature-sensor@4b {
716 compatible = "ti,tmp75";
717 reg = <0x4b>;
718 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]719
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]720 gpio@11 {
721 compatible = "nxp,pca9555";
722 reg = <0x11>;
723 gpio-controller;
724 #gpio-cells = <2>;
725 interrupt-parent = <&sgpiom0>;
726 interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
727
728 gpio-line-names =
729 "P48V_FAN13_PWRGD_R", "P48V_FAN14_PWRGD_R",
730 "P48V_FAN15_PWRGD_R", "P48V_FAN16_PWRGD_R",
731 "FCB_4_P48V_ZONE0_PWRGD_R", "FCB_4_P48V_ZONE1_PWRGD_R",
732 "FCB_4_PWRGD_P3V3_R", "",
733 "", "",
734 "", "",
735 "", "",
736 "", "";
737 };
738
739 gpio@12 {
740 compatible = "nxp,pca9555";
741 reg = <0x12>;
742 gpio-controller;
743 #gpio-cells = <2>;
744 interrupt-parent = <&sgpiom0>;
745 interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
746
747 gpio-line-names =
748 "INA238_FAN13_ALERT_N", "INA238_FAN14_ALERT_N",
749 "INA238_FAN15_ALERT_N", "INA238_FAN16_ALERT_N",
750 "FCB_4_TMP75_ALERT_N", "",
751 "", "",
752 "FAN13_PRSNT", "FAN14_PRSNT",
753 "FAN15_PRSNT", "FAN16_PRSNT",
754 "", "",
755 "", "";
756 };
757
758 gpio@13 {
759 compatible = "nxp,pca9555";
760 reg = <0x13>;
761 gpio-controller;
762 #gpio-cells = <2>;
763 interrupt-parent = <&sgpiom0>;
764 interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
765
766 gpio-line-names =
767 "FAN13_IL_TACH_ALERT", "FAN13_OL_TACH_ALERT",
768 "FAN14_IL_TACH_ALERT", "FAN14_OL_TACH_ALERT",
769 "FAN15_IL_TACH_ALERT", "FAN15_OL_TACH_ALERT",
770 "FAN16_IL_TACH_ALERT", "FAN16_IL_TACH_ALERT",
771 "", "",
772 "", "",
773 "", "",
774 "", "";
775 };
776
777 gpio@17 {
778 compatible = "nxp,pca9555";
779 reg = <0x17>;
780 gpio-controller;
781 #gpio-cells = <2>;
782 interrupt-parent = <&sgpiom0>;
783 interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
784
785 gpio-line-names =
786 "FCB_4_P1V0_POWER_FAIL", "FCB_4_P1V8_POWER_FAIL",
787 "FCB_4_P48V_ZONE0_POWER_FAIL", "FAN13_POWER_FAIL",
788 "FAN14_POWER_FAIL", "FAN15_POWER_FAIL",
789 "FAN16_POWER_FAIL", "",
790 "", "",
791 "", "",
792 "", "",
793 "", "";
794 };
795 };
796 // FCB 5
797 imux20: i2c@4 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]798 #address-cells = <1>;
799 #size-cells = <0>;
800 reg = <4>;
801
802 eeprom@50 {
803 compatible = "atmel,24c128";
804 reg = <0x50>;
805 };
806
807 pwm@5e{
808 compatible = "max31790";
809 reg = <0x5e>;
810 #address-cells = <1>;
811 #size-cells = <0>;
812 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]813
814 power-sensor@40 {
815 compatible = "ti,ina238";
816 reg = <0x40>;
817 shunt-resistor = <1000>;
818 };
819
820 power-sensor@41 {
821 compatible = "ti,ina238";
822 reg = <0x41>;
823 shunt-resistor = <1000>;
824 };
825
826 power-sensor@44 {
827 compatible = "ti,ina238";
828 reg = <0x44>;
829 shunt-resistor = <1000>;
830 };
831
832 power-sensor@45 {
833 compatible = "ti,ina238";
834 reg = <0x45>;
835 shunt-resistor = <1000>;
836 };
837 temperature-sensor@4b {
838 compatible = "ti,tmp75";
839 reg = <0x4b>;
840 };
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]841
842 gpio@11 {
843 compatible = "nxp,pca9555";
844 reg = <0x11>;
845 gpio-controller;
846 #gpio-cells = <2>;
847 interrupt-parent = <&sgpiom0>;
848 interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
849
850 gpio-line-names =
851 "P48V_FAN20_PWRGD_R", "P48V_FAN19_PWRGD_R",
852 "P48V_FAN18_PWRGD_R", "P48V_FAN17_PWRGD_R",
853 "FCB_5_P48V_ZONE0_PWRGD_R", "FCB_5_P48V_ZONE1_PWRGD_R",
854 "FCB_5_PWRGD_P3V3_R", "",
855 "", "",
856 "", "",
857 "", "",
858 "", "";
859 };
860
861 gpio@12 {
862 compatible = "nxp,pca9555";
863 reg = <0x12>;
864 gpio-controller;
865 #gpio-cells = <2>;
866 interrupt-parent = <&sgpiom0>;
867 interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
868
869 gpio-line-names =
870 "INA238_FAN20_ALERT_N", "INA238_FAN19_ALERT_N",
871 "INA238_FAN18_ALERT_N", "INA238_FAN17_ALERT_N",
872 "FCB_5_TMP75_ALERT_N", "",
873 "", "",
874 "FAN20_PRSNT", "FAN19_PRSNT",
875 "FAN18_PRSNT", "FAN17_PRSNT",
876 "", "",
877 "", "";
878 };
879
880 gpio@13 {
881 compatible = "nxp,pca9555";
882 reg = <0x13>;
883 gpio-controller;
884 #gpio-cells = <2>;
885 interrupt-parent = <&sgpiom0>;
886 interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
887
888 gpio-line-names =
889 "FAN20_IL_TACH_ALERT", "FAN20_OL_TACH_ALERT",
890 "FAN19_IL_TACH_ALERT", "FAN19_OL_TACH_ALERT",
891 "FAN18_IL_TACH_ALERT", "FAN18_OL_TACH_ALERT",
892 "FAN17_IL_TACH_ALERT", "FAN17_OL_TACH_ALERT",
893 "", "",
894 "", "",
895 "", "",
896 "", "";
897 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]898
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]899 gpio@17 {
900 compatible = "nxp,pca9555";
901 reg = <0x17>;
902 gpio-controller;
903 #gpio-cells = <2>;
904 interrupt-parent = <&sgpiom0>;
905 interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
906
907 gpio-line-names =
908 "FCB_5_P1V0_POWER_FAIL", "FCB_5_P1V8_POWER_FAIL",
909 "FCB_5_P48V_ZONE0_POWER_FAIL", "FAN20_POWER_FAIL",
910 "FAN19_POWER_FAIL", "FAN18_POWER_FAIL",
911 "FAN17_POWER_FAIL", "",
912 "", "",
913 "", "",
914 "", "",
915 "", "";
916 };
917 };
918 // FCB 6
919 imux21: i2c@5 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]920 #address-cells = <1>;
921 #size-cells = <0>;
922 reg = <5>;
923
924 eeprom@50 {
925 compatible = "atmel,24c128";
926 reg = <0x50>;
927 };
928
929 pwm@5e{
930 compatible = "max31790";
931 reg = <0x5e>;
932 #address-cells = <1>;
933 #size-cells = <0>;
934 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]935
936 power-sensor@40 {
937 compatible = "ti,ina238";
938 reg = <0x40>;
939 shunt-resistor = <1000>;
940 };
941
942 power-sensor@41 {
943 compatible = "ti,ina238";
944 reg = <0x41>;
945 shunt-resistor = <1000>;
946 };
947
948 power-sensor@44 {
949 compatible = "ti,ina238";
950 reg = <0x44>;
951 shunt-resistor = <1000>;
952 };
953
954 power-sensor@45 {
955 compatible = "ti,ina238";
956 reg = <0x45>;
957 shunt-resistor = <1000>;
958 };
959 temperature-sensor@4b {
960 compatible = "ti,tmp75";
961 reg = <0x4b>;
962 };
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]963
964 gpio@11 {
965 compatible = "nxp,pca9555";
966 reg = <0x11>;
967 gpio-controller;
968 #gpio-cells = <2>;
969 interrupt-parent = <&sgpiom0>;
970 interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
971
972 gpio-line-names =
973 "P48V_FAN24_PWRGD_R", "P48V_FAN23_PWRGD_R",
974 "P48V_FAN22_PWRGD_R", "P48V_FAN21_PWRGD_R",
975 "FCB_6_P48V_ZONE0_PWRGD_R", "FCB_6_P48V_ZONE1_PWRGD_R",
976 "FCB_6_PWRGD_P3V3_R", "",
977 "", "",
978 "", "",
979 "", "",
980 "", "";
981 };
982
983 gpio@12 {
984 compatible = "nxp,pca9555";
985 reg = <0x12>;
986 gpio-controller;
987 #gpio-cells = <2>;
988 interrupt-parent = <&sgpiom0>;
989 interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
990
991 gpio-line-names =
992 "INA238_FAN24_ALERT_N", "INA238_FAN23_ALERT_N",
993 "INA238_FAN22_ALERT_N", "INA238_FAN21_ALERT_N",
994 "FCB_6_TMP75_ALERT_N", "",
995 "", "",
996 "FAN24_PRSNT", "FAN23_PRSNT",
997 "FAN22_PRSNT", "FAN21_PRSNT",
998 "", "",
999 "", "";
1000 };
1001
1002 gpio@13 {
1003 compatible = "nxp,pca9555";
1004 reg = <0x13>;
1005 gpio-controller;
1006 #gpio-cells = <2>;
1007 interrupt-parent = <&sgpiom0>;
1008 interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
1009
1010 gpio-line-names =
1011 "FAN24_IL_TACH_ALERT", "FAN24_OL_TACH_ALERT",
1012 "FAN23_IL_TACH_ALERT", "FAN23_OL_TACH_ALERT",
1013 "FAN22_IL_TACH_ALERT", "FAN22_OL_TACH_ALERT",
1014 "FAN21_IL_TACH_ALERT", "FAN21_OL_TACH_ALERT",
1015 "", "",
1016 "", "",
1017 "", "",
1018 "", "";
1019 };
1020
1021 gpio@17 {
1022 compatible = "nxp,pca9555";
1023 reg = <0x17>;
1024 gpio-controller;
1025 #gpio-cells = <2>;
1026 interrupt-parent = <&sgpiom0>;
1027 interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
1028
1029 gpio-line-names =
1030 "FCB_6_P1V0_POWER_FAIL", "FCB_6_P1V8_POWER_FAIL",
1031 "FCB_6_P48V_ZONE0_POWER_FAIL", "FAN24_POWER_FAIL",
1032 "FAN23_POWER_FAIL", "FAN22_POWER_FAIL",
1033 "FAN21_POWER_FAIL", "",
1034 "", "",
1035 "", "",
1036 "", "",
1037 "", "";
1038 };
1039 };
1040
1041 imux22: i2c@6 {
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044 reg = <6>;
1045 };
1046
1047 imux23: i2c@7 {
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 reg = <7>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1051 };
1052 };
1053};
1054
1055&i2c3 {
1056 status = "okay";
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1057
1058 i2c-mux@72 {
1059 compatible = "nxp,pca9545";
1060 reg = <0x72>;
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063
1064 imux24: i2c@0 {
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1067 reg = <0>;
1068
1069 eeprom@50 {
1070 compatible = "atmel,24c64";
1071 reg = <0x50>;
1072 };
1073 };
1074
1075 imux25: i2c@1 {
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1078 reg = <1>;
1079
1080 eeprom@50 {
1081 compatible = "atmel,24c64";
1082 reg = <0x50>;
1083 };
1084 };
1085
1086 imux26: i2c@2 {
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089 reg = <2>;
1090
1091 eeprom@50 {
1092 compatible = "atmel,24c64";
1093 reg = <0x50>;
1094 };
1095 };
1096
1097 imux27: i2c@3 {
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 reg = <3>;
1101
1102 eeprom@50 {
1103 compatible = "atmel,24c64";
1104 reg = <0x50>;
1105 };
1106 };
1107 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1108};
1109
1110&i2c4 {
1111 status = "okay";
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1112
1113 i2c-mux@72 {
1114 compatible = "nxp,pca9545";
1115 reg = <0x72>;
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118
1119 imux28: i2c@0 {
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1122 reg = <0>;
1123
1124 eeprom@50 {
1125 compatible = "atmel,24c64";
1126 reg = <0x50>;
1127 };
1128 };
1129
1130 imux29: i2c@1 {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 reg = <1>;
1134
1135 eeprom@50 {
1136 compatible = "atmel,24c64";
1137 reg = <0x50>;
1138 };
1139 };
1140
1141 imux30: i2c@2 {
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144 reg = <2>;
1145
1146 eeprom@50 {
1147 compatible = "atmel,24c64";
1148 reg = <0x50>;
1149 };
1150 };
1151
1152 imux31: i2c@3 {
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 reg = <3>;
1156
1157 eeprom@50 {
1158 compatible = "atmel,24c64";
1159 reg = <0x50>;
1160 };
1161 };
1162 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1163};
1164
1165&i2c5 {
1166 status = "okay";
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1167
1168 i2c-mux@72 {
1169 compatible = "nxp,pca9545";
1170 reg = <0x72>;
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1173
1174 imux32: i2c@0 {
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 reg = <0>;
1178
1179 eeprom@50 {
1180 compatible = "atmel,24c64";
1181 reg = <0x50>;
1182 };
1183 };
1184
1185 imux33: i2c@1 {
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 reg = <1>;
1189
1190 eeprom@50 {
1191 compatible = "atmel,24c64";
1192 reg = <0x50>;
1193 };
1194 };
1195
1196 imux34: i2c@2 {
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 reg = <2>;
1200
1201 eeprom@50 {
1202 compatible = "atmel,24c64";
1203 reg = <0x50>;
1204 };
1205 };
1206
1207 imux35: i2c@3 {
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1210 reg = <3>;
1211
1212 eeprom@50 {
1213 compatible = "atmel,24c64";
1214 reg = <0x50>;
1215 };
1216 };
1217 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1218};
1219
1220&i2c6 {
1221 status = "okay";
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1222
1223 i2c-mux@72 {
1224 compatible = "nxp,pca9545";
1225 reg = <0x72>;
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1228
1229 imux36: i2c@0 {
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1232 reg = <0>;
1233
1234 eeprom@50 {
1235 compatible = "atmel,24c64";
1236 reg = <0x50>;
1237 };
1238 };
1239
1240 imux37: i2c@1 {
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1243 reg = <1>;
1244
1245 eeprom@50 {
1246 compatible = "atmel,24c64";
1247 reg = <0x50>;
1248 };
1249 };
1250
1251 imux38: i2c@2 {
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 reg = <2>;
1255
1256 eeprom@50 {
1257 compatible = "atmel,24c64";
1258 reg = <0x50>;
1259 };
1260 };
1261
1262 imux39: i2c@3 {
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1265 reg = <3>;
1266
1267 eeprom@50 {
1268 compatible = "atmel,24c64";
1269 reg = <0x50>;
1270 };
1271 };
1272 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1273};
1274
1275&i2c7 {
1276 status = "okay";
1277};
1278
1279&i2c8 {
1280 status = "okay";
1281};
1282
1283&i2c9 {
1284 status = "okay";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1285
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1286 eeprom@50 {
1287 compatible = "atmel,24c64";
1288 reg = <0x50>;
1289 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1290
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1291 rtc@51 {
1292 compatible = "nxp,pcf8563";
1293 reg = <0x51>;
1294 };
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1295
1296 rtc@68 {
1297 compatible = "dallas,ds1339";
1298 reg = <0x68>;
1299 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1300};
1301
1302&i2c12 {
1303 status = "okay";
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1304
1305 i2c-mux@70 {
1306 compatible = "nxp,pca9545";
1307 reg = <0x70>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310
1311 imux40: i2c@0 {
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314 reg = <0>;
1315
1316 eeprom@50 {
1317 compatible = "atmel,24c64";
1318 reg = <0x50>;
1319 };
1320 };
1321
1322 imux41: i2c@1 {
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1325 reg = <1>;
1326
1327 eeprom@50 {
1328 compatible = "atmel,24c64";
1329 reg = <0x50>;
1330 };
1331 };
1332
1333 imux42: i2c@2 {
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 reg = <2>;
1337
1338 eeprom@50 {
1339 compatible = "atmel,24c64";
1340 reg = <0x50>;
1341 };
1342 };
1343
1344 imux43: i2c@3 {
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1347 reg = <3>;
1348 };
1349 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1350};
1351
1352&i2c13 {
1353 status = "okay";
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1354
1355 i2c-mux@70 {
1356 compatible = "nxp,pca9545";
1357 reg = <0x70>;
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360
1361 imux44: i2c@0 {
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 reg = <0>;
1365
1366 eeprom@50 {
1367 compatible = "atmel,24c64";
1368 reg = <0x50>;
1369 };
1370 };
1371
1372 imux45: i2c@1 {
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1375 reg = <1>;
1376
1377 eeprom@50 {
1378 compatible = "atmel,24c64";
1379 reg = <0x50>;
1380 };
1381 };
1382
1383 imux46: i2c@2 {
1384 #address-cells = <1>;
1385 #size-cells = <0>;
1386 reg = <2>;
1387
1388 eeprom@50 {
1389 compatible = "atmel,24c64";
1390 reg = <0x50>;
1391 };
1392 };
1393
1394 imux47: i2c@3 {
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1397 reg = <3>;
1398 };
1399 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1400};
1401
1402&i2c14 {
1403 status = "okay";
1404 multi-master;
1405
1406 ipmb@10 {
1407 compatible = "ipmb-dev";
1408 reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
1409 i2c-protocol;
1410 };
1411};
1412
1413&i2c15 {
1414 status = "okay";
1415
1416 eeprom@50 {
1417 compatible = "atmel,24c128";
1418 reg = <0x50>;
1419 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1420
1421 eeprom@56 {
1422 compatible = "atmel,24c64";
1423 reg = <0x56>;
1424 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1425};
1426
1427&adc0 {
1428 aspeed,int-vref-microvolt = <2500000>;
1429 status = "okay";
1430 pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
1431 &pinctrl_adc2_default &pinctrl_adc3_default
1432 &pinctrl_adc4_default &pinctrl_adc5_default
1433 &pinctrl_adc6_default &pinctrl_adc7_default>;
1434};
1435
1436&adc1 {
1437 aspeed,int-vref-microvolt = <2500000>;
1438 status = "okay";
1439 pinctrl-0 = <&pinctrl_adc10_default>;
1440};
1441
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1442&ehci0 {
1443 status = "okay";
1444};
1445
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1446&ehci1 {
1447 status = "okay";
1448};
1449
1450&uhci {
1451 status = "okay";
1452};
1453
1454&gpio0 {
1455 gpio-line-names =
1456 /*A0-A7*/ "","","","","","","","",
1457 /*B0-B7*/ "","","","","","","","",
1458 /*C0-C7*/ "","","","","BLADE_UART_SEL2","","","",
1459 /*D0-D7*/ "","","","","","","","",
1460 /*E0-E7*/ "","","","","","","","",
1461 /*F0-F7*/ "","","","","","","","",
1462 /*G0-G7*/ "","","","","","","","",
1463 /*H0-H7*/ "","","","","","","","",
1464 /*I0-I7*/ "","","","","","","","",
1465 /*J0-J7*/ "","","","","","","","",
1466 /*K0-K7*/ "","","","","","","","",
1467 /*L0-L7*/ "","","","","BLADE_UART_SEL0","","","",
1468 /*M0-M7*/ "","","","","","BLADE_UART_SEL1","","",
1469 /*N0-N7*/ "","","","","","","","",
1470 /*O0-O7*/ "","","","","","","","",
1471 /*P0-P7*/ "","","","","","","","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1472 /*Q0-Q7*/ "","","","","","power-chassis-control","","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1473 /*R0-R7*/ "","","","","","","","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1474 /*S0-S7*/ "","","","","","","","host0-ready",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1475 /*T0-T7*/ "","","","","","","","",
1476 /*U0-U7*/ "","","","","","","","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1477 /*V0-V7*/ "","","","","BAT_DETECT","","power-chassis-good","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1478 /*W0-W7*/ "","","","","","","","",
1479 /*X0-X7*/ "","","BLADE_UART_SEL3","","","","","",
1480 /*Y0-Y7*/ "","","","","","","","",
1481 /*Z0-Z7*/ "","","","","","","","";
1482};
1483
1484&sgpiom0 {
1485 gpio-line-names =
1486 /*"input pin","output pin"*/
1487 /*A0 - A7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1488 "PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N",
1489 "PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N",
1490 "PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N",
1491 "PRSNT_MTIA_BLADE4_N","PWREN_MTIA_BLADE4_EN_N",
1492 "PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N",
1493 "PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N",
1494 "PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1495 "PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1496 /*B0 - B7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1497 "PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N",
1498 "PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N",
1499 "PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N",
1500 "PRSNT_MTIA_BLADE12_N","PWREN_MTIA_BLADE12_EN_N",
1501 "PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N",
1502 "PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N",
1503 "PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1504 "PRSNT_MTIA_BLADE16_N","PWREN_MTIA_BLADE16_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1505 /*C0 - C7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1506 "PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N",
1507 "PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N",
1508 "PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N",
1509 "PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N",
1510 "PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1511 "PRSNT_NW_BLADE6_N","PWREN_NW_BLADE6_EN_N",
1512 "PRSNT_FCB_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
1513 "PRSNT_FCB_2_N","PWREN_MTIA_BLADE2_HSC_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1514 /*D0 - D7*/
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1515 "PRSNT_FCB_3_N","PWREN_MTIA_BLADE3_HSC_EN_N",
1516 "PRSNT_FCB_4_N","PWREN_MTIA_BLADE4_HSC_EN_N",
1517 "PRSNT_FCB_6_N","PWREN_MTIA_BLADE5_HSC_EN_N",
1518 "PRSNT_FCB_5_N","PWREN_MTIA_BLADE6_HSC_EN_N",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1519 "PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N",
1520 "PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N",
1521 "PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1522 "PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1523 /*E0 - E7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1524 "PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N",
1525 "PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N",
1526 "PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N",
1527 "PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N",
1528 "PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1529 "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_MTIA_BLADE16_HSC_EN_N",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1530 "PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1531 "PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1532 /*F0 - F7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1533 "PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N",
1534 "PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N",
1535 "PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1536 "PWRGD_MTIA_BLADE16_PWROK_N","PWREN_NW_BLADE6_HSC_EN_N",
1537 "PWRGD_NW_BLADE1_PWROK_N","PWREN_SGPIO_FCB_2_EN_N",
1538 "PWRGD_NW_BLADE2_PWROK_N","PWREN_SGPIO_FCB_1_EN_N",
1539 "PWRGD_NW_BLADE3_PWROK_N","PWREN_SGPIO_FCB_4_EN_N",
1540 "PWRGD_NW_BLADE4_PWROK_N","PWREN_SGPIO_FCB_3_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1541 /*G0 - G7*/
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1542 "PWRGD_NW_BLADE5_PWROK_N","PWREN_SGPIO_FCB_5_EN_N",
1543 "PWRGD_NW_BLADE6_PWROK_N","PWREN_SGPIO_FCB_6_EN_N",
1544 "PWRGD_FCB_1","FM_BMC_RST_RTCRST_R",
1545 "PWRGD_FCB_2","",
1546 "PWRGD_FCB_3","FM_MDIO_SW_SEL",
1547 "PWRGD_FCB_4","FM_P24V_SMPWR_EN",
1548 "PWRGD_FCB_6","",
1549 "PWRGD_FCB_5","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1550 /*H0 - H7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1551 "LEAK_DETECT_MTIA_BLADE1_N","",
1552 "LEAK_DETECT_MTIA_BLADE2_N","",
1553 "LEAK_DETECT_MTIA_BLADE3_N","",
1554 "LEAK_DETECT_MTIA_BLADE4_N","",
1555 "LEAK_DETECT_MTIA_BLADE5_N","",
1556 "LEAK_DETECT_MTIA_BLADE6_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1557 "LEAK_DETECT_MTIA_BLADE7_N","ERR_INJECT_CMM_PWR_FAIL_N",
1558 "LEAK_DETECT_MTIA_BLADE8_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1559 /*I0 - I7*/
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1560 "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_5_N",
1561 "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_6_N",
1562 "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_4_N",
1563 "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_3_N",
1564 "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_2_N",
1565 "LEAK_DETECT_MTIA_BLADE14_N","RST_I2CRST_FCB_1_N",
1566 "LEAK_DETECT_MTIA_BLADE15_N","BMC_READY",
1567 "LEAK_DETECT_MTIA_BLADE16_N","FM_88E6393X_BIN_UPDATE_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1568 /*J0 - J7*/
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1569 "LEAK_DETECT_NW_BLADE1_N","WATER_VALVE_CLOSED_N",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1570 "LEAK_DETECT_NW_BLADE2_N","",
1571 "LEAK_DETECT_NW_BLADE3_N","",
1572 "LEAK_DETECT_NW_BLADE4_N","",
1573 "LEAK_DETECT_NW_BLADE5_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1574 "LEAK_DETECT_NW_BLADE6_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1575 "PWRGD_MTIA_BLADE1_HSC_PWROK_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1576 "PWRGD_MTIA_BLADE2_HSC_PWROK_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1577 /*K0 - K7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1578 "PWRGD_MTIA_BLADE3_HSC_PWROK_N","",
1579 "PWRGD_MTIA_BLADE4_HSC_PWROK_N","",
1580 "PWRGD_MTIA_BLADE5_HSC_PWROK_N","",
1581 "PWRGD_MTIA_BLADE6_HSC_PWROK_N","",
1582 "PWRGD_MTIA_BLADE7_HSC_PWROK_N","",
1583 "PWRGD_MTIA_BLADE8_HSC_PWROK_N","",
1584 "PWRGD_MTIA_BLADE9_HSC_PWROK_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1585 "PWRGD_MTIA_BLADE10_HSC_PWROK_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1586 /*L0 - L7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1587 "PWRGD_MTIA_BLADE11_HSC_PWROK_N","",
1588 "PWRGD_MTIA_BLADE12_HSC_PWROK_N","",
1589 "PWRGD_MTIA_BLADE13_HSC_PWROK_N","",
1590 "PWRGD_MTIA_BLADE14_HSC_PWROK_N","",
1591 "PWRGD_MTIA_BLADE15_HSC_PWROK_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1592 "PWRGD_MTIA_BLADE16_HSC_PWROK_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1593 "PWRGD_NW_BLADE1_HSC_PWROK_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1594 "PWRGD_NW_BLADE2_HSC_PWROK_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1595 /*M0 - M7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1596 "PWRGD_NW_BLADE3_HSC_PWROK_N","",
1597 "PWRGD_NW_BLADE4_HSC_PWROK_N","",
1598 "PWRGD_NW_BLADE5_HSC_PWROK_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1599 "PWRGD_NW_BLADE6_HSC_PWROK_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1600 "RPU_READY","",
1601 "IT_GEAR_RPU_LINK_N","",
1602 "IT_GEAR_LEAK","",
1603 "WATER_VALVE_CLOSED_N","",
1604 /*N0 - N7*/
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1605 "VALVE_STATUS_0","",
1606 "VALVE_STATUS_1","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1607 "PCA9555_IRQ1_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1608 "PCA9555_IRQ2_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1609 "CR_TOGGLE_BOOT_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1610 "IRQ_FCB_1_N","",
1611 "IRQ_FCB_2_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1612 "CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","",
1613 /*O0 - O7*/
1614 "CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","",
1615 "BOT_BCB_CABLE_PRSNT_N","",
1616 "TOP_BCB_CABLE_PRSNT_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1617 "IRQ_FCB_3_N","",
1618 "IRQ_FCB_4_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1619 "CHASSIS_LEAK0_DETECT_N","",
1620 "CHASSIS_LEAK1_DETECT_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1621 "PCA9555_IRQ3_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1622 /*P0 - P7*/
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1623 "PCA9555_IRQ4_N","",
1624 "PCA9555_IRQ5_N","",
1625 "CMM_AC_PWR_BTN_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1626 "RPU_READY_SPARE","",
1627 "IT_GEAR_LEAK_SPARE","",
1628 "IT_GEAR_RPU_LINK_SPARE_N","",
Tom Riniab06a532025-04-02 08:31:19 -0600[diff] [blame^]1629 "IRQ_FCB_6_N","",
1630 "IRQ_FCB_5_N","";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1631};