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git01.mediatek.com / filogic / uboot / 9c8af15f86b602d32dc0a1e638467c05b8792439 / . / src / arm / aspeed / aspeed-bmc-facebook-minerva.dts
blob: 41e2246cfbd1caf5c5eabbf6ca2ac683f12e9676 [file] [log] [blame]
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2023 Facebook Inc.
3/dts-v1/;
4
5#include "aspeed-g6.dtsi"
6#include <dt-bindings/gpio/aspeed-gpio.h>
7#include <dt-bindings/i2c/i2c.h>
8
9/ {
10 model = "Facebook Minerva CMM";
11 compatible = "facebook,minerva-cmc", "aspeed,ast2600";
12
13 aliases {
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]14 serial4 = &uart5;
15 serial5 = &uart6;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]16 /*
17 * PCA9548 (2-0077) provides 8 channels connecting to
18 * 6 pcs of FCB (Fan Controller Board).
19 */
20 i2c16 = &imux16;
21 i2c17 = &imux17;
22 i2c18 = &imux18;
23 i2c19 = &imux19;
24 i2c20 = &imux20;
25 i2c21 = &imux21;
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]26
27 spi1 = &spi_gpio;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]28 };
29
30 chosen {
31 stdout-path = "serial5:57600n8";
32 };
33
34 memory@80000000 {
35 device_type = "memory";
36 reg = <0x80000000 0x80000000>;
37 };
38
39 iio-hwmon {
40 compatible = "iio-hwmon";
41 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
42 <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
43 <&adc1 2>;
44 };
45
46 leds {
47 compatible = "gpio-leds";
48
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]49 led-0 {
50 label = "bmc_heartbeat_amber";
51 gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
52 linux,default-trigger = "heartbeat";
53 };
54
55 led-1 {
56 label = "fp_id_amber";
57 default-state = "off";
58 gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
59 };
60
61 led-2 {
62 label = "power_blue";
63 default-state = "off";
64 gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
65 };
66
67 led-3 {
68 label = "fan_status_led";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]69 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
70 default-state = "off";
71 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]72
73 led-4 {
74 label = "fan_fault_led_n";
75 gpios = <&leds_gpio 10 GPIO_ACTIVE_LOW>;
76 default-state = "off";
77 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]78 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]79
80 spi_gpio: spi {
81 status = "okay";
82 compatible = "spi-gpio";
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
87 mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
88 miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
89 num-chipselects = <1>;
90 cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
91
92 tpm@0 {
93 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
94 spi-max-frequency = <33000000>;
95 reg = <0>;
96 };
97 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]98};
99
100&uart6 {
101 status = "okay";
102};
103
104&wdt1 {
105 status = "okay";
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_wdtrst1_default>;
108 aspeed,reset-type = "soc";
109 aspeed,external-signal;
110 aspeed,ext-push-pull;
111 aspeed,ext-active-high;
112 aspeed,ext-pulse-duration = <256>;
113};
114
115&mac3 {
116 status = "okay";
117 phy-mode = "rmii";
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_rmii4_default>;
120 fixed-link {
121 speed = <100>;
122 full-duplex;
123 };
124};
125
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]126&mdio3 {
127 status = "okay";
128};
129
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]130&fmc {
131 status = "okay";
132 flash@0 {
133 status = "okay";
134 m25p,fast-read;
135 label = "bmc";
136 spi-max-frequency = <50000000>;
137#include "openbmc-flash-layout-128.dtsi"
138 };
139 flash@1 {
140 status = "okay";
141 m25p,fast-read;
142 label = "alt-bmc";
143 spi-max-frequency = <50000000>;
144 };
145};
146
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]147&sgpiom0 {
148 status = "okay";
149 ngpios = <128>;
150 bus-frequency = <2000000>;
151};
152
153&i2c0 {
154 status = "okay";
155
156 power-monitor@40 {
157 compatible = "ti,ina230";
158 reg = <0x40>;
159 shunt-resistor = <1000>;
160 };
161
162 power-monitor@41 {
163 compatible = "ti,ina230";
164 reg = <0x41>;
165 shunt-resistor = <1000>;
166 };
167
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]168 power-monitor@44 {
169 compatible = "lltc,ltc4287";
170 reg = <0x44>;
171 shunt-resistor-micro-ohms = <2000>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]172 };
173
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]174 power-monitor@43 {
175 compatible = "infineon,xdp710";
176 reg = <0x43>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]177 };
178
179 leds_gpio: gpio@19 {
180 compatible = "nxp,pca9555";
181 reg = <0x19>;
182 gpio-controller;
183 #gpio-cells = <2>;
184 };
185};
186
187&i2c1 {
188 status = "okay";
189
190 temperature-sensor@4b {
191 compatible = "ti,tmp75";
192 reg = <0x4b>;
193 };
194
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]195 temperature-sensor@4f {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]196 compatible = "ti,tmp75";
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]197 reg = <0x4f>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]198 };
199
200 eeprom@54 {
201 compatible = "atmel,24c128";
202 reg = <0x54>;
203 };
204};
205
206&i2c2 {
207 status = "okay";
208
209 i2c-mux@77 {
210 compatible = "nxp,pca9548";
211 reg = <0x77>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 i2c-mux-idle-disconnect;
215
216 imux16: i2c@0 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 reg = <0>;
220
221 eeprom@50 {
222 compatible = "atmel,24c128";
223 reg = <0x50>;
224 };
225
226 pwm@5e{
227 compatible = "max31790";
228 reg = <0x5e>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]232
233 power-sensor@40 {
234 compatible = "ti,ina238";
235 reg = <0x40>;
236 shunt-resistor = <1000>;
237 };
238
239 power-sensor@41 {
240 compatible = "ti,ina238";
241 reg = <0x41>;
242 shunt-resistor = <1000>;
243 };
244
245 power-sensor@44 {
246 compatible = "ti,ina238";
247 reg = <0x44>;
248 shunt-resistor = <1000>;
249 };
250
251 power-sensor@45 {
252 compatible = "ti,ina238";
253 reg = <0x45>;
254 shunt-resistor = <1000>;
255 };
256
257 temperature-sensor@4b {
258 compatible = "ti,tmp75";
259 reg = <0x4b>;
260 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]261 };
262
263 imux17: i2c@1 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 reg = <1>;
267
268 eeprom@50 {
269 compatible = "atmel,24c128";
270 reg = <0x50>;
271 };
272
273 pwm@5e{
274 compatible = "max31790";
275 reg = <0x5e>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]279
280 power-sensor@40 {
281 compatible = "ti,ina238";
282 reg = <0x40>;
283 shunt-resistor = <1000>;
284 };
285
286 power-sensor@41 {
287 compatible = "ti,ina238";
288 reg = <0x41>;
289 shunt-resistor = <1000>;
290 };
291
292 power-sensor@44 {
293 compatible = "ti,ina238";
294 reg = <0x44>;
295 shunt-resistor = <1000>;
296 };
297
298 power-sensor@45 {
299 compatible = "ti,ina238";
300 reg = <0x45>;
301 shunt-resistor = <1000>;
302 };
303
304 temperature-sensor@4b {
305 compatible = "ti,tmp75";
306 reg = <0x4b>;
307 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]308 };
309
310 imux18: i2c@2 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <2>;
314
315 eeprom@50 {
316 compatible = "atmel,24c128";
317 reg = <0x50>;
318 };
319
320 pwm@5e{
321 compatible = "max31790";
322 reg = <0x5e>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]326
327 power-sensor@40 {
328 compatible = "ti,ina238";
329 reg = <0x40>;
330 shunt-resistor = <1000>;
331 };
332
333 power-sensor@41 {
334 compatible = "ti,ina238";
335 reg = <0x41>;
336 shunt-resistor = <1000>;
337 };
338
339 power-sensor@44 {
340 compatible = "ti,ina238";
341 reg = <0x44>;
342 shunt-resistor = <1000>;
343 };
344
345 power-sensor@45 {
346 compatible = "ti,ina238";
347 reg = <0x45>;
348 shunt-resistor = <1000>;
349 };
350
351 temperature-sensor@4b {
352 compatible = "ti,tmp75";
353 reg = <0x4b>;
354 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]355 };
356
357 imux19: i2c@3 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 reg = <3>;
361
362 eeprom@50 {
363 compatible = "atmel,24c128";
364 reg = <0x50>;
365 };
366
367 pwm@5e{
368 compatible = "max31790";
369 reg = <0x5e>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]373
374 power-sensor@40 {
375 compatible = "ti,ina238";
376 reg = <0x40>;
377 shunt-resistor = <1000>;
378 };
379
380 power-sensor@41 {
381 compatible = "ti,ina238";
382 reg = <0x41>;
383 shunt-resistor = <1000>;
384 };
385
386 power-sensor@44 {
387 compatible = "ti,ina238";
388 reg = <0x44>;
389 shunt-resistor = <1000>;
390 };
391
392 power-sensor@45 {
393 compatible = "ti,ina238";
394 reg = <0x45>;
395 shunt-resistor = <1000>;
396 };
397
398 temperature-sensor@4b {
399 compatible = "ti,tmp75";
400 reg = <0x4b>;
401 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]402 };
403
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]404 imux20: i2c@5 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]405 #address-cells = <1>;
406 #size-cells = <0>;
407 reg = <4>;
408
409 eeprom@50 {
410 compatible = "atmel,24c128";
411 reg = <0x50>;
412 };
413
414 pwm@5e{
415 compatible = "max31790";
416 reg = <0x5e>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]420
421 power-sensor@40 {
422 compatible = "ti,ina238";
423 reg = <0x40>;
424 shunt-resistor = <1000>;
425 };
426
427 power-sensor@41 {
428 compatible = "ti,ina238";
429 reg = <0x41>;
430 shunt-resistor = <1000>;
431 };
432
433 power-sensor@44 {
434 compatible = "ti,ina238";
435 reg = <0x44>;
436 shunt-resistor = <1000>;
437 };
438
439 power-sensor@45 {
440 compatible = "ti,ina238";
441 reg = <0x45>;
442 shunt-resistor = <1000>;
443 };
444 temperature-sensor@4b {
445 compatible = "ti,tmp75";
446 reg = <0x4b>;
447 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]448 };
449
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]450 imux21: i2c@4 {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]451 #address-cells = <1>;
452 #size-cells = <0>;
453 reg = <5>;
454
455 eeprom@50 {
456 compatible = "atmel,24c128";
457 reg = <0x50>;
458 };
459
460 pwm@5e{
461 compatible = "max31790";
462 reg = <0x5e>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]466
467 power-sensor@40 {
468 compatible = "ti,ina238";
469 reg = <0x40>;
470 shunt-resistor = <1000>;
471 };
472
473 power-sensor@41 {
474 compatible = "ti,ina238";
475 reg = <0x41>;
476 shunt-resistor = <1000>;
477 };
478
479 power-sensor@44 {
480 compatible = "ti,ina238";
481 reg = <0x44>;
482 shunt-resistor = <1000>;
483 };
484
485 power-sensor@45 {
486 compatible = "ti,ina238";
487 reg = <0x45>;
488 shunt-resistor = <1000>;
489 };
490 temperature-sensor@4b {
491 compatible = "ti,tmp75";
492 reg = <0x4b>;
493 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]494 };
495 };
496};
497
498&i2c3 {
499 status = "okay";
500};
501
502&i2c4 {
503 status = "okay";
504};
505
506&i2c5 {
507 status = "okay";
508};
509
510&i2c6 {
511 status = "okay";
512};
513
514&i2c7 {
515 status = "okay";
516};
517
518&i2c8 {
519 status = "okay";
520};
521
522&i2c9 {
523 status = "okay";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]524
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]525 eeprom@50 {
526 compatible = "atmel,24c64";
527 reg = <0x50>;
528 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]529
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]530 rtc@51 {
531 compatible = "nxp,pcf8563";
532 reg = <0x51>;
533 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]534};
535
536&i2c12 {
537 status = "okay";
538};
539
540&i2c13 {
541 status = "okay";
542};
543
544&i2c14 {
545 status = "okay";
546 multi-master;
547
548 ipmb@10 {
549 compatible = "ipmb-dev";
550 reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
551 i2c-protocol;
552 };
553};
554
555&i2c15 {
556 status = "okay";
557
558 eeprom@50 {
559 compatible = "atmel,24c128";
560 reg = <0x50>;
561 };
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]562
563 eeprom@56 {
564 compatible = "atmel,24c64";
565 reg = <0x56>;
566 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]567};
568
569&adc0 {
570 aspeed,int-vref-microvolt = <2500000>;
571 status = "okay";
572 pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
573 &pinctrl_adc2_default &pinctrl_adc3_default
574 &pinctrl_adc4_default &pinctrl_adc5_default
575 &pinctrl_adc6_default &pinctrl_adc7_default>;
576};
577
578&adc1 {
579 aspeed,int-vref-microvolt = <2500000>;
580 status = "okay";
581 pinctrl-0 = <&pinctrl_adc10_default>;
582};
583
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]584&ehci0 {
585 status = "okay";
586};
587
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]588&ehci1 {
589 status = "okay";
590};
591
592&uhci {
593 status = "okay";
594};
595
596&gpio0 {
597 gpio-line-names =
598 /*A0-A7*/ "","","","","","","","",
599 /*B0-B7*/ "","","","","","","","",
600 /*C0-C7*/ "","","","","BLADE_UART_SEL2","","","",
601 /*D0-D7*/ "","","","","","","","",
602 /*E0-E7*/ "","","","","","","","",
603 /*F0-F7*/ "","","","","","","","",
604 /*G0-G7*/ "","","","","","","","",
605 /*H0-H7*/ "","","","","","","","",
606 /*I0-I7*/ "","","","","","","","",
607 /*J0-J7*/ "","","","","","","","",
608 /*K0-K7*/ "","","","","","","","",
609 /*L0-L7*/ "","","","","BLADE_UART_SEL0","","","",
610 /*M0-M7*/ "","","","","","BLADE_UART_SEL1","","",
611 /*N0-N7*/ "","","","","","","","",
612 /*O0-O7*/ "","","","","","","","",
613 /*P0-P7*/ "","","","","","","","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]614 /*Q0-Q7*/ "","","","","","power-chassis-control","","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]615 /*R0-R7*/ "","","","","","","","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]616 /*S0-S7*/ "","","","","","","","host0-ready",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]617 /*T0-T7*/ "","","","","","","","",
618 /*U0-U7*/ "","","","","","","","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]619 /*V0-V7*/ "","","","","BAT_DETECT","","power-chassis-good","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]620 /*W0-W7*/ "","","","","","","","",
621 /*X0-X7*/ "","","BLADE_UART_SEL3","","","","","",
622 /*Y0-Y7*/ "","","","","","","","",
623 /*Z0-Z7*/ "","","","","","","","";
624};
625
626&sgpiom0 {
627 gpio-line-names =
628 /*"input pin","output pin"*/
629 /*A0 - A7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]630 "PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N",
631 "PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N",
632 "PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N",
633 "PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N",
634 "PRSNT_MTIA_BLADE4_N","PWREN_MTIA_BLADE4_EN_N",
635 "PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N",
636 "PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N",
637 "PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]638 /*B0 - B7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]639 "PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N",
640 "PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N",
641 "PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N",
642 "PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N",
643 "PRSNT_MTIA_BLADE12_N","PWREN_MTIA_BLADE12_EN_N",
644 "PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N",
645 "PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N",
646 "PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]647 /*C0 - C7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]648 "PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N",
649 "PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N",
650 "PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N",
651 "PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N",
652 "PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N",
653 "PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N",
654 "PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N",
655 "PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]656 /*D0 - D7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]657 "PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N",
658 "PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N",
659 "PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N",
660 "PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N",
661 "PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N",
662 "PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N",
663 "PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N",
664 "PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]665 /*E0 - E7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]666 "PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N",
667 "PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N",
668 "PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N",
669 "PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N",
670 "PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N",
671 "PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N",
672 "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N",
673 "PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]674 /*F0 - F7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]675 "PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N",
676 "PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N",
677 "PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N",
678 "PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N",
679 "PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N",
680 "PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N",
681 "PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N",
682 "PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]683 /*G0 - G7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]684 "PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N",
685 "PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N",
686 "PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N",
687 "PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS",
688 "PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL",
689 "PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN",
690 "PWRGD_FCB_BOTTOM_1_PWROK_N","",
691 "PWRGD_FCB_BOTTOM_0_PWROK_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]692 /*H0 - H7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]693 "LEAK_DETECT_MTIA_BLADE0_N","",
694 "LEAK_DETECT_MTIA_BLADE1_N","",
695 "LEAK_DETECT_MTIA_BLADE2_N","",
696 "LEAK_DETECT_MTIA_BLADE3_N","",
697 "LEAK_DETECT_MTIA_BLADE4_N","",
698 "LEAK_DETECT_MTIA_BLADE5_N","",
699 "LEAK_DETECT_MTIA_BLADE6_N","",
700 "LEAK_DETECT_MTIA_BLADE7_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]701 /*I0 - I7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]702 "LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N",
703 "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N",
704 "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N",
705 "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N",
706 "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N",
707 "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N",
708 "LEAK_DETECT_MTIA_BLADE14_N","BMC_READY",
709 "LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]710 /*J0 - J7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]711 "LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N",
712 "LEAK_DETECT_NW_BLADE1_N","",
713 "LEAK_DETECT_NW_BLADE2_N","",
714 "LEAK_DETECT_NW_BLADE3_N","",
715 "LEAK_DETECT_NW_BLADE4_N","",
716 "LEAK_DETECT_NW_BLADE5_N","",
717 "PWRGD_MTIA_BLADE0_HSC_PWROK_N","",
718 "PWRGD_MTIA_BLADE1_HSC_PWROK_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]719 /*K0 - K7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]720 "PWRGD_MTIA_BLADE2_HSC_PWROK_N","",
721 "PWRGD_MTIA_BLADE3_HSC_PWROK_N","",
722 "PWRGD_MTIA_BLADE4_HSC_PWROK_N","",
723 "PWRGD_MTIA_BLADE5_HSC_PWROK_N","",
724 "PWRGD_MTIA_BLADE6_HSC_PWROK_N","",
725 "PWRGD_MTIA_BLADE7_HSC_PWROK_N","",
726 "PWRGD_MTIA_BLADE8_HSC_PWROK_N","",
727 "PWRGD_MTIA_BLADE9_HSC_PWROK_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]728 /*L0 - L7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]729 "PWRGD_MTIA_BLADE10_HSC_PWROK_N","",
730 "PWRGD_MTIA_BLADE11_HSC_PWROK_N","",
731 "PWRGD_MTIA_BLADE12_HSC_PWROK_N","",
732 "PWRGD_MTIA_BLADE13_HSC_PWROK_N","",
733 "PWRGD_MTIA_BLADE14_HSC_PWROK_N","",
734 "PWRGD_MTIA_BLADE15_HSC_PWROK_N","",
735 "PWRGD_NW_BLADE0_HSC_PWROK_N","",
736 "PWRGD_NW_BLADE1_HSC_PWROK_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]737 /*M0 - M7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]738 "PWRGD_NW_BLADE2_HSC_PWROK_N","",
739 "PWRGD_NW_BLADE3_HSC_PWROK_N","",
740 "PWRGD_NW_BLADE4_HSC_PWROK_N","",
741 "PWRGD_NW_BLADE5_HSC_PWROK_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]742 "RPU_READY","",
743 "IT_GEAR_RPU_LINK_N","",
744 "IT_GEAR_LEAK","",
745 "WATER_VALVE_CLOSED_N","",
746 /*N0 - N7*/
747 "VALVE_STS0","",
748 "VALVE_STS1","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]749 "PCA9555_IRQ0_N","",
750 "PCA9555_IRQ1_N","",
751 "CR_TOGGLE_BOOT_N","",
752 "IRQ_FCB_TOP0_N","",
753 "IRQ_FCB_TOP1_N","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]754 "CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","",
755 /*O0 - O7*/
756 "CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","",
757 "BOT_BCB_CABLE_PRSNT_N","",
758 "TOP_BCB_CABLE_PRSNT_N","",
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]759 "IRQ_FCB_MID0_N","",
760 "IRQ_FCB_MID1_N","",
761 "CHASSIS_LEAK0_DETECT_N","",
762 "CHASSIS_LEAK1_DETECT_N","",
763 "VALVE_RMON_A_1","",
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]764 /*P0 - P7*/
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame^]765 "VALVE_RMON_A_2","",
766 "VALVE_RMON_B_1","",
767 "VALVE_RMON_B_2","",
768 "RPU_READY_SPARE","",
769 "IT_GEAR_LEAK_SPARE","",
770 "IT_GEAR_RPU_LINK_SPARE_N","",
771 "IRQ_FCB_BOT0_N","",
772 "IRQ_FCB_BOT0_N","";
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]773};