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git01.mediatek.com / filogic / uboot / aad11b152f03bbc21e8e9a3a6de56ea05132d2ce / . / arch / arm / dts / vf-colibri.dtsi
blob: 9de4b28e8707ee99b11c6a95f22914de23c0cd3c [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]2/*
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]3 * Copyright 2014-2019 Toradex AG
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]4 */
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]5
6/dts-v1/;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]7#include "vf.dtsi"
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]8#include "vf610-pinfunc.h"
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]9
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]10/ {
11 chosen {
12 stdout-path = &uart0;
13 };
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]14
15 aliases {
16 usb0 = &ehci0; /* required for ums */
Igor Opaniuk7a6310a2019-06-10 14:47:51 +0300[diff] [blame]17 display1 = &dcu0;
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]18 };
19
20 reg_usbh_vbus: regulator-usbh-vbus {
21 compatible = "regulator-fixed";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_usbh1_reg>;
24 regulator-name = "VCC_USB[1-4]";
25 regulator-min-microvolt = <5000000>;
26 regulator-max-microvolt = <5000000>;
27 gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN */
28 };
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]29};
30
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]31&dspi1 {
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]32 bus-num = <1>;
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_dspi1>;
35 status = "okay";
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]36
37 spi_cmd: sspi@0 {
38 reg = <0>;
39 spi-max-frequency = <50000000>;
40 };
41};
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]42
Sanchayan Maity270666f2016-08-09 23:45:01 +0530[diff] [blame]43&ehci0 {
44 dr_mode = "otg";
45 fsl,cdet-gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
46 status = "okay";
47};
48
49&ehci1 {
50 dr_mode = "host";
51 status = "okay";
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]52 vbus-supply = <&reg_usbh_vbus>;
53};
54
55&esdhc1 {
56 bus-width = <4>;
57 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
58 disable-wp;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_esdhc1>;
61 status = "okay";
62};
63
Marcel Ziswilercb9e2842019-03-28 23:24:50 +0100[diff] [blame]64/* Ethernet */
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]65&fec1 {
66 phy-mode = "rmii";
Marcel Ziswilercb9e2842019-03-28 23:24:50 +0100[diff] [blame]67 phy-handle = <&ethphy1>;
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_fec1>;
70 status = "okay";
Marcel Ziswilercb9e2842019-03-28 23:24:50 +0100[diff] [blame]71
72 mdio {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 ethphy1: ethernet-phy@1 {
77 compatible = "ethernet-phy-ieee802.3-c22";
78 max-speed = <100>;
79 reg = <1>;
80 };
81 };
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]82};
83
84&i2c0 {
85 clock-frequency = <400000>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_i2c0>;
88 status = "okay";
89
90 /* M41T0M6 real time clock on carrier board */
91 rtc: m41t0m6@68 {
92 compatible = "st,m41t0";
93 reg = <0x68>;
94 };
95};
96
97&iomuxc {
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_ddr>;
100
101 pinctrl_ddr: ddrgrp {
102 fsl,pins = <
103 VF610_PAD_DDR_A15__DDR_A_15 0x180
104 VF610_PAD_DDR_A14__DDR_A_14 0x180
105 VF610_PAD_DDR_A13__DDR_A_13 0x180
106 VF610_PAD_DDR_A12__DDR_A_12 0x180
107 VF610_PAD_DDR_A11__DDR_A_11 0x180
108 VF610_PAD_DDR_A10__DDR_A_10 0x180
109 VF610_PAD_DDR_A9__DDR_A_9 0x180
110 VF610_PAD_DDR_A8__DDR_A_8 0x180
111 VF610_PAD_DDR_A7__DDR_A_7 0x180
112 VF610_PAD_DDR_A6__DDR_A_6 0x180
113 VF610_PAD_DDR_A5__DDR_A_5 0x180
114 VF610_PAD_DDR_A4__DDR_A_4 0x180
115 VF610_PAD_DDR_A3__DDR_A_3 0x180
116 VF610_PAD_DDR_A2__DDR_A_2 0x180
117 VF610_PAD_DDR_A1__DDR_A_1 0x180
118 VF610_PAD_DDR_A0__DDR_A_0 0x180
119 VF610_PAD_DDR_BA2__DDR_BA_2 0x180
120 VF610_PAD_DDR_BA1__DDR_BA_1 0x180
121 VF610_PAD_DDR_BA0__DDR_BA_0 0x180
122 VF610_PAD_DDR_CAS__DDR_CAS_B 0x180
123 VF610_PAD_DDR_CKE__DDR_CKE_0 0x180
124 VF610_PAD_DDR_CLK__DDR_CLK_0 0x180
125 VF610_PAD_DDR_CS__DDR_CS_B_0 0x180
126 VF610_PAD_DDR_D15__DDR_D_15 0x10180
127 VF610_PAD_DDR_D14__DDR_D_14 0x10180
128 VF610_PAD_DDR_D13__DDR_D_13 0x10180
129 VF610_PAD_DDR_D12__DDR_D_12 0x10180
130 VF610_PAD_DDR_D11__DDR_D_11 0x10180
131 VF610_PAD_DDR_D10__DDR_D_10 0x10180
132 VF610_PAD_DDR_D9__DDR_D_9 0x10180
133 VF610_PAD_DDR_D8__DDR_D_8 0x10180
134 VF610_PAD_DDR_D7__DDR_D_7 0x10180
135 VF610_PAD_DDR_D6__DDR_D_6 0x10180
136 VF610_PAD_DDR_D5__DDR_D_5 0x10180
137 VF610_PAD_DDR_D4__DDR_D_4 0x10180
138 VF610_PAD_DDR_D3__DDR_D_3 0x10180
139 VF610_PAD_DDR_D2__DDR_D_2 0x10180
140 VF610_PAD_DDR_D1__DDR_D_1 0x10180
141 VF610_PAD_DDR_D0__DDR_D_0 0x10180
142 VF610_PAD_DDR_DQM1__DDR_DQM_1 0x10180
143 VF610_PAD_DDR_DQM0__DDR_DQM_0 0x10180
144 VF610_PAD_DDR_DQS1__DDR_DQS_1 0x10180
145 VF610_PAD_DDR_DQS0__DDR_DQS_0 0x10180
146 VF610_PAD_DDR_RAS__DDR_RAS_B 0x180
147 VF610_PAD_DDR_WE__DDR_WE_B 0x180
148 VF610_PAD_DDR_ODT1__DDR_ODT_0 0x180
149 VF610_PAD_DDR_ODT0__DDR_ODT_1 0x180
150 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x180
151 VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x180
152 VF610_PAD_DDR_RESETB 0x180
153 >;
154 };
155
156 pinctrl_dspi1: dspi1grp {
157 fsl,pins = <
158 VF610_PAD_PTD5__DSPI1_CS0 0x33e2
159 VF610_PAD_PTD6__DSPI1_SIN 0x33e1
160 VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
161 VF610_PAD_PTD8__DSPI1_SCK 0x33e2
162 >;
163 };
164
165 pinctrl_esdhc1: esdhc1grp {
166 fsl,pins = <
167 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
168 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
169 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
170 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
171 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
172 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
173 VF610_PAD_PTB20__GPIO_42 0x219d
174 >;
175 };
176
177 pinctrl_fec1: fec1grp {
178 fsl,pins = <
179 VF610_PAD_PTA6__RMII_CLKOUT 0x30df
180 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30df
181 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df
182 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30df
183 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30df
184 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30df
185 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30df
186 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30df
187 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30df
188 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30df
189 >;
190 };
191
192 pinctrl_i2c0: i2c0grp {
193 fsl,pins = <
194 VF610_PAD_PTB14__I2C0_SCL 0x37ff
195 VF610_PAD_PTB15__I2C0_SDA 0x37ff
196 >;
197 };
198
199 pinctrl_nfc: nfcgrp {
200 fsl,pins = <
201 VF610_PAD_PTD23__NF_IO7 0x28df
202 VF610_PAD_PTD22__NF_IO6 0x28df
203 VF610_PAD_PTD21__NF_IO5 0x28df
204 VF610_PAD_PTD20__NF_IO4 0x28df
205 VF610_PAD_PTD19__NF_IO3 0x28df
206 VF610_PAD_PTD18__NF_IO2 0x28df
207 VF610_PAD_PTD17__NF_IO1 0x28df
208 VF610_PAD_PTD16__NF_IO0 0x28df
209 VF610_PAD_PTB24__NF_WE_B 0x28c2
210 VF610_PAD_PTB25__NF_CE0_B 0x28c2
211 VF610_PAD_PTB27__NF_RE_B 0x28c2
212 VF610_PAD_PTC26__NF_RB_B 0x283d
213 VF610_PAD_PTC27__NF_ALE 0x28c2
214 VF610_PAD_PTC28__NF_CLE 0x28c2
215 >;
216 };
217
218 pinctrl_uart0: uart0grp {
219 fsl,pins = <
220 VF610_PAD_PTB10__UART0_TX 0x11af
221 VF610_PAD_PTB11__UART0_RX 0x11af
222 VF610_PAD_PTB12__UART0_RTS 0x11af
223 VF610_PAD_PTB13__UART0_CTS 0x11af
224 >;
225 };
226
227 pinctrl_usbh1_reg: gpio_usb_vbus {
228 fsl,pins = <
229 VF610_PAD_PTD4__GPIO_83 0x22ed
230 >;
231 };
232};
233
234&nfc {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_nfc>;
237 status = "okay";
Sanchayan Maity270666f2016-08-09 23:45:01 +0530[diff] [blame]238};
239
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]240&uart0 {
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame]241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart0>;
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]243 status = "okay";
244};
Igor Opaniuk7a6310a2019-06-10 14:47:51 +0300[diff] [blame]245
246&dcu0 {
247 status = "okay";
248};