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git01.mediatek.com / filogic / uboot / 3d6a025b9c99d7d73c3ecaaa41942dd5bc36d228 / . / arch / arm / dts / vf-colibri.dtsi
blob: 5ce17076e9cecec0669d0ccba89e5787ed974d86 [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]2/*
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame^]3 * Copyright 2014-2019 Toradex AG
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]4 */
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame^]5
6/dts-v1/;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]7#include "vf.dtsi"
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame^]8#include "vf610-pinfunc.h"
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]9
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]10/ {
11 chosen {
12 stdout-path = &uart0;
13 };
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame^]14
15 aliases {
16 usb0 = &ehci0; /* required for ums */
17 };
18
19 reg_usbh_vbus: regulator-usbh-vbus {
20 compatible = "regulator-fixed";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_usbh1_reg>;
23 regulator-name = "VCC_USB[1-4]";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN */
27 };
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]28};
29
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]30&dspi1 {
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]31 bus-num = <1>;
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame^]32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_dspi1>;
34 status = "okay";
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]35
36 spi_cmd: sspi@0 {
37 reg = <0>;
38 spi-max-frequency = <50000000>;
39 };
40};
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]41
Sanchayan Maity270666f2016-08-09 23:45:01 +0530[diff] [blame]42&ehci0 {
43 dr_mode = "otg";
44 fsl,cdet-gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
45 status = "okay";
46};
47
48&ehci1 {
49 dr_mode = "host";
50 status = "okay";
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame^]51 vbus-supply = <&reg_usbh_vbus>;
52};
53
54&esdhc1 {
55 bus-width = <4>;
56 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
57 disable-wp;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_esdhc1>;
60 status = "okay";
61};
62
63&fec1 {
64 phy-mode = "rmii";
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_fec1>;
67 status = "okay";
68};
69
70&i2c0 {
71 clock-frequency = <400000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_i2c0>;
74 status = "okay";
75
76 /* M41T0M6 real time clock on carrier board */
77 rtc: m41t0m6@68 {
78 compatible = "st,m41t0";
79 reg = <0x68>;
80 };
81};
82
83&iomuxc {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_ddr>;
86
87 pinctrl_ddr: ddrgrp {
88 fsl,pins = <
89 VF610_PAD_DDR_A15__DDR_A_15 0x180
90 VF610_PAD_DDR_A14__DDR_A_14 0x180
91 VF610_PAD_DDR_A13__DDR_A_13 0x180
92 VF610_PAD_DDR_A12__DDR_A_12 0x180
93 VF610_PAD_DDR_A11__DDR_A_11 0x180
94 VF610_PAD_DDR_A10__DDR_A_10 0x180
95 VF610_PAD_DDR_A9__DDR_A_9 0x180
96 VF610_PAD_DDR_A8__DDR_A_8 0x180
97 VF610_PAD_DDR_A7__DDR_A_7 0x180
98 VF610_PAD_DDR_A6__DDR_A_6 0x180
99 VF610_PAD_DDR_A5__DDR_A_5 0x180
100 VF610_PAD_DDR_A4__DDR_A_4 0x180
101 VF610_PAD_DDR_A3__DDR_A_3 0x180
102 VF610_PAD_DDR_A2__DDR_A_2 0x180
103 VF610_PAD_DDR_A1__DDR_A_1 0x180
104 VF610_PAD_DDR_A0__DDR_A_0 0x180
105 VF610_PAD_DDR_BA2__DDR_BA_2 0x180
106 VF610_PAD_DDR_BA1__DDR_BA_1 0x180
107 VF610_PAD_DDR_BA0__DDR_BA_0 0x180
108 VF610_PAD_DDR_CAS__DDR_CAS_B 0x180
109 VF610_PAD_DDR_CKE__DDR_CKE_0 0x180
110 VF610_PAD_DDR_CLK__DDR_CLK_0 0x180
111 VF610_PAD_DDR_CS__DDR_CS_B_0 0x180
112 VF610_PAD_DDR_D15__DDR_D_15 0x10180
113 VF610_PAD_DDR_D14__DDR_D_14 0x10180
114 VF610_PAD_DDR_D13__DDR_D_13 0x10180
115 VF610_PAD_DDR_D12__DDR_D_12 0x10180
116 VF610_PAD_DDR_D11__DDR_D_11 0x10180
117 VF610_PAD_DDR_D10__DDR_D_10 0x10180
118 VF610_PAD_DDR_D9__DDR_D_9 0x10180
119 VF610_PAD_DDR_D8__DDR_D_8 0x10180
120 VF610_PAD_DDR_D7__DDR_D_7 0x10180
121 VF610_PAD_DDR_D6__DDR_D_6 0x10180
122 VF610_PAD_DDR_D5__DDR_D_5 0x10180
123 VF610_PAD_DDR_D4__DDR_D_4 0x10180
124 VF610_PAD_DDR_D3__DDR_D_3 0x10180
125 VF610_PAD_DDR_D2__DDR_D_2 0x10180
126 VF610_PAD_DDR_D1__DDR_D_1 0x10180
127 VF610_PAD_DDR_D0__DDR_D_0 0x10180
128 VF610_PAD_DDR_DQM1__DDR_DQM_1 0x10180
129 VF610_PAD_DDR_DQM0__DDR_DQM_0 0x10180
130 VF610_PAD_DDR_DQS1__DDR_DQS_1 0x10180
131 VF610_PAD_DDR_DQS0__DDR_DQS_0 0x10180
132 VF610_PAD_DDR_RAS__DDR_RAS_B 0x180
133 VF610_PAD_DDR_WE__DDR_WE_B 0x180
134 VF610_PAD_DDR_ODT1__DDR_ODT_0 0x180
135 VF610_PAD_DDR_ODT0__DDR_ODT_1 0x180
136 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x180
137 VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x180
138 VF610_PAD_DDR_RESETB 0x180
139 >;
140 };
141
142 pinctrl_dspi1: dspi1grp {
143 fsl,pins = <
144 VF610_PAD_PTD5__DSPI1_CS0 0x33e2
145 VF610_PAD_PTD6__DSPI1_SIN 0x33e1
146 VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
147 VF610_PAD_PTD8__DSPI1_SCK 0x33e2
148 >;
149 };
150
151 pinctrl_esdhc1: esdhc1grp {
152 fsl,pins = <
153 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
154 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
155 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
156 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
157 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
158 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
159 VF610_PAD_PTB20__GPIO_42 0x219d
160 >;
161 };
162
163 pinctrl_fec1: fec1grp {
164 fsl,pins = <
165 VF610_PAD_PTA6__RMII_CLKOUT 0x30df
166 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30df
167 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df
168 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30df
169 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30df
170 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30df
171 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30df
172 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30df
173 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30df
174 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30df
175 >;
176 };
177
178 pinctrl_i2c0: i2c0grp {
179 fsl,pins = <
180 VF610_PAD_PTB14__I2C0_SCL 0x37ff
181 VF610_PAD_PTB15__I2C0_SDA 0x37ff
182 >;
183 };
184
185 pinctrl_nfc: nfcgrp {
186 fsl,pins = <
187 VF610_PAD_PTD23__NF_IO7 0x28df
188 VF610_PAD_PTD22__NF_IO6 0x28df
189 VF610_PAD_PTD21__NF_IO5 0x28df
190 VF610_PAD_PTD20__NF_IO4 0x28df
191 VF610_PAD_PTD19__NF_IO3 0x28df
192 VF610_PAD_PTD18__NF_IO2 0x28df
193 VF610_PAD_PTD17__NF_IO1 0x28df
194 VF610_PAD_PTD16__NF_IO0 0x28df
195 VF610_PAD_PTB24__NF_WE_B 0x28c2
196 VF610_PAD_PTB25__NF_CE0_B 0x28c2
197 VF610_PAD_PTB27__NF_RE_B 0x28c2
198 VF610_PAD_PTC26__NF_RB_B 0x283d
199 VF610_PAD_PTC27__NF_ALE 0x28c2
200 VF610_PAD_PTC28__NF_CLE 0x28c2
201 >;
202 };
203
204 pinctrl_uart0: uart0grp {
205 fsl,pins = <
206 VF610_PAD_PTB10__UART0_TX 0x11af
207 VF610_PAD_PTB11__UART0_RX 0x11af
208 VF610_PAD_PTB12__UART0_RTS 0x11af
209 VF610_PAD_PTB13__UART0_CTS 0x11af
210 >;
211 };
212
213 pinctrl_usbh1_reg: gpio_usb_vbus {
214 fsl,pins = <
215 VF610_PAD_PTD4__GPIO_83 0x22ed
216 >;
217 };
218};
219
220&nfc {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_nfc>;
223 status = "okay";
Sanchayan Maity270666f2016-08-09 23:45:01 +0530[diff] [blame]224};
225
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]226&uart0 {
Marcel Ziswiler3d6a0252019-03-25 17:24:58 +0100[diff] [blame^]227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_uart0>;
Bhuvanchandra DV0e8ad892016-01-27 10:31:47 +0530[diff] [blame]229 status = "okay";
230};