Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 1 | /* |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 2 | * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 3 | * |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 4 | * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB |
| 5 | * |
| 6 | * Author: Tor Krill tor@excito.com |
| 7 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <pci.h> |
| 13 | #include <usb.h> |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 14 | #include <asm/io.h> |
Mateusz Kulikowski | 3add69e | 2016-03-31 23:12:23 +0200 | [diff] [blame] | 15 | #include <usb/ehci-ci.h> |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 16 | #include <hwconfig.h> |
Nikhil Badola | 76c2f2e | 2014-09-30 11:22:43 +0530 | [diff] [blame] | 17 | #include <fsl_usb.h> |
Nikhil Badola | b6fd44c | 2014-10-20 16:50:49 +0530 | [diff] [blame] | 18 | #include <fdt_support.h> |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 19 | |
Jean-Christophe PLAGNIOL-VILLARD | 8f6bcf4 | 2009-04-03 12:46:58 +0200 | [diff] [blame] | 20 | #include "ehci.h" |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 21 | |
Nikhil Badola | b6fd44c | 2014-10-20 16:50:49 +0530 | [diff] [blame] | 22 | #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT |
| 23 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| 24 | #endif |
| 25 | |
Nikhil Badola | b0b48da | 2014-04-07 08:46:14 +0530 | [diff] [blame] | 26 | static void set_txfifothresh(struct usb_ehci *, u32); |
| 27 | |
Shengzhou Liu | d407e1f | 2012-10-22 13:18:24 +0800 | [diff] [blame] | 28 | /* Check USB PHY clock valid */ |
| 29 | static int usb_phy_clk_valid(struct usb_ehci *ehci) |
| 30 | { |
| 31 | if (!((in_be32(&ehci->control) & PHY_CLK_VALID) || |
| 32 | in_be32(&ehci->prictrl))) { |
| 33 | printf("USB PHY clock invalid!\n"); |
| 34 | return 0; |
| 35 | } else { |
| 36 | return 1; |
| 37 | } |
| 38 | } |
| 39 | |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 40 | /* |
| 41 | * Create the appropriate control structures to manage |
| 42 | * a new EHCI host controller. |
| 43 | * |
| 44 | * Excerpts from linux ehci fsl driver. |
| 45 | */ |
Troy Kisky | 7d6bbb9 | 2013-10-10 15:27:57 -0700 | [diff] [blame] | 46 | int ehci_hcd_init(int index, enum usb_init_type init, |
| 47 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 48 | { |
ramneek mehresh | 16b0806 | 2013-09-12 16:35:49 +0530 | [diff] [blame] | 49 | struct usb_ehci *ehci = NULL; |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 50 | const char *phy_type = NULL; |
| 51 | size_t len; |
Nikhil Badola | eb97e25 | 2013-12-19 11:08:46 +0530 | [diff] [blame] | 52 | char current_usb_controller[5]; |
Kumar Gala | 7b83c35 | 2011-11-09 10:04:15 -0600 | [diff] [blame] | 53 | #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 54 | char usb_phy[5]; |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 55 | |
| 56 | usb_phy[0] = '\0'; |
Kumar Gala | 7b83c35 | 2011-11-09 10:04:15 -0600 | [diff] [blame] | 57 | #endif |
Nikhil Badola | 2613cfc | 2014-02-26 17:43:15 +0530 | [diff] [blame] | 58 | if (has_erratum_a007075()) { |
| 59 | /* |
| 60 | * A 5ms delay is needed after applying soft-reset to the |
| 61 | * controller to let external ULPI phy come out of reset. |
| 62 | * This delay needs to be added before re-initializing |
| 63 | * the controller after soft-resetting completes |
| 64 | */ |
| 65 | mdelay(5); |
| 66 | } |
Nikhil Badola | eb97e25 | 2013-12-19 11:08:46 +0530 | [diff] [blame] | 67 | memset(current_usb_controller, '\0', 5); |
| 68 | snprintf(current_usb_controller, 4, "usb%d", index+1); |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 69 | |
ramneek mehresh | 16b0806 | 2013-09-12 16:35:49 +0530 | [diff] [blame] | 70 | switch (index) { |
| 71 | case 0: |
| 72 | ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; |
| 73 | break; |
| 74 | case 1: |
| 75 | ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; |
| 76 | break; |
| 77 | default: |
| 78 | printf("ERROR: wrong controller index!!\n"); |
Nikhil Badola | 16e6cf0 | 2015-06-07 12:28:04 +0530 | [diff] [blame] | 79 | return -EINVAL; |
ramneek mehresh | 16b0806 | 2013-09-12 16:35:49 +0530 | [diff] [blame] | 80 | }; |
| 81 | |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 82 | *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); |
| 83 | *hcor = (struct ehci_hcor *)((uint32_t) *hccr + |
| 84 | HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 85 | |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 86 | /* Set to Host mode */ |
Vivek Mahajan | 32c5220 | 2009-06-19 17:56:00 +0530 | [diff] [blame] | 87 | setbits_le32(&ehci->usbmode, CM_HOST); |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 88 | |
Vivek Mahajan | 32c5220 | 2009-06-19 17:56:00 +0530 | [diff] [blame] | 89 | out_be32(&ehci->snoop1, SNOOP_SIZE_2GB); |
| 90 | out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 91 | |
| 92 | /* Init phy */ |
Nikhil Badola | eb97e25 | 2013-12-19 11:08:46 +0530 | [diff] [blame] | 93 | if (hwconfig_sub(current_usb_controller, "phy_type")) |
| 94 | phy_type = hwconfig_subarg(current_usb_controller, |
| 95 | "phy_type", &len); |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 96 | else |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 97 | phy_type = getenv("usb_phy_type"); |
| 98 | |
| 99 | if (!phy_type) { |
| 100 | #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 101 | /* if none specified assume internal UTMI */ |
| 102 | strcpy(usb_phy, "utmi"); |
| 103 | phy_type = usb_phy; |
| 104 | #else |
| 105 | printf("WARNING: USB phy type not defined !!\n"); |
| 106 | return -1; |
| 107 | #endif |
| 108 | } |
| 109 | |
Nikhil Badola | 09a3b56 | 2014-02-17 16:58:36 +0530 | [diff] [blame] | 110 | if (!strncmp(phy_type, "utmi", 4)) { |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 111 | #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) |
Nikhil Badola | 369f663 | 2014-05-08 17:05:26 +0530 | [diff] [blame] | 112 | clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, |
| 113 | PHY_CLK_SEL_UTMI); |
| 114 | clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, |
| 115 | UTMI_PHY_EN); |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 116 | udelay(1000); /* delay required for PHY Clk to appear */ |
| 117 | #endif |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 118 | out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); |
Nikhil Badola | 369f663 | 2014-05-08 17:05:26 +0530 | [diff] [blame] | 119 | clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, |
| 120 | USB_EN); |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 121 | } else { |
Nikhil Badola | 369f663 | 2014-05-08 17:05:26 +0530 | [diff] [blame] | 122 | clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, |
| 123 | PHY_CLK_SEL_ULPI); |
| 124 | clrsetbits_be32(&ehci->control, UTMI_PHY_EN | |
| 125 | CONTROL_REGISTER_W1C_MASK, USB_EN); |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 126 | udelay(1000); /* delay required for PHY Clk to appear */ |
Shengzhou Liu | d407e1f | 2012-10-22 13:18:24 +0800 | [diff] [blame] | 127 | if (!usb_phy_clk_valid(ehci)) |
| 128 | return -EINVAL; |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 129 | out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); |
Ramneek Mehresh | 3fb68ee | 2011-03-23 15:20:43 +0530 | [diff] [blame] | 130 | } |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 131 | |
Vivek Mahajan | 32c5220 | 2009-06-19 17:56:00 +0530 | [diff] [blame] | 132 | out_be32(&ehci->prictrl, 0x0000000c); |
| 133 | out_be32(&ehci->age_cnt_limit, 0x00000040); |
| 134 | out_be32(&ehci->sictrl, 0x00000001); |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 135 | |
Vivek Mahajan | 32c5220 | 2009-06-19 17:56:00 +0530 | [diff] [blame] | 136 | in_le32(&ehci->usbmode); |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 137 | |
Nikhil Badola | 67f4b26 | 2014-10-17 09:12:07 +0530 | [diff] [blame] | 138 | if (has_erratum_a007798()) |
Nikhil Badola | b0b48da | 2014-04-07 08:46:14 +0530 | [diff] [blame] | 139 | set_txfifothresh(ehci, TXFIFOTHRESH); |
| 140 | |
Nikhil Badola | 288542c | 2014-11-21 17:25:21 +0530 | [diff] [blame] | 141 | if (has_erratum_a004477()) { |
| 142 | /* |
| 143 | * When reset is issued while any ULPI transaction is ongoing |
| 144 | * then it may result to corruption of ULPI Function Control |
| 145 | * Register which eventually causes phy clock to enter low |
| 146 | * power mode which stops the clock. Thus delay is required |
| 147 | * before reset to let ongoing ULPI transaction complete. |
| 148 | */ |
| 149 | udelay(1); |
| 150 | } |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | /* |
| 155 | * Destroy the appropriate control structures corresponding |
| 156 | * the the EHCI host controller. |
| 157 | */ |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 158 | int ehci_hcd_stop(int index) |
Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 159 | { |
| 160 | return 0; |
| 161 | } |
Nikhil Badola | b0b48da | 2014-04-07 08:46:14 +0530 | [diff] [blame] | 162 | |
| 163 | /* |
| 164 | * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register |
| 165 | * to counter DDR latencies in writing data into Tx buffer. |
| 166 | * This prevents Tx buffer from getting underrun |
| 167 | */ |
| 168 | static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) |
| 169 | { |
| 170 | u32 cmd; |
| 171 | cmd = ehci_readl(&ehci->txfilltuning); |
| 172 | cmd &= ~TXFIFO_THRESH_MASK; |
| 173 | cmd |= TXFIFO_THRESH(txfifo_thresh); |
| 174 | ehci_writel(&ehci->txfilltuning, cmd); |
| 175 | } |