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Michael Trimarchie30a3362008-11-28 13:22:09 +01001/*
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +05302 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
Vivek Mahajan288f7fb2009-05-25 17:23:16 +05303 *
Michael Trimarchie30a3362008-11-28 13:22:09 +01004 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
5 *
6 * Author: Tor Krill tor@excito.com
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Michael Trimarchie30a3362008-11-28 13:22:09 +01009 */
10
11#include <common.h>
12#include <pci.h>
13#include <usb.h>
Michael Trimarchie30a3362008-11-28 13:22:09 +010014#include <asm/io.h>
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020015#include <usb/ehci-ci.h>
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +053016#include <hwconfig.h>
Nikhil Badola76c2f2e2014-09-30 11:22:43 +053017#include <fsl_usb.h>
Nikhil Badolab6fd44c2014-10-20 16:50:49 +053018#include <fdt_support.h>
Michael Trimarchie30a3362008-11-28 13:22:09 +010019
Jean-Christophe PLAGNIOL-VILLARD8f6bcf42009-04-03 12:46:58 +020020#include "ehci.h"
Michael Trimarchie30a3362008-11-28 13:22:09 +010021
Nikhil Badolab6fd44c2014-10-20 16:50:49 +053022#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
23#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
24#endif
25
Nikhil Badolab0b48da2014-04-07 08:46:14 +053026static void set_txfifothresh(struct usb_ehci *, u32);
27
Shengzhou Liud407e1f2012-10-22 13:18:24 +080028/* Check USB PHY clock valid */
29static int usb_phy_clk_valid(struct usb_ehci *ehci)
30{
31 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
32 in_be32(&ehci->prictrl))) {
33 printf("USB PHY clock invalid!\n");
34 return 0;
35 } else {
36 return 1;
37 }
38}
39
Michael Trimarchie30a3362008-11-28 13:22:09 +010040/*
41 * Create the appropriate control structures to manage
42 * a new EHCI host controller.
43 *
44 * Excerpts from linux ehci fsl driver.
45 */
Troy Kisky7d6bbb92013-10-10 15:27:57 -070046int ehci_hcd_init(int index, enum usb_init_type init,
47 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Michael Trimarchie30a3362008-11-28 13:22:09 +010048{
ramneek mehresh16b08062013-09-12 16:35:49 +053049 struct usb_ehci *ehci = NULL;
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +053050 const char *phy_type = NULL;
51 size_t len;
Nikhil Badolaeb97e252013-12-19 11:08:46 +053052 char current_usb_controller[5];
Kumar Gala7b83c352011-11-09 10:04:15 -060053#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
54 char usb_phy[5];
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +053055
56 usb_phy[0] = '\0';
Kumar Gala7b83c352011-11-09 10:04:15 -060057#endif
Nikhil Badola2613cfc2014-02-26 17:43:15 +053058 if (has_erratum_a007075()) {
59 /*
60 * A 5ms delay is needed after applying soft-reset to the
61 * controller to let external ULPI phy come out of reset.
62 * This delay needs to be added before re-initializing
63 * the controller after soft-resetting completes
64 */
65 mdelay(5);
66 }
Nikhil Badolaeb97e252013-12-19 11:08:46 +053067 memset(current_usb_controller, '\0', 5);
68 snprintf(current_usb_controller, 4, "usb%d", index+1);
Michael Trimarchie30a3362008-11-28 13:22:09 +010069
ramneek mehresh16b08062013-09-12 16:35:49 +053070 switch (index) {
71 case 0:
72 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
73 break;
74 case 1:
75 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
76 break;
77 default:
78 printf("ERROR: wrong controller index!!\n");
Nikhil Badola16e6cf02015-06-07 12:28:04 +053079 return -EINVAL;
ramneek mehresh16b08062013-09-12 16:35:49 +053080 };
81
Lucas Stach3494a4c2012-09-26 00:14:35 +020082 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
83 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
84 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Michael Trimarchie30a3362008-11-28 13:22:09 +010085
Michael Trimarchie30a3362008-11-28 13:22:09 +010086 /* Set to Host mode */
Vivek Mahajan32c52202009-06-19 17:56:00 +053087 setbits_le32(&ehci->usbmode, CM_HOST);
Michael Trimarchie30a3362008-11-28 13:22:09 +010088
Vivek Mahajan32c52202009-06-19 17:56:00 +053089 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
90 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
Michael Trimarchie30a3362008-11-28 13:22:09 +010091
92 /* Init phy */
Nikhil Badolaeb97e252013-12-19 11:08:46 +053093 if (hwconfig_sub(current_usb_controller, "phy_type"))
94 phy_type = hwconfig_subarg(current_usb_controller,
95 "phy_type", &len);
Vivek Mahajan288f7fb2009-05-25 17:23:16 +053096 else
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +053097 phy_type = getenv("usb_phy_type");
98
99 if (!phy_type) {
100#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
101 /* if none specified assume internal UTMI */
102 strcpy(usb_phy, "utmi");
103 phy_type = usb_phy;
104#else
105 printf("WARNING: USB phy type not defined !!\n");
106 return -1;
107#endif
108 }
109
Nikhil Badola09a3b562014-02-17 16:58:36 +0530110 if (!strncmp(phy_type, "utmi", 4)) {
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530111#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
Nikhil Badola369f6632014-05-08 17:05:26 +0530112 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
113 PHY_CLK_SEL_UTMI);
114 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
115 UTMI_PHY_EN);
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530116 udelay(1000); /* delay required for PHY Clk to appear */
117#endif
Lucas Stach3494a4c2012-09-26 00:14:35 +0200118 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
Nikhil Badola369f6632014-05-08 17:05:26 +0530119 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
120 USB_EN);
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530121 } else {
Nikhil Badola369f6632014-05-08 17:05:26 +0530122 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
123 PHY_CLK_SEL_ULPI);
124 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
125 CONTROL_REGISTER_W1C_MASK, USB_EN);
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530126 udelay(1000); /* delay required for PHY Clk to appear */
Shengzhou Liud407e1f2012-10-22 13:18:24 +0800127 if (!usb_phy_clk_valid(ehci))
128 return -EINVAL;
Lucas Stach3494a4c2012-09-26 00:14:35 +0200129 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530130 }
Michael Trimarchie30a3362008-11-28 13:22:09 +0100131
Vivek Mahajan32c52202009-06-19 17:56:00 +0530132 out_be32(&ehci->prictrl, 0x0000000c);
133 out_be32(&ehci->age_cnt_limit, 0x00000040);
134 out_be32(&ehci->sictrl, 0x00000001);
Michael Trimarchie30a3362008-11-28 13:22:09 +0100135
Vivek Mahajan32c52202009-06-19 17:56:00 +0530136 in_le32(&ehci->usbmode);
Michael Trimarchie30a3362008-11-28 13:22:09 +0100137
Nikhil Badola67f4b262014-10-17 09:12:07 +0530138 if (has_erratum_a007798())
Nikhil Badolab0b48da2014-04-07 08:46:14 +0530139 set_txfifothresh(ehci, TXFIFOTHRESH);
140
Nikhil Badola288542c2014-11-21 17:25:21 +0530141 if (has_erratum_a004477()) {
142 /*
143 * When reset is issued while any ULPI transaction is ongoing
144 * then it may result to corruption of ULPI Function Control
145 * Register which eventually causes phy clock to enter low
146 * power mode which stops the clock. Thus delay is required
147 * before reset to let ongoing ULPI transaction complete.
148 */
149 udelay(1);
150 }
Michael Trimarchie30a3362008-11-28 13:22:09 +0100151 return 0;
152}
153
154/*
155 * Destroy the appropriate control structures corresponding
156 * the the EHCI host controller.
157 */
Lucas Stach3494a4c2012-09-26 00:14:35 +0200158int ehci_hcd_stop(int index)
Michael Trimarchie30a3362008-11-28 13:22:09 +0100159{
160 return 0;
161}
Nikhil Badolab0b48da2014-04-07 08:46:14 +0530162
163/*
164 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
165 * to counter DDR latencies in writing data into Tx buffer.
166 * This prevents Tx buffer from getting underrun
167 */
168static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
169{
170 u32 cmd;
171 cmd = ehci_readl(&ehci->txfilltuning);
172 cmd &= ~TXFIFO_THRESH_MASK;
173 cmd |= TXFIFO_THRESH(txfifo_thresh);
174 ehci_writel(&ehci->txfilltuning, cmd);
175}