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git01.mediatek.com / filogic / uboot / aa60336798d431e54cd3e554380f1b296139ce63 / . / drivers / lan91c96.h
blob: 3ac58bce20fbf1ad3309fe284e8d546be6b8a958 [file] [log] [blame]
wdenkaa603362003-05-12 21:50:16 +0000[diff] [blame^]1/*------------------------------------------------------------------------
2 * lan91c96.h
3 *
4 * (C) Copyright 2002
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Rolf Offermanns <rof@sysgo.de>
7 * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
8 * Developed by Simple Network Magic Corporation (SNMC)
9 * Copyright (C) 1996 by Erik Stahlman (ES)
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * This file contains register information and access macros for
26 * the LAN91C96 single chip ethernet controller. It is a modified
27 * version of the smc9111.h file.
28 *
29 * Information contained in this file was obtained from the LAN91C96
30 * manual from SMC. To get a copy, if you really want one, you can find
31 * information under www.smsc.com.
32 *
33 * Authors
34 * Erik Stahlman ( erik@vt.edu )
35 * Daris A Nevil ( dnevil@snmc.com )
36 *
37 * History
38 * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version)
39 * for lan91c96
40 *-------------------------------------------------------------------------
41 */
42#ifndef _LAN91C96_H_
43#define _LAN91C96_H_
44
45#include <asm/types.h>
46#include <asm/io.h>
47#include <config.h>
48
49/*
50 * This function may be called by the board specific initialisation code
51 * in order to override the default mac address.
52 */
53
54void smc_set_mac_addr(const char *addr);
55int eth_hw_init(void);
56
57
58/* I want some simple types */
59
60typedef unsigned char byte;
61typedef unsigned short word;
62typedef unsigned long int dword;
63
64/*
65 * DEBUGGING LEVELS
66 *
67 * 0 for normal operation
68 * 1 for slightly more details
69 * >2 for various levels of increasingly useless information
70 * 2 for interrupt tracking, status flags
71 * 3 for packet info
72 * 4 for complete packet dumps
73 */
74/*#define SMC_DEBUG 0 */
75
76/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
77
78#define SMC_IO_EXTENT 16
79
80#ifdef CONFIG_PXA250
81
82#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+( r * 4 ))))
83#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+( r * 4 ))))
84#define SMC_inb(p) ({ \
85 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p * 4)); \
86 unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
87 if (__p & 1) __v >>= 8; \
88 else __v &= 0xff; \
89 __v; })
90
91#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r * 4))) = d)
92#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r * 4))) = d)
93#define SMC_outb(d,r) ({ word __d = (byte)(d); \
94 word __w = SMC_inw((r)&~1); \
95 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
96 __w |= ((r)&1) ? __d<<8 : __d; \
97 SMC_outw(__w,(r)&~1); \
98 })
99
100#define SMC_outsl(r,b,l) ({ int __i; \
101 dword *__b2; \
102 __b2 = (dword *) b; \
103 for (__i = 0; __i < l; __i++) { \
104 SMC_outl( *(__b2 + __i), r ); \
105 } \
106 })
107
108#define SMC_outsw(r,b,l) ({ int __i; \
109 word *__b2; \
110 __b2 = (word *) b; \
111 for (__i = 0; __i < l; __i++) { \
112 SMC_outw( *(__b2 + __i), r ); \
113 } \
114 })
115
116#define SMC_insl(r,b,l) ({ int __i ; \
117 dword *__b2; \
118 __b2 = (dword *) b; \
119 for (__i = 0; __i < l; __i++) { \
120 *(__b2 + __i) = SMC_inl(r); \
121 SMC_inl(0); \
122 }; \
123 })
124
125#define SMC_insw(r,b,l) ({ int __i ; \
126 word *__b2; \
127 __b2 = (word *) b; \
128 for (__i = 0; __i < l; __i++) { \
129 *(__b2 + __i) = SMC_inw(r); \
130 SMC_inw(0); \
131 }; \
132 })
133
134#define SMC_insb(r,b,l) ({ int __i ; \
135 byte *__b2; \
136 __b2 = (byte *) b; \
137 for (__i = 0; __i < l; __i++) { \
138 *(__b2 + __i) = SMC_inb(r); \
139 SMC_inb(0); \
140 }; \
141 })
142
143#else /* if not CONFIG_PXA250 */
144
145/*
146 * We have only 16 Bit PCMCIA access on Socket 0
147 */
148
149#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
150#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
151
152#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
153#define SMC_outb(d,r) ({ word __d = (byte)(d); \
154 word __w = SMC_inw((r)&~1); \
155 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
156 __w |= ((r)&1) ? __d<<8 : __d; \
157 SMC_outw(__w,(r)&~1); \
158 })
159#if 0
160#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l))
161#else
162#define SMC_outsw(r,b,l) ({ int __i; \
163 word *__b2; \
164 __b2 = (word *) b; \
165 for (__i = 0; __i < l; __i++) { \
166 SMC_outw( *(__b2 + __i), r); \
167 } \
168 })
169#endif
170
171#if 0
172#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l))
173#else
174#define SMC_insw(r,b,l) ({ int __i ; \
175 word *__b2; \
176 __b2 = (word *) b; \
177 for (__i = 0; __i < l; __i++) { \
178 *(__b2 + __i) = SMC_inw(r); \
179 SMC_inw(0); \
180 }; \
181 })
182#endif
183
184#endif
185
186/*
187 ****************************************************************************
188 * Bank Select Field
189 ****************************************************************************
190 */
191#define LAN91C96_BANK_SELECT 14 // Bank Select Register
192#define LAN91C96_BANKSELECT (0x3UC << 0)
193#define BANK0 0x00
194#define BANK1 0x01
195#define BANK2 0x02
196#define BANK3 0x03
197#define BANK4 0x04
198
199/*
200 ****************************************************************************
201 * EEPROM Addresses.
202 ****************************************************************************
203 */
204#define EEPROM_MAC_OFFSET_1 0x6020
205#define EEPROM_MAC_OFFSET_2 0x6021
206#define EEPROM_MAC_OFFSET_3 0x6022
207
208/*
209 ****************************************************************************
210 * Bank 0 Register Map in I/O Space
211 ****************************************************************************
212 */
213#define LAN91C96_TCR 0 // Transmit Control Register
214#define LAN91C96_EPH_STATUS 2 // EPH Status Register
215#define LAN91C96_RCR 4 // Receive Control Register
216#define LAN91C96_COUNTER 6 // Counter Register
217#define LAN91C96_MIR 8 // Memory Information Register
218#define LAN91C96_MCR 10 // Memory Configuration Register
219
220/*
221 ****************************************************************************
222 * Transmit Control Register - Bank 0 - Offset 0
223 ****************************************************************************
224 */
225#define LAN91C96_TCR_TXENA (0x1U << 0)
226#define LAN91C96_TCR_LOOP (0x1U << 1)
227#define LAN91C96_TCR_FORCOL (0x1U << 2)
228#define LAN91C96_TCR_TXP_EN (0x1U << 3)
229#define LAN91C96_TCR_PAD_EN (0x1U << 7)
230#define LAN91C96_TCR_NOCRC (0x1U << 8)
231#define LAN91C96_TCR_MON_CSN (0x1U << 10)
232#define LAN91C96_TCR_FDUPLX (0x1U << 11)
233#define LAN91C96_TCR_STP_SQET (0x1U << 12)
234#define LAN91C96_TCR_EPH_LOOP (0x1U << 13)
235#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)
236#define LAN91C96_TCR_FDSE (0x1U << 15)
237
238/*
239 ****************************************************************************
240 * EPH Status Register - Bank 0 - Offset 2
241 ****************************************************************************
242 */
243#define LAN91C96_EPHSR_TX_SUC (0x1U << 0)
244#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)
245#define LAN91C96_EPHSR_MUL_COL (0x1U << 2)
246#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)
247#define LAN91C96_EPHSR_16COL (0x1U << 4)
248#define LAN91C96_EPHSR_SQET (0x1U << 5)
249#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)
250#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)
251#define LAN91C96_EPHSR_WAKEUP (0x1U << 8)
252#define LAN91C96_EPHSR_LATCOL (0x1U << 9)
253#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)
254#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)
255#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)
256
257#define LAN91C96_EPHSR_LINK_OK (0x1U << 14)
258#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)
259
260#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \
261 LAN91C96_EPHSR_MUL_COL | \
262 LAN91C96_EPHSR_16COL | \
263 LAN91C96_EPHSR_SQET | \
264 LAN91C96_EPHSR_TX_DEFR | \
265 LAN91C96_EPHSR_LATCOL | \
266 LAN91C96_EPHSR_LOST_CARR | \
267 LAN91C96_EPHSR_EXC_DEF | \
268 LAN91C96_EPHSR_LINK_OK | \
269 LAN91C96_EPHSR_TX_UNRN)
270
271/*
272 ****************************************************************************
273 * Receive Control Register - Bank 0 - Offset 4
274 ****************************************************************************
275 */
276#define LAN91C96_RCR_RX_ABORT (0x1U << 0)
277#define LAN91C96_RCR_PRMS (0x1U << 1)
278#define LAN91C96_RCR_ALMUL (0x1U << 2)
279#define LAN91C96_RCR_RXEN (0x1U << 8)
280#define LAN91C96_RCR_STRIP_CRC (0x1U << 9)
281#define LAN91C96_RCR_FILT_CAR (0x1U << 14)
282#define LAN91C96_RCR_SOFT_RST (0x1U << 15)
283
284/*
285 ****************************************************************************
286 * Counter Register - Bank 0 - Offset 6
287 ****************************************************************************
288 */
289#define LAN91C96_ECR_SNGL_COL (0xFU << 0)
290#define LAN91C96_ECR_MULT_COL (0xFU << 5)
291#define LAN91C96_ECR_DEF_TX (0xFU << 8)
292#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)
293
294/*
295 ****************************************************************************
296 * Memory Information Register - Bank 0 - OFfset 8
297 ****************************************************************************
298 */
299#define LAN91C96_MIR_SIZE (0x18 << 0) // 6144 bytes
300
301/*
302 ****************************************************************************
303 * Memory Configuration Register - Bank 0 - Offset 10
304 ****************************************************************************
305 */
306#define LAN91C96_MCR_MEM_RES (0xFFU << 0)
307#define LAN91C96_MCR_MEM_MULT (0x3U << 9)
308#define LAN91C96_MCR_HIGH_ID (0x3U << 12)
309
310#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
311
312/*
313 ****************************************************************************
314 * Bank 1 Register Map in I/O Space
315 ****************************************************************************
316 */
317#define LAN91C96_CONFIG 0 // Configuration Register
318#define LAN91C96_BASE 2 // Base Address Register
319#define LAN91C96_IA0 4 // Individual Address Register - 0
320#define LAN91C96_IA1 5 // Individual Address Register - 1
321#define LAN91C96_IA2 6 // Individual Address Register - 2
322#define LAN91C96_IA3 7 // Individual Address Register - 3
323#define LAN91C96_IA4 8 // Individual Address Register - 4
324#define LAN91C96_IA5 9 // Individual Address Register - 5
325#define LAN91C96_GEN_PURPOSE 10 // General Address Registers
326#define LAN91C96_CONTROL 12 // Control Register
327
328/*
329 ****************************************************************************
330 * Configuration Register - Bank 1 - Offset 0
331 ****************************************************************************
332 */
333#define LAN91C96_CR_INT_SEL0 (0x1U << 1)
334#define LAN91C96_CR_INT_SEL1 (0x1U << 2)
335#define LAN91C96_CR_RES (0x3U << 3)
336#define LAN91C96_CR_DIS_LINK (0x1U << 6)
337#define LAN91C96_CR_16BIT (0x1U << 7)
338#define LAN91C96_CR_AUI_SELECT (0x1U << 8)
339#define LAN91C96_CR_SET_SQLCH (0x1U << 9)
340#define LAN91C96_CR_FULL_STEP (0x1U << 10)
341#define LAN91C96_CR_NO_WAIT (0x1U << 12)
342
343/*
344 ****************************************************************************
345 * Base Address Register - Bank 1 - Offset 2
346 ****************************************************************************
347 */
348#define LAN91C96_BAR_RA_BITS (0x27U << 0)
349#define LAN91C96_BAR_ROM_SIZE (0x1U << 6)
350#define LAN91C96_BAR_A_BITS (0xFFU << 8)
351
352/*
353 ****************************************************************************
354 * Control Register - Bank 1 - Offset 12
355 ****************************************************************************
356 */
357#define LAN91C96_CTR_STORE (0x1U << 0)
358#define LAN91C96_CTR_RELOAD (0x1U << 1)
359#define LAN91C96_CTR_EEPROM (0x1U << 2)
360#define LAN91C96_CTR_TE_ENABLE (0x1U << 5)
361#define LAN91C96_CTR_CR_ENABLE (0x1U << 6)
362#define LAN91C96_CTR_LE_ENABLE (0x1U << 7)
363#define LAN91C96_CTR_BIT_8 (0x1U << 8)
364#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
365#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)
366#define LAN91C96_CTR_PWRDN (0x1U << 13)
367#define LAN91C96_CTR_RCV_BAD (0x1U << 14)
368
369/*
370 ****************************************************************************
371 * Bank 2 Register Map in I/O Space
372 ****************************************************************************
373 */
374#define LAN91C96_MMU 0 // MMU Command Register
375#define LAN91C96_AUTO_TX_START 1 // Auto Tx Start Register
376#define LAN91C96_PNR 2 // Packet Number Register
377#define LAN91C96_ARR 3 // Allocation Result Register
378#define LAN91C96_FIFO 4 // FIFO Ports Register
379#define LAN91C96_POINTER 6 // Pointer Register
380#define LAN91C96_DATA_HIGH 8 // Data High Register
381#define LAN91C96_DATA_LOW 10 // Data Low Register
382#define LAN91C96_INT_STATS 12 // Interrupt Status Register - RO
383#define LAN91C96_INT_ACK 12 // Interrupt Acknowledge Register -WO
384#define LAN91C96_INT_MASK 13 // Interrupt Mask Register
385
386/*
387 ****************************************************************************
388 * MMU Command Register - Bank 2 - Offset 0
389 ****************************************************************************
390 */
391#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)
392#define LAN91C96_MMUCR_N1 (0x1U << 1)
393#define LAN91C96_MMUCR_N2 (0x1U << 2)
394#define LAN91C96_MMUCR_COMMAND (0xFU << 4)
395#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) // WXYZ = 0010
396#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) // WXYZ = 0100
397#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) // WXYZ = 0110
398#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) // WXYZ = 0111
399#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) // WXYZ = 1000
400#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) // WXYZ = 1010
401#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) // WXYZ = 1100
402#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) // WXYZ = 1110
403
404/*
405 ****************************************************************************
406 * Auto Tx Start Register - Bank 2 - Offset 1
407 ****************************************************************************
408 */
409#define LAN91C96_AUTOTX (0xFFU << 0)
410
411/*
412 ****************************************************************************
413 * Packet Number Register - Bank 2 - Offset 2
414 ****************************************************************************
415 */
416#define LAN91C96_PNR_TX (0x1FU << 0)
417
418/*
419 ****************************************************************************
420 * Allocation Result Register - Bank 2 - Offset 3
421 ****************************************************************************
422 */
423#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)
424#define LAN91C96_ARR_FAILED (0x1U << 7)
425
426/*
427 ****************************************************************************
428 * FIFO Ports Register - Bank 2 - Offset 4
429 ****************************************************************************
430 */
431#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)
432#define LAN91C96_FIFO_TEMPTY (0x1U << 7)
433#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)
434#define LAN91C96_FIFO_RXEMPTY (0x1U << 15)
435
436/*
437 ****************************************************************************
438 * Pointer Register - Bank 2 - Offset 6
439 ****************************************************************************
440 */
441#define LAN91C96_PTR_LOW (0xFFU << 0)
442#define LAN91C96_PTR_HIGH (0x7U << 8)
443#define LAN91C96_PTR_AUTO_TX (0x1U << 11)
444#define LAN91C96_PTR_ETEN (0x1U << 12)
445#define LAN91C96_PTR_READ (0x1U << 13)
446#define LAN91C96_PTR_AUTO_INCR (0x1U << 14)
447#define LAN91C96_PTR_RCV (0x1U << 15)
448
449#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \
450 LAN91C96_PTR_AUTO_INCR | \
451 LAN91C96_PTR_READ)
452
453/*
454 ****************************************************************************
455 * Data Register - Bank 2 - Offset 8
456 ****************************************************************************
457 */
458#define LAN91C96_CONTROL_CRC (0x1U << 4) // CRC bit
459#define LAN91C96_CONTROL_ODD (0x1U << 5) // ODD bit
460
461/*
462 ****************************************************************************
463 * Interrupt Status Register - Bank 2 - Offset 12
464 ****************************************************************************
465 */
466#define LAN91C96_IST_RCV_INT (0x1U << 0)
467#define LAN91C96_IST_TX_INT (0x1U << 1)
468#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
469#define LAN91C96_IST_ALLOC_INT (0x1U << 3)
470#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)
471#define LAN91C96_IST_EPH_INT (0x1U << 5)
472#define LAN91C96_IST_ERCV_INT (0x1U << 6)
473#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)
474
475/*
476 ****************************************************************************
477 * Interrupt Acknowledge Register - Bank 2 - Offset 12
478 ****************************************************************************
479 */
480#define LAN91C96_ACK_TX_INT (0x1U << 1)
481#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
482#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)
483#define LAN91C96_ACK_ERCV_INT (0x1U << 6)
484
485/*
486 ****************************************************************************
487 * Interrupt Mask Register - Bank 2 - Offset 13
488 ****************************************************************************
489 */
490#define LAN91C96_MSK_RCV_INT (0x1U << 0)
491#define LAN91C96_MSK_TX_INT (0x1U << 1)
492#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
493#define LAN91C96_MSK_ALLOC_INT (0x1U << 3)
494#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)
495#define LAN91C96_MSK_EPH_INT (0x1U << 5)
496#define LAN91C96_MSK_ERCV_INT (0x1U << 6)
497#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)
498
499/*
500 ****************************************************************************
501 * Bank 3 Register Map in I/O Space
502 **************************************************************************
503 */
504#define LAN91C96_MGMT_MDO (0x1U << 0)
505#define LAN91C96_MGMT_MDI (0x1U << 1)
506#define LAN91C96_MGMT_MCLK (0x1U << 2)
507#define LAN91C96_MGMT_MDOE (0x1U << 3)
508#define LAN91C96_MGMT_LOW_ID (0x3U << 4)
509#define LAN91C96_MGMT_IOS0 (0x1U << 8)
510#define LAN91C96_MGMT_IOS1 (0x1U << 9)
511#define LAN91C96_MGMT_IOS2 (0x1U << 10)
512#define LAN91C96_MGMT_nXNDEC (0x1U << 11)
513#define LAN91C96_MGMT_HIGH_ID (0x3U << 12)
514
515/*
516 ****************************************************************************
517 * Revision Register - Bank 3 - Offset 10
518 ****************************************************************************
519 */
520#define LAN91C96_REV_REVID (0xFU << 0)
521#define LAN91C96_REV_CHIPID (0xFU << 4)
522
523/*
524 ****************************************************************************
525 * Early RCV Register - Bank 3 - Offset 12
526 ****************************************************************************
527 */
528#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)
529#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)
530
531/*
532 ****************************************************************************
533 * PCMCIA Configuration Registers
534 ****************************************************************************
535 */
536#define LAN91C96_ECOR 0x8000 // Ethernet Configuration Register
537#define LAN91C96_ECSR 0x8002 // Ethernet Configuration and Status
538
539/*
540 ****************************************************************************
541 * PCMCIA Ethernet Configuration Option Register (ECOR)
542 ****************************************************************************
543 */
544#define LAN91C96_ECOR_ENABLE (0x1U << 0)
545#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)
546#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)
547#define LAN91C96_ECOR_SRESET (0x1U << 7)
548
549/*
550 ****************************************************************************
551 * PCMCIA Ethernet Configuration and Status Register (ECSR)
552 ****************************************************************************
553 */
554#define LAN91C96_ECSR_INTR (0x1U << 1)
555#define LAN91C96_ECSR_PWRDWN (0x1U << 2)
556#define LAN91C96_ECSR_IOIS8 (0x1U << 5)
557
558/*
559 ****************************************************************************
560 * Receive Frame Status Word - See page 38 of the LAN91C96 specification.
561 ****************************************************************************
562 */
563#define LAN91C96_TOO_SHORT (0x1U << 10)
564#define LAN91C96_TOO_LONG (0x1U << 11)
565#define LAN91C96_ODD_FRM (0x1U << 12)
566#define LAN91C96_BAD_CRC (0x1U << 13)
567#define LAN91C96_BROD_CAST (0x1U << 14)
568#define LAN91C96_ALGN_ERR (0x1U << 15)
569
570#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR)
571
572/*
573 ****************************************************************************
574 * Default MAC Address
575 ****************************************************************************
576 */
577#define MAC_DEF_HI 0x0800
578#define MAC_DEF_MED 0x3333
579#define MAC_DEF_LO 0x0100
580
581/*
582 ****************************************************************************
583 * Default I/O Signature - 0x33
584 ****************************************************************************
585 */
586#define LAN91C96_LOW_SIGNATURE (0x33U << 0)
587#define LAN91C96_HIGH_SIGNATURE (0x33U << 8)
588#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
589
590#define LAN91C96_MAX_PAGES 6 // Maximum number of 256 pages.
591#define ETHERNET_MAX_LENGTH 1514
592
593
594
595/*-------------------------------------------------------------------------
596 * I define some macros to make it easier to do somewhat common
597 * or slightly complicated, repeated tasks.
598 *-------------------------------------------------------------------------
599 */
600
601/* select a register bank, 0 to 3 */
602
603#define SMC_SELECT_BANK(x) { SMC_outw( x, LAN91C96_BANK_SELECT ); }
604
605/* this enables an interrupt in the interrupt mask register */
606#define SMC_ENABLE_INT(x) {\
607 unsigned char mask;\
608 SMC_SELECT_BANK(2);\
609 mask = SMC_inb( LAN91C96_INT_MASK );\
610 mask |= (x);\
611 SMC_outb( mask, LAN91C96_INT_MASK ); \
612}
613
614/* this disables an interrupt from the interrupt mask register */
615
616#define SMC_DISABLE_INT(x) {\
617 unsigned char mask;\
618 SMC_SELECT_BANK(2);\
619 mask = SMC_inb( LAN91C96_INT_MASK );\
620 mask &= ~(x);\
621 SMC_outb( mask, LAN91C96_INT_MASK ); \
622}
623
624/*----------------------------------------------------------------------
625 * Define the interrupts that I want to receive from the card
626 *
627 * I want:
628 * LAN91C96_IST_EPH_INT, for nasty errors
629 * LAN91C96_IST_RCV_INT, for happy received packets
630 * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
631 *-------------------------------------------------------------------------
632 */
633#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
634
635#endif /* _LAN91C96_H_ */