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Yuantian Tang92f18ff2019-04-10 16:43:34 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2019-2021 NXP
Yuantian Tang92f18ff2019-04-10 16:43:34 +08004 */
5
6#ifndef __L1028A_COMMON_H
7#define __L1028A_COMMON_H
8
9#define CONFIG_REMAKE_ELF
Yuantian Tang92f18ff2019-04-10 16:43:34 +080010#define CONFIG_MP
11
12#include <asm/arch/stream_id_lsch3.h>
13#include <asm/arch/config.h>
14#include <asm/arch/soc.h>
15
16/* Link Definitions */
17#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20
21#define CONFIG_VERY_BIG_RAM
22#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
23#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
24#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
25#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
26#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
27
Yuantian Tang92f18ff2019-04-10 16:43:34 +080028/*
29 * SMP Definitinos
30 */
Michael Wallef056e0f2020-06-01 21:53:26 +020031#define CPU_RELEASE_ADDR secondary_boot_addr
Yuantian Tang92f18ff2019-04-10 16:43:34 +080032
33/* Generic Timer Definitions */
34#define COUNTER_FREQUENCY 25000000 /* 25MHz */
35
36/* Size of malloc() pool */
37#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
38
Biwen Lie7c3b042021-02-05 19:01:57 +080039/* GPIO */
40#ifdef CONFIG_DM_GPIO
41#ifndef CONFIG_MPC8XXX_GPIO
42#define CONFIG_MPC8XXX_GPIO
43#endif
44#endif
45
Yuantian Tang92f18ff2019-04-10 16:43:34 +080046/* I2C */
Igor Opaniukf7c91762021-02-09 13:52:45 +020047#if !CONFIG_IS_ENABLED(DM_I2C)
Yuantian Tang92f18ff2019-04-10 16:43:34 +080048#define CONFIG_SYS_I2C
Chuanhua Haneaf4a7c2019-07-10 21:16:49 +080049#endif
Yuantian Tang92f18ff2019-04-10 16:43:34 +080050
51/* Serial Port */
Yuantian Tang92f18ff2019-04-10 16:43:34 +080052#define CONFIG_SYS_NS16550_SERIAL
53#define CONFIG_SYS_NS16550_REG_SIZE 1
54#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
55
Yuantian Tang92f18ff2019-04-10 16:43:34 +080056#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
57
58/* Miscellaneous configurable options */
59#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
60
61/* Physical Memory Map */
62#define CONFIG_CHIP_SELECTS_PER_CTRL 4
63
64#define CONFIG_HWCONFIG
65#define HWCONFIG_BUFFER_SIZE 128
66
Yuantian Tang92f18ff2019-04-10 16:43:34 +080067#define BOOT_TARGET_DEVICES(func) \
68 func(MMC, mmc, 0) \
Yuantian Tang7f3da7b2019-11-04 15:10:45 +080069 func(MMC, mmc, 1) \
Yuantian Tang7a224e72020-03-10 11:31:05 +080070 func(USB, usb, 0) \
71 func(DHCP, dhcp, na)
Yuantian Tang92f18ff2019-04-10 16:43:34 +080072#include <config_distro_bootcmd.h>
73
Yuantian Tang92f18ff2019-04-10 16:43:34 +080074#undef CONFIG_BOOTCOMMAND
75
Yuantian Tang7f3da7b2019-11-04 15:10:45 +080076#define XSPI_NOR_BOOTCOMMAND \
77 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
78 "env exists secureboot && esbc_halt;;"
Yuantian Tang92f18ff2019-04-10 16:43:34 +080079#define SD_BOOTCOMMAND \
Yuantian Tang7f3da7b2019-11-04 15:10:45 +080080 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
81 "env exists secureboot && esbc_halt;"
82#define SD2_BOOTCOMMAND \
83 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
Yuantian Tang92f18ff2019-04-10 16:43:34 +080084 "env exists secureboot && esbc_halt;"
85
86/* Monitor Command Prompt */
87#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
88#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
89 sizeof(CONFIG_SYS_PROMPT) + 16)
90#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
91
Yuantian Tang92f18ff2019-04-10 16:43:34 +080092#define CONFIG_SYS_MAXARGS 64 /* max command args */
93
94#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
95
Yuantian Tang92f18ff2019-04-10 16:43:34 +080096#define OCRAM_NONSECURE_SIZE 0x00010000
Yuantian Tang92f18ff2019-04-10 16:43:34 +080097#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
Yuantian Tang92f18ff2019-04-10 16:43:34 +080098
99#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
100
Yuantian Tang92f18ff2019-04-10 16:43:34 +0800101/* I2C bus multiplexer */
102#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
103#define I2C_MUX_CH_DEFAULT 0x8
104
105/* EEPROM */
106#define CONFIG_ID_EEPROM
107#define CONFIG_SYS_I2C_EEPROM_NXID
108#define CONFIG_SYS_EEPROM_BUS_NUM 0
109#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
110#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
111#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
112#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
113
Wen He41e63db2019-11-18 13:26:09 +0800114/* DisplayPort */
115#define DP_PWD_EN_DEFAULT_MASK 0x8
116
Udit Agarwal22ec2382019-11-07 16:11:32 +0000117#ifdef CONFIG_NXP_ESBC
Yuantian Tang029d8ab2019-05-24 14:36:27 +0800118#include <asm/fsl_secure_boot.h>
119#endif
120
Alex Marginean3a918732019-07-03 12:11:39 +0300121/* Ethernet */
122/* smallest ENETC BD ring has 8 entries */
123#define CONFIG_SYS_RX_ETH_BUFFER 8
124
Yuantian Tang92f18ff2019-04-10 16:43:34 +0800125#endif /* __L1028A_COMMON_H */