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git01.mediatek.com / filogic / uboot / 7977d66e7027f6bb4c0eec61324cfa2bc378f916 / . / drivers / spi / Kconfig
blob: 16dce77c04f53ba0068e945b4c71172efc58a9be [file] [log] [blame]
Jagan Tekibfd3f8b2015-06-27 22:35:14 +0530[diff] [blame]1menu "SPI Support"
2
Masahiro Yamada57ad8ee2014-10-23 22:26:09 +0900[diff] [blame]3config DM_SPI
4 bool "Enable Driver Model for SPI drivers"
5 depends on DM
6 help
Simon Glassd8b771d2015-02-05 21:41:35 -0700[diff] [blame]7 Enable driver model for SPI. The SPI slave interface
8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9 the SPI uclass. Drivers provide methods to access the SPI
10 buses that they control. The uclass interface is defined in
11 include/spi.h. The existing spi_slave structure is attached
12 as 'parent data' to every slave on each bus. Slaves
13 typically use driver-private data instead of extending the
14 spi_slave structure.
Simon Glass4b322d32015-03-06 13:19:05 -0700[diff] [blame]15
Jagan Teki15a932c2015-06-27 22:37:00 +0530[diff] [blame]16if DM_SPI
17
18config CADENCE_QSPI
19 bool "Cadence QSPI driver"
20 help
21 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
22 used to access the SPI NOR flash on platforms embedding this
23 Cadence IP core.
24
25config DESIGNWARE_SPI
26 bool "Designware SPI driver"
27 help
28 Enable the Designware SPI driver. This driver can be used to
29 access the SPI NOR flash on platforms embedding this Designware
30 IP core.
31
Jagan Teki6274bf92015-06-27 15:32:19 +0530[diff] [blame]32config EXYNOS_SPI
33 bool "Samsung Exynos SPI driver"
34 help
35 Enable the Samsung Exynos SPI driver. This driver can be used to
36 access the SPI NOR flash on platforms embedding this Samsung
37 Exynos IP core.
38
Jagan Tekiae30c022015-06-27 14:17:06 +0530[diff] [blame]39config FSL_DSPI
40 bool "Freescale DSPI driver"
41 help
42 Enable the Freescale DSPI driver. This driver can be used to
43 access the SPI NOR flash and SPI Data flash on platforms embedding
44 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
45 use this driver.
46
Jagan Teki0e9be242015-06-27 15:23:07 +0530[diff] [blame]47config FSL_QSPI
48 bool "Freescale QSPI driver"
49 help
50 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
51 used to access the SPI NOR flash on platforms embedding this
52 Freescale IP core.
53
Jagan Teki3872b7c2015-06-27 15:43:27 +0530[diff] [blame]54config ICH_SPI
55 bool "Intel ICH SPI driver"
56 help
57 Enable the Intel ICH SPI driver. This driver can be used to
58 access the SPI NOR flash on platforms embedding this Intel
59 ICH IP core.
60
Simon Glass4b322d32015-03-06 13:19:05 -0700[diff] [blame]61config SANDBOX_SPI
62 bool "Sandbox SPI driver"
63 depends on SANDBOX && DM
64 help
65 Enable SPI support for sandbox. This is an emulation of a real SPI
66 bus. Devices can be attached to the bus using the device tree
67 which specifies the driver to use. As an example, see this device
68 tree fragment from sandbox.dts. It shows that the SPI bus has a
69 single flash device on chip select 0 which is emulated by the driver
70 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
71
72 spi@0 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 reg = <0>;
76 compatible = "sandbox,spi";
77 cs-gpios = <0>, <&gpio_a 0>;
78 flash@0 {
79 reg = <0>;
80 compatible = "spansion,m25p16", "sandbox,spi-flash";
81 spi-max-frequency = <40000000>;
82 sandbox,filename = "spi.bin";
83 };
Jagan Teki15a932c2015-06-27 22:37:00 +0530[diff] [blame]84 };
Jagan Tekidd32f512015-06-27 04:41:11 +0530[diff] [blame]85
Jagan Teki7977d662015-06-27 15:57:53 +0530[diff] [blame^]86config TEGRA114_SPI
87 bool "nVidia Tegra114 SPI driver"
88 help
89 Enable the nVidia Tegra114 SPI driver. This driver can be used to
90 access the SPI NOR flash on platforms embedding this nVidia Tegra114
91 IP core.
92
93 This controller is different than the older SoCs SPI controller and
94 also register interface get changed with this controller.
95
Jagan Tekicd70d7d2015-06-27 04:32:43 +0530[diff] [blame]96config XILINX_SPI
97 bool "Xilinx SPI driver"
Jagan Tekicd70d7d2015-06-27 04:32:43 +0530[diff] [blame]98 help
99 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
100 controller support 8 bit SPI transfers only, with or w/o FIFO.
101 For more info on Xilinx SPI Register Definitions and Overview
102 see driver file - drivers/spi/xilinx_spi.c
103
Jagan Tekicad526f2015-06-27 00:51:38 +0530[diff] [blame]104config ZYNQ_SPI
105 bool "Zynq SPI driver"
Jagan Teki15a932c2015-06-27 22:37:00 +0530[diff] [blame]106 depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
Jagan Tekicad526f2015-06-27 00:51:38 +0530[diff] [blame]107 help
108 Enable the Zynq SPI driver. This driver can be used to
109 access the SPI NOR flash on platforms embedding this Zynq
110 SPI IP core.
Jagan Tekibfd3f8b2015-06-27 22:35:14 +0530[diff] [blame]111
Jagan Teki15a932c2015-06-27 22:37:00 +0530[diff] [blame]112endif # if DM_SPI
113
Jagan Tekia0497a32015-06-27 15:21:36 +0530[diff] [blame]114config FSL_ESPI
115 bool "Freescale eSPI driver"
116 help
117 Enable the Freescale eSPI driver. This driver can be used to
118 access the SPI interface and SPI NOR flash on platforms embedding
119 this Freescale eSPI IP core.
120
Jagan Teki15a932c2015-06-27 22:37:00 +0530[diff] [blame]121config TI_QSPI
122 bool "TI QSPI driver"
123 help
124 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
125 This driver support spi flash single, quad and memory reads.
126
Jagan Tekibfd3f8b2015-06-27 22:35:14 +0530[diff] [blame]127endmenu # menu "SPI Support"