blob: 8837f5c122e781a6bcb05f928a030b16dd1480ef [file] [log] [blame]
wdenk5d3207d2002-08-21 22:08:56 +00001/*
Michal Simek15d654c2013-04-22 15:43:02 +02002 * (C) Copyright 2012-2013, Xilinx, Michal Simek
3 *
wdenk5d3207d2002-08-21 22:08:56 +00004 * (C) Copyright 2002
5 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
6 * Keith Outwater, keith_outwater@mvis.com
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk5d3207d2002-08-21 22:08:56 +00009 */
10
11/*
12 * Xilinx FPGA support
13 */
14
15#include <common.h>
Michal Simek6ff890d2013-04-26 15:04:48 +020016#include <fpga.h>
wdenk5d3207d2002-08-21 22:08:56 +000017#include <virtex2.h>
18#include <spartan2.h>
Wolfgang Denkc38e70c2005-09-25 16:44:21 +020019#include <spartan3.h>
Michal Simek15d654c2013-04-22 15:43:02 +020020#include <zynqpl.h>
wdenk5d3207d2002-08-21 22:08:56 +000021
wdenk5d3207d2002-08-21 22:08:56 +000022/* Local Static Functions */
Michal Simek25e1e2e2014-03-13 12:49:21 +010023static int xilinx_validate(xilinx_desc *desc, char *fn);
wdenk5d3207d2002-08-21 22:08:56 +000024
25/* ------------------------------------------------------------------------- */
26
Michal Simek78617b42013-05-01 19:02:02 +020027int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
Michal Simekcd5a1cf2013-04-26 13:12:07 +020028{
29 unsigned int length;
30 unsigned int swapsize;
31 char buffer[80];
32 unsigned char *dataptr;
33 unsigned int i;
Michal Simek6ff890d2013-04-26 15:04:48 +020034 const fpga_desc *desc;
Michal Simek25e1e2e2014-03-13 12:49:21 +010035 xilinx_desc *xdesc;
Michal Simekcd5a1cf2013-04-26 13:12:07 +020036
37 dataptr = (unsigned char *)fpgadata;
Michal Simek6ff890d2013-04-26 15:04:48 +020038 /* Find out fpga_description */
39 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
40 /* Assign xilinx device description */
41 xdesc = desc->devdesc;
Michal Simekcd5a1cf2013-04-26 13:12:07 +020042
43 /* skip the first bytes of the bitsteam, their meaning is unknown */
44 length = (*dataptr << 8) + *(dataptr + 1);
45 dataptr += 2;
46 dataptr += length;
47
48 /* get design name (identifier, length, string) */
49 length = (*dataptr << 8) + *(dataptr + 1);
50 dataptr += 2;
51 if (*dataptr++ != 0x61) {
52 debug("%s: Design name id not recognized in bitstream\n",
53 __func__);
54 return FPGA_FAIL;
55 }
56
57 length = (*dataptr << 8) + *(dataptr + 1);
58 dataptr += 2;
59 for (i = 0; i < length; i++)
60 buffer[i] = *dataptr++;
61
62 printf(" design filename = \"%s\"\n", buffer);
63
64 /* get part number (identifier, length, string) */
65 if (*dataptr++ != 0x62) {
66 printf("%s: Part number id not recognized in bitstream\n",
67 __func__);
68 return FPGA_FAIL;
69 }
70
71 length = (*dataptr << 8) + *(dataptr + 1);
72 dataptr += 2;
73 for (i = 0; i < length; i++)
74 buffer[i] = *dataptr++;
Michal Simek6ff890d2013-04-26 15:04:48 +020075
76 if (xdesc->name) {
77 i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
78 if (i) {
79 printf("%s: Wrong bitstream ID for this device\n",
80 __func__);
81 printf("%s: Bitstream ID %s, current device ID %d/%s\n",
82 __func__, buffer, devnum, xdesc->name);
83 return FPGA_FAIL;
84 }
85 } else {
Michal Simek25e1e2e2014-03-13 12:49:21 +010086 printf("%s: Please fill correct device ID to xilinx_desc\n",
Michal Simek6ff890d2013-04-26 15:04:48 +020087 __func__);
88 }
Michal Simekcd5a1cf2013-04-26 13:12:07 +020089 printf(" part number = \"%s\"\n", buffer);
90
91 /* get date (identifier, length, string) */
92 if (*dataptr++ != 0x63) {
93 printf("%s: Date identifier not recognized in bitstream\n",
94 __func__);
95 return FPGA_FAIL;
96 }
97
98 length = (*dataptr << 8) + *(dataptr+1);
99 dataptr += 2;
100 for (i = 0; i < length; i++)
101 buffer[i] = *dataptr++;
102 printf(" date = \"%s\"\n", buffer);
103
104 /* get time (identifier, length, string) */
105 if (*dataptr++ != 0x64) {
106 printf("%s: Time identifier not recognized in bitstream\n",
107 __func__);
108 return FPGA_FAIL;
109 }
110
111 length = (*dataptr << 8) + *(dataptr+1);
112 dataptr += 2;
113 for (i = 0; i < length; i++)
114 buffer[i] = *dataptr++;
115 printf(" time = \"%s\"\n", buffer);
116
117 /* get fpga data length (identifier, length) */
118 if (*dataptr++ != 0x65) {
119 printf("%s: Data length id not recognized in bitstream\n",
120 __func__);
121 return FPGA_FAIL;
122 }
123 swapsize = ((unsigned int) *dataptr << 24) +
124 ((unsigned int) *(dataptr + 1) << 16) +
125 ((unsigned int) *(dataptr + 2) << 8) +
126 ((unsigned int) *(dataptr + 3));
127 dataptr += 4;
128 printf(" bytes in bitstream = %d\n", swapsize);
129
Michal Simek78617b42013-05-01 19:02:02 +0200130 return fpga_load(devnum, dataptr, swapsize);
Michal Simekcd5a1cf2013-04-26 13:12:07 +0200131}
132
Michal Simek25e1e2e2014-03-13 12:49:21 +0100133int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
wdenk5d3207d2002-08-21 22:08:56 +0000134{
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200135 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000136 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
Michal Simek75fafac2014-03-13 13:07:57 +0100137 return FPGA_FAIL;
138 }
wdenk5d3207d2002-08-21 22:08:56 +0000139
Michal Simek75fafac2014-03-13 13:07:57 +0100140 return desc->operations->load(desc, buf, bsize);
wdenk5d3207d2002-08-21 22:08:56 +0000141}
142
Michal Simek25e1e2e2014-03-13 12:49:21 +0100143int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
wdenk5d3207d2002-08-21 22:08:56 +0000144{
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200145 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000146 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
Michal Simek75fafac2014-03-13 13:07:57 +0100147 return FPGA_FAIL;
148 }
wdenk5d3207d2002-08-21 22:08:56 +0000149
Michal Simek75fafac2014-03-13 13:07:57 +0100150 return desc->operations->dump(desc, buf, bsize);
wdenk5d3207d2002-08-21 22:08:56 +0000151}
152
Michal Simek25e1e2e2014-03-13 12:49:21 +0100153int xilinx_info(xilinx_desc *desc)
wdenk5d3207d2002-08-21 22:08:56 +0000154{
155 int ret_val = FPGA_FAIL;
156
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200157 if (xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000158 printf ("Family: \t");
159 switch (desc->family) {
Michal Simek5206cca2014-03-13 11:23:43 +0100160 case xilinx_spartan2:
wdenk5d3207d2002-08-21 22:08:56 +0000161 printf ("Spartan-II\n");
162 break;
Michal Simek2091a0c2014-03-13 11:28:42 +0100163 case xilinx_spartan3:
Wolfgang Denkc38e70c2005-09-25 16:44:21 +0200164 printf ("Spartan-III\n");
165 break;
Michal Simek90258882014-03-13 11:33:36 +0100166 case xilinx_virtex2:
wdenk5d3207d2002-08-21 22:08:56 +0000167 printf ("Virtex-II\n");
168 break;
Michal Simek15d654c2013-04-22 15:43:02 +0200169 case xilinx_zynq:
170 printf("Zynq PL\n");
171 break;
wdenk5d3207d2002-08-21 22:08:56 +0000172 /* Add new family types here */
173 default:
174 printf ("Unknown family type, %d\n", desc->family);
175 }
176
177 printf ("Interface type:\t");
178 switch (desc->iface) {
179 case slave_serial:
180 printf ("Slave Serial\n");
181 break;
182 case master_serial: /* Not used */
183 printf ("Master Serial\n");
184 break;
185 case slave_parallel:
186 printf ("Slave Parallel\n");
187 break;
188 case jtag_mode: /* Not used */
189 printf ("JTAG Mode\n");
190 break;
191 case slave_selectmap:
192 printf ("Slave SelectMap Mode\n");
193 break;
194 case master_selectmap:
195 printf ("Master SelectMap Mode\n");
196 break;
Michal Simek15d654c2013-04-22 15:43:02 +0200197 case devcfg:
198 printf("Device configuration interface (Zynq)\n");
199 break;
wdenk5d3207d2002-08-21 22:08:56 +0000200 /* Add new interface types here */
201 default:
202 printf ("Unsupported interface type, %d\n", desc->iface);
203 }
204
205 printf ("Device Size: \t%d bytes\n"
206 "Cookie: \t0x%x (%d)\n",
207 desc->size, desc->cookie, desc->cookie);
Michal Simek6ff890d2013-04-26 15:04:48 +0200208 if (desc->name)
209 printf("Device name: \t%s\n", desc->name);
wdenk5d3207d2002-08-21 22:08:56 +0000210
211 if (desc->iface_fns) {
212 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
Michal Simek75fafac2014-03-13 13:07:57 +0100213 desc->operations->info(desc);
wdenk5d3207d2002-08-21 22:08:56 +0000214 } else
215 printf ("No Device Function Table.\n");
216
217 ret_val = FPGA_SUCCESS;
218 } else {
219 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
220 }
221
222 return ret_val;
223}
224
wdenk5d3207d2002-08-21 22:08:56 +0000225/* ------------------------------------------------------------------------- */
226
Michal Simek25e1e2e2014-03-13 12:49:21 +0100227static int xilinx_validate(xilinx_desc *desc, char *fn)
wdenk5d3207d2002-08-21 22:08:56 +0000228{
York Sun4a598092013-04-01 11:29:11 -0700229 int ret_val = false;
wdenk5d3207d2002-08-21 22:08:56 +0000230
231 if (desc) {
232 if ((desc->family > min_xilinx_type) &&
233 (desc->family < max_xilinx_type)) {
234 if ((desc->iface > min_xilinx_iface_type) &&
235 (desc->iface < max_xilinx_iface_type)) {
236 if (desc->size) {
York Sun4a598092013-04-01 11:29:11 -0700237 ret_val = true;
wdenk5d3207d2002-08-21 22:08:56 +0000238 } else
239 printf ("%s: NULL part size\n", fn);
240 } else
241 printf ("%s: Invalid Interface type, %d\n",
242 fn, desc->iface);
243 } else
244 printf ("%s: Invalid family type, %d\n", fn, desc->family);
245 } else
246 printf ("%s: NULL descriptor!\n", fn);
247
248 return ret_val;
249}