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git01.mediatek.com / filogic / uboot / a7df05ca371f78303b17004484b699ff15115ef1 / . / arch / sandbox / dts / sandbox64.dts
blob: 3eb045708914ad5975080b24cbb82e76d612c0de [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Main sandbox64 devicetree
4 */
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]5/dts-v1/;
6
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]7#include <config.h>
8
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]9/ {
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +0100[diff] [blame]13 compatible = "sandbox";
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]14
15 aliases {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]16 i2c0 = &i2c_0;
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]17 pci0 = &pcic;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]18 rtc0 = &rtc_0;
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]19 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]20 spi0 = &spi;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]21 };
22
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]23 memory {
24 reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>;
25 };
26
Heinrich Schuchardtad935702020-03-14 12:13:39 +0100[diff] [blame]27 reserved-memory {
28 #address-cells = <2>;
29 #size-cells = <2>;
30 ranges;
31
32 reservation_test_size {
33 size = <0 0x4000>;
34 alignment = <0 0x2000>;
35 };
36
37 reservation_test@a000 {
38 reg = <0 0x00d0a000 0 0x2000>;
39 };
40
41 reservation_test@7000 {
42 reg = <0 0x00d07000 0 0x1000>;
43 };
44 };
45
46 /* ... */
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]47 cros_ec: cros-ec {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]48 reg = <0 0 0 0>;
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]49 u-boot,dm-pre-reloc;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]50 compatible = "google,cros-ec-sandbox";
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]51 };
52
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]53 ethrawbus {
54 compatible = "sandbox,eth-raw-bus";
55 skip-localhost = <1>;
56 };
57
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]58 eth@10002000 {
59 compatible = "sandbox,eth";
60 reg = <0x0 0x10002000 0x0 0x1000>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]61 };
62
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]63 i2c_0: i2c@0 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 reg = <0 0 0 0>;
67 compatible = "sandbox,i2c";
68 clock-frequency = <400000>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_i2c0>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]71 };
72
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]73 pcic: pci@0 {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]74 compatible = "sandbox,pci";
75 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]76 bus-range = <0x00 0xff>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]77 #address-cells = <3>;
78 #size-cells = <2>;
79 ranges = <0x02000000 0 0x10000000 0 0x10000000 0 0x2000
80 0x01000000 0 0x20000000 0 0x20000000 0 0x2000>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]81 };
82
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]83 spi: spi@0 {
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]84 u-boot,dm-pre-reloc;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]85 #address-cells = <1>;
86 #size-cells = <0>;
87 reg = <0 0 0 0>;
88 compatible = "sandbox,spi";
89 cs-gpios = <0>, <&gpio_a 0>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]90 };
91
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]92};
93
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]94#include "sandbox.dtsi"
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]95#include "cros-ec-keyboard.dtsi"
96#include "sandbox_pmic.dtsi"