Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 4a3ca485e8373e4a741826c3994ad8596a454570 / . / arch / sandbox / dts / sandbox64.dts
blob: 97e33f110eefdfa2deca80d8c4fcd6dce05b11a2 [file] [log] [blame]
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]1/dts-v1/;
2
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]3#include <config.h>
4
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]5/ {
6 #address-cells = <2>;
7 #size-cells = <2>;
8 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +0100[diff] [blame]9 compatible = "sandbox";
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]10
11 aliases {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]12 i2c0 = &i2c_0;
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame^]13 pci0 = &pcic;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]14 rtc0 = &rtc_0;
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]15 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]16 spi0 = &spi;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]17 };
18
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]19 memory {
20 reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>;
21 };
22
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]23 cros_ec: cros-ec {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]24 reg = <0 0 0 0>;
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]25 u-boot,dm-pre-reloc;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]26 compatible = "google,cros-ec-sandbox";
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]27 };
28
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]29 ethrawbus {
30 compatible = "sandbox,eth-raw-bus";
31 skip-localhost = <1>;
32 };
33
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]34 eth@10002000 {
35 compatible = "sandbox,eth";
36 reg = <0x0 0x10002000 0x0 0x1000>;
37 fake-host-hwaddr = [00 00 66 44 22 00];
38 };
39
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]40 i2c_0: i2c@0 {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 reg = <0 0 0 0>;
44 compatible = "sandbox,i2c";
45 clock-frequency = <400000>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_i2c0>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]48 };
49
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame^]50 pcic: pci@0 {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]51 compatible = "sandbox,pci";
52 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame^]53 bus-range = <0x00 0xff>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]54 #address-cells = <3>;
55 #size-cells = <2>;
56 ranges = <0x02000000 0 0x10000000 0 0x10000000 0 0x2000
57 0x01000000 0 0x20000000 0 0x20000000 0 0x2000>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]58 };
59
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]60 spi: spi@0 {
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]61 u-boot,dm-pre-reloc;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]62 #address-cells = <1>;
63 #size-cells = <0>;
64 reg = <0 0 0 0>;
65 compatible = "sandbox,spi";
66 cs-gpios = <0>, <&gpio_a 0>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]67 };
68
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]69};
70
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]71#include "sandbox.dtsi"
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]72#include "cros-ec-keyboard.dtsi"
73#include "sandbox_pmic.dtsi"