blob: fce3568eca149391b670c3ace3ca1a30cb922c15 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Dirk Behmea1aa39c2008-12-14 09:47:12 +01002/*
3 * (C) Copyright 2006-2008
4 * Texas Instruments, <www.ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
Dirk Behmea1aa39c2008-12-14 09:47:12 +01006 */
7
8#ifndef _MEM_H_
9#define _MEM_H_
10
11#define CS0 0x0
12#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
13
14#ifndef __ASSEMBLY__
Dirk Behmedc7af202009-08-08 09:30:21 +020015enum {
Dirk Behmea1aa39c2008-12-14 09:47:12 +010016 STACKED = 0,
17 IP_DDR = 1,
18 COMBO_DDR = 2,
19 IP_SDR = 3,
Dirk Behmedc7af202009-08-08 09:30:21 +020020};
Dirk Behmea1aa39c2008-12-14 09:47:12 +010021#endif /* __ASSEMBLY__ */
22
23#define EARLY_INIT 1
24
Tom Rini5b5e5762011-11-18 12:48:03 +000025/*
26 * For a full explanation of these registers and values please see
27 * the Technical Reference Manual (TRM) for any of the processors in
28 * this family.
29 */
30
Dirk Behmea1aa39c2008-12-14 09:47:12 +010031/* Slower full frequency range default timings for x32 operation*/
Nishanth Menon0d60d522009-11-07 10:40:47 -050032#define SDRC_SHARING 0x00000100
33#define SDRC_MR_0_SDR 0x00000031
Dirk Behmea1aa39c2008-12-14 09:47:12 +010034
Tom Rini0e860dd2011-11-18 12:48:04 +000035/*
36 * SDRC autorefresh control values. This register consists of autorefresh
37 * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
38 * counter is a result of ( tREFI / tCK ) - 50.
39 */
40#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
41#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
42#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
43#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
44
Dirk Behmea1aa39c2008-12-14 09:47:12 +010045#define DLL_OFFSET 0
46#define DLL_WRITEDDRCLKX2DIS 1
47#define DLL_ENADLL 1
48#define DLL_LOCKDLL 0
49#define DLL_DLLPHASE_72 0
50#define DLL_DLLPHASE_90 1
51
52/* rkw - need to find of 90/72 degree recommendation for speed like before */
53#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
54 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
55
Sanjeev Premi95655322011-10-27 16:15:19 +053056/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
57#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
58#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
59#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
60#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
61#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
62#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
63#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
64#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
65
Peter Baradaa7e15ff2012-02-07 11:02:40 +000066#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \
67 ACTIM_CTRLA_TRFC(trfc) | \
68 ACTIM_CTRLA_TRC(trc) | \
69 ACTIM_CTRLA_TRAS(tras) | \
70 ACTIM_CTRLA_TRP(trp) | \
71 ACTIM_CTRLA_TRCD(trcd) | \
72 ACTIM_CTRLA_TRRD(trrd) | \
73 ACTIM_CTRLA_TDPL(tdpl) | \
74 ACTIM_CTRLA_TDAL(tdal)
Sanjeev Premi95655322011-10-27 16:15:19 +053075
76/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
77#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
78#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
79#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
80#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
81
Peter Baradaa7e15ff2012-02-07 11:02:40 +000082#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
83 ACTIM_CTRLB_TWTR(twtr) | \
84 ACTIM_CTRLB_TCKE(tcke) | \
85 ACTIM_CTRLB_TXP(txp) | \
86 ACTIM_CTRLB_TXSR(txsr)
Sanjeev Premi95655322011-10-27 16:15:19 +053087
Tom Rini5b5e5762011-11-18 12:48:03 +000088/*
89 * Values used in the MCFG register. Only values we use today
90 * are defined and the rest can be found in the TRM. Unless otherwise
91 * noted all fields are one bit.
92 */
93#define V_MCFG_RAMTYPE_DDR (0x1)
94#define V_MCFG_DEEPPD_EN (0x1 << 3)
95#define V_MCFG_B32NOT16_32 (0x1 << 4)
Peter Baradaa7e15ff2012-02-07 11:02:40 +000096#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
97#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */
Tom Rini5b5e5762011-11-18 12:48:03 +000098#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
Peter Baradaa7e15ff2012-02-07 11:02:40 +000099#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */
100#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10)
101#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */
Tom Rini5b5e5762011-11-18 12:48:03 +0000102
103/* Macro to construct MCFG */
Peter Baradaa7e15ff2012-02-07 11:02:40 +0000104#define MCFG(ramsize, raswidth) \
105 V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \
106 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \
107 V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \
108 V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
Tom Rini5b5e5762011-11-18 12:48:03 +0000109
Andreas Müller785f1f02012-01-04 15:26:25 +0000110/* Hynix part of Overo (165MHz optimized) 6.06ns */
111#define HYNIX_TDAL_165 6
112#define HYNIX_TDPL_165 3
113#define HYNIX_TRRD_165 2
114#define HYNIX_TRCD_165 3
115#define HYNIX_TRP_165 3
116#define HYNIX_TRAS_165 7
117#define HYNIX_TRC_165 10
118#define HYNIX_TRFC_165 21
119#define HYNIX_V_ACTIMA_165 \
120 ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
121 HYNIX_TRAS_165, HYNIX_TRP_165, \
122 HYNIX_TRCD_165, HYNIX_TRRD_165, \
123 HYNIX_TDPL_165, HYNIX_TDAL_165)
124
125#define HYNIX_TWTR_165 1
126#define HYNIX_TCKE_165 1
127#define HYNIX_TXP_165 2
128#define HYNIX_XSR_165 24
129#define HYNIX_V_ACTIMB_165 \
130 ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
131 HYNIX_TXP_165, HYNIX_XSR_165)
132
Peter Baradaa7e15ff2012-02-07 11:02:40 +0000133#define HYNIX_RASWIDTH_165 13
Andreas Müller785f1f02012-01-04 15:26:25 +0000134#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
135
Tom Rini988a2352011-11-18 12:48:09 +0000136/* Hynix part of AM/DM37xEVM (200MHz optimized) */
137#define HYNIX_TDAL_200 6
138#define HYNIX_TDPL_200 3
139#define HYNIX_TRRD_200 2
140#define HYNIX_TRCD_200 4
141#define HYNIX_TRP_200 3
142#define HYNIX_TRAS_200 8
143#define HYNIX_TRC_200 11
144#define HYNIX_TRFC_200 18
145#define HYNIX_V_ACTIMA_200 \
146 ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
147 HYNIX_TRAS_200, HYNIX_TRP_200, \
148 HYNIX_TRCD_200, HYNIX_TRRD_200, \
149 HYNIX_TDPL_200, HYNIX_TDAL_200)
150
151#define HYNIX_TWTR_200 2
152#define HYNIX_TCKE_200 1
153#define HYNIX_TXP_200 1
154#define HYNIX_XSR_200 28
155#define HYNIX_V_ACTIMB_200 \
156 ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
157 HYNIX_TXP_200, HYNIX_XSR_200)
158
Peter Baradaa7e15ff2012-02-07 11:02:40 +0000159#define HYNIX_RASWIDTH_200 14
Tom Rini988a2352011-11-18 12:48:09 +0000160#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
161
Sanjeev Premid4f9ae82011-10-27 16:53:14 +0530162/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
163#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
164 /* 15/6 + 18/6 = 5.5 -> 6 */
165#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
166#define INFINEON_TRRD_165 2 /* 12/6 = 2 */
167#define INFINEON_TRCD_165 3 /* 18/6 = 3 */
168#define INFINEON_TRP_165 3 /* 18/6 = 3 */
169#define INFINEON_TRAS_165 7 /* 42/6 = 7 */
170#define INFINEON_TRC_165 10 /* 60/6 = 10 */
171#define INFINEON_TRFC_165 12 /* 72/6 = 12 */
Sanjeev Premi95655322011-10-27 16:15:19 +0530172
173#define INFINEON_V_ACTIMA_165 \
174 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
175 INFINEON_TRAS_165, INFINEON_TRP_165, \
176 INFINEON_TRCD_165, INFINEON_TRRD_165, \
177 INFINEON_TDPL_165, INFINEON_TDAL_165)
Nishanth Menon076501b2009-11-07 10:51:24 -0500178
179#define INFINEON_TWTR_165 1
180#define INFINEON_TCKE_165 2
181#define INFINEON_TXP_165 2
Sanjeev Premid4f9ae82011-10-27 16:53:14 +0530182#define INFINEON_XSR_165 20 /* 120/6 = 20 */
Sanjeev Premi95655322011-10-27 16:15:19 +0530183
184#define INFINEON_V_ACTIMB_165 \
185 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
186 INFINEON_TXP_165, INFINEON_XSR_165)
Nishanth Menon076501b2009-11-07 10:51:24 -0500187
Sanjeev Premid4f9ae82011-10-27 16:53:14 +0530188/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
189#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
190 /* 15/6 + 18/6 = 5.5 -> 6 */
191#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
192#define MICRON_TRRD_165 2 /* 12/6 = 2 */
193#define MICRON_TRCD_165 3 /* 18/6 = 3 */
194#define MICRON_TRP_165 3 /* 18/6 = 3 */
195#define MICRON_TRAS_165 7 /* 42/6 = 7 */
196#define MICRON_TRC_165 10 /* 60/6 = 10 */
197#define MICRON_TRFC_165 21 /* 125/6 = 21 */
Sanjeev Premi95655322011-10-27 16:15:19 +0530198
199#define MICRON_V_ACTIMA_165 \
200 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
201 MICRON_TRAS_165, MICRON_TRP_165, \
202 MICRON_TRCD_165, MICRON_TRRD_165, \
203 MICRON_TDPL_165, MICRON_TDAL_165)
Nishanth Menon076501b2009-11-07 10:51:24 -0500204
205#define MICRON_TWTR_165 1
206#define MICRON_TCKE_165 1
Sanjeev Premid4f9ae82011-10-27 16:53:14 +0530207#define MICRON_XSR_165 23 /* 138/6 = 23 */
208#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
Sanjeev Premi95655322011-10-27 16:15:19 +0530209
210#define MICRON_V_ACTIMB_165 \
211 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
212 MICRON_TXP_165, MICRON_XSR_165)
Nishanth Menon076501b2009-11-07 10:51:24 -0500213
Peter Baradaa7e15ff2012-02-07 11:02:40 +0000214#define MICRON_RASWIDTH_165 13
Tom Rini3cc8b552011-11-18 12:48:05 +0000215#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
Simon Schwarzee50ca92011-09-14 15:15:37 -0400216
Tom Rini3cc8b552011-11-18 12:48:05 +0000217#define MICRON_BL_165 0x2
218#define MICRON_SIL_165 0x0
219#define MICRON_CASL_165 0x3
220#define MICRON_WBST_165 0x0
221#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
222 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
223 (MICRON_BL_165))
Simon Schwarzee50ca92011-09-14 15:15:37 -0400224
Tom Rini06c32fb2011-11-18 12:48:08 +0000225/* Micron part (200MHz optimized) 5 ns */
226#define MICRON_TDAL_200 6
227#define MICRON_TDPL_200 3
228#define MICRON_TRRD_200 2
229#define MICRON_TRCD_200 3
230#define MICRON_TRP_200 3
231#define MICRON_TRAS_200 8
232#define MICRON_TRC_200 11
233#define MICRON_TRFC_200 15
234#define MICRON_V_ACTIMA_200 \
235 ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
236 MICRON_TRAS_200, MICRON_TRP_200, \
237 MICRON_TRCD_200, MICRON_TRRD_200, \
238 MICRON_TDPL_200, MICRON_TDAL_200)
239
240#define MICRON_TWTR_200 2
241#define MICRON_TCKE_200 4
242#define MICRON_TXP_200 2
243#define MICRON_XSR_200 23
244#define MICRON_V_ACTIMB_200 \
245 ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
246 MICRON_TXP_200, MICRON_XSR_200)
247
Peter Baradaa7e15ff2012-02-07 11:02:40 +0000248#define MICRON_RASWIDTH_200 14
Tom Rini06c32fb2011-11-18 12:48:08 +0000249#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
250
Albert ARIBAUD \(3ADEV\)60467102015-01-16 09:09:49 +0100251/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
252#define SAMSUNG_TDAL_165 5
253#define SAMSUNG_TDPL_165 2
254#define SAMSUNG_TRRD_165 2
255#define SAMSUNG_TRCD_165 3
256#define SAMSUNG_TRP_165 3
257#define SAMSUNG_TRAS_165 7
258#define SAMSUNG_TRC_165 10
259#define SAMSUNG_TRFC_165 12
260
261#define SAMSUNG_V_ACTIMA_165 \
262 ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
263 SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
264 SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
265 SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
266
267#define SAMSUNG_TWTR_165 1
268#define SAMSUNG_TCKE_165 2
269#define SAMSUNG_XSR_165 20
270#define SAMSUNG_TXP_165 5
271
272#define SAMSUNG_V_ACTIMB_165 \
273 ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
274 SAMSUNG_TXP_165, SAMSUNG_XSR_165)
275
276#define SAMSUNG_RASWIDTH_165 14
277#define SAMSUNG_V_MCFG_165(size) \
278 V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
279 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
280 V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
281
282/* TODO: find which register these were taken from */
283
284#define SAMSUNG_BL_165 0x2
285#define SAMSUNG_SIL_165 0x0
286#define SAMSUNG_CASL_165 0x3
287#define SAMSUNG_WBST_165 0x0
288#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
289 (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
290 (SAMSUNG_BL_165))
291
292#define SAMSUNG_SHARING 0x00003700
293
Sanjeev Premid4f9ae82011-10-27 16:53:14 +0530294/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
295#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
296 /* 15/6 + 18/6 = 5.5 -> 6 */
297#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
298#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
299#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
300#define NUMONYX_TRP_165 3 /* 18/6 = 3 */
301#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
302#define NUMONYX_TRC_165 10 /* 60/6 = 10 */
303#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
Sanjeev Premi95655322011-10-27 16:15:19 +0530304
305#define NUMONYX_V_ACTIMA_165 \
306 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
307 NUMONYX_TRAS_165, NUMONYX_TRP_165, \
308 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
309 NUMONYX_TDPL_165, NUMONYX_TDAL_165)
Enric Balletbo i Serrae7f3e722010-10-14 16:53:27 -0400310
Sanjeev Premi26225e42011-10-27 16:21:57 +0530311#define NUMONYX_TWTR_165 2
312#define NUMONYX_TCKE_165 2
Sanjeev Premid4f9ae82011-10-27 16:53:14 +0530313#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
314#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
Sanjeev Premi95655322011-10-27 16:15:19 +0530315
316#define NUMONYX_V_ACTIMB_165 \
317 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
318 NUMONYX_TXP_165, NUMONYX_XSR_165)
Enric Balletbo i Serrae7f3e722010-10-14 16:53:27 -0400319
Peter Baradaa7e15ff2012-02-07 11:02:40 +0000320#define NUMONYX_RASWIDTH_165 15
Tom Rini06c32fb2011-11-18 12:48:08 +0000321#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
322
Javier Martinez Canillas94458fc2012-07-28 01:19:33 +0000323/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
324#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
325 /* 15/5 + 15/5 = 3 + 3 -> 6 */
326#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
327#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
328#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
329#define NUMONYX_TRP_200 3 /* 15/5 = 3 */
330#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
331#define NUMONYX_TRC_200 11 /* 55/5 = 11 */
332#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */
333
334#define NUMONYX_V_ACTIMA_200 \
335 ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
336 NUMONYX_TRAS_200, NUMONYX_TRP_200, \
337 NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
338 NUMONYX_TDPL_200, NUMONYX_TDAL_200)
339
340#define NUMONYX_TWTR_200 2
341#define NUMONYX_TCKE_200 2
342#define NUMONYX_TXP_200 3
343#define NUMONYX_XSR_200 40
344
345#define NUMONYX_V_ACTIMB_200 \
346 ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
347 NUMONYX_TXP_200, NUMONYX_XSR_200)
348
349#define NUMONYX_RASWIDTH_200 15
350#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
351
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100352/*
353 * GPMC settings -
354 * Definitions is as per the following format
355 * #define <PART>_GPMC_CONFIG<x> <value>
356 * Where:
357 * PART is the part name e.g. STNOR - Intel Strata Flash
358 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
359 * Value is corresponding value
360 *
361 * For every valid PRCM configuration there should be only one definition of
362 * the same. if values are independent of the board, this definition will be
363 * present in this file if values are dependent on the board, then this should
364 * go into corresponding mem-boardName.h file
365 *
366 * Currently valid part Names are (PART):
367 * STNOR - Intel Strata Flash
368 * SMNAND - Samsung NAND
369 * MPDB - H4 MPDB board
370 * SBNOR - Sibley NOR
371 * MNAND - Micron Large page x16 NAND
372 * ONNAND - Samsung One NAND
373 *
374 * include/configs/file.h contains the defn - for all CS we are interested
375 * #define OMAP34XX_GPMC_CSx PART
376 * #define OMAP34XX_GPMC_CSx_SIZE Size
377 * #define OMAP34XX_GPMC_CSx_MAP Map
378 * Where:
379 * x - CS number
380 * PART - Part Name as defined above
381 * SIZE - how big is the mapping to be
382 * GPMC_SIZE_128M - 0x8
383 * GPMC_SIZE_64M - 0xC
384 * GPMC_SIZE_32M - 0xE
385 * GPMC_SIZE_16M - 0xF
386 * MAP - Map this CS to which address(GPMC address space)- Absolute address
387 * >>24 before being used.
388 */
pekon gupta48e1e152014-05-08 21:43:47 +0530389#define GPMC_SIZE_256M 0x0
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100390#define GPMC_SIZE_128M 0x8
391#define GPMC_SIZE_64M 0xC
392#define GPMC_SIZE_32M 0xE
393#define GPMC_SIZE_16M 0xF
394
Tom Rini51b2be52011-11-18 12:47:58 +0000395#define GPMC_BASEADDR_MASK 0x3F
396
397#define GPMC_CS_ENABLE 0x1
398
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100399#define M_NAND_GPMC_CONFIG1 0x00001800
400#define M_NAND_GPMC_CONFIG2 0x00141400
401#define M_NAND_GPMC_CONFIG3 0x00141400
402#define M_NAND_GPMC_CONFIG4 0x0F010F01
403#define M_NAND_GPMC_CONFIG5 0x010C1414
404#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
405#define M_NAND_GPMC_CONFIG7 0x00000C44
406
407#define STNOR_GPMC_CONFIG1 0x3
408#define STNOR_GPMC_CONFIG2 0x00151501
409#define STNOR_GPMC_CONFIG3 0x00060602
410#define STNOR_GPMC_CONFIG4 0x11091109
411#define STNOR_GPMC_CONFIG5 0x01141F1F
412#define STNOR_GPMC_CONFIG6 0x000004c4
413
414#define SIBNOR_GPMC_CONFIG1 0x1200
415#define SIBNOR_GPMC_CONFIG2 0x001f1f00
416#define SIBNOR_GPMC_CONFIG3 0x00080802
417#define SIBNOR_GPMC_CONFIG4 0x1C091C09
418#define SIBNOR_GPMC_CONFIG5 0x01131F1F
419#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
420
421#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
422#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
423#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
424#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
425#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
426#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
427
428#define MPDB_GPMC_CONFIG1 0x00011000
429#define MPDB_GPMC_CONFIG2 0x001f1f01
430#define MPDB_GPMC_CONFIG3 0x00080803
431#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
432#define MPDB_GPMC_CONFIG5 0x041f1F1F
433#define MPDB_GPMC_CONFIG6 0x1F0F04C4
434
435#define P2_GPMC_CONFIG1 0x0
436#define P2_GPMC_CONFIG2 0x0
437#define P2_GPMC_CONFIG3 0x0
438#define P2_GPMC_CONFIG4 0x0
439#define P2_GPMC_CONFIG5 0x0
440#define P2_GPMC_CONFIG6 0x0
441
442#define ONENAND_GPMC_CONFIG1 0x00001200
443#define ONENAND_GPMC_CONFIG2 0x000F0F01
444#define ONENAND_GPMC_CONFIG3 0x00030301
445#define ONENAND_GPMC_CONFIG4 0x0F040F04
446#define ONENAND_GPMC_CONFIG5 0x010F1010
447#define ONENAND_GPMC_CONFIG6 0x1F060000
448
449#define NET_GPMC_CONFIG1 0x00001000
450#define NET_GPMC_CONFIG2 0x001e1e01
451#define NET_GPMC_CONFIG3 0x00080300
452#define NET_GPMC_CONFIG4 0x1c091c09
453#define NET_GPMC_CONFIG5 0x04181f1f
454#define NET_GPMC_CONFIG6 0x00000FCF
455#define NET_GPMC_CONFIG7 0x00000f6c
456
pekon gupta930eb902013-11-22 16:53:26 +0530457/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
458#define NET_LAN9221_GPMC_CONFIG1 0x00001000
459#define NET_LAN9221_GPMC_CONFIG2 0x00060700
460#define NET_LAN9221_GPMC_CONFIG3 0x00020201
461#define NET_LAN9221_GPMC_CONFIG4 0x06000700
462#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
463#define NET_LAN9221_GPMC_CONFIG6 0x87030000
464#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
465
466
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100467/* max number of GPMC Chip Selects */
468#define GPMC_MAX_CS 8
469/* max number of GPMC regs */
470#define GPMC_MAX_REG 7
471
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100472#define DBG_MPDB 6
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100473#define DBG_MPDB_BASE DEBUG_BASE
474
Vaibhav Hiremath558d23d2010-06-07 15:20:34 -0400475#ifndef __ASSEMBLY__
476
477/* Function prototypes */
Maxim Uvarov74dde142023-12-26 21:46:18 +0600478void omap3_mem_init(void);
Vaibhav Hiremath558d23d2010-06-07 15:20:34 -0400479
480u32 is_mem_sdr(void);
481u32 mem_ok(u32 cs);
482
Vaibhav Hiremath558d23d2010-06-07 15:20:34 -0400483u32 get_sdr_cs_offset(u32);
484
485#endif /* __ASSEMBLY__ */
486
Dirk Behmea1aa39c2008-12-14 09:47:12 +0100487#endif /* endif _MEM_H_ */