Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 SAMSUNG Electronics |
| 3 | * Minkyu Kang <mk7.kang@samsung.com> |
| 4 | * Heungjun Kim <riverful.kim@samsung.com> |
| 5 | * |
| 6 | * based on drivers/serial/s3c64xx.c |
| 7 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 12 | #include <dm.h> |
| 13 | #include <errno.h> |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 14 | #include <fdtdec.h> |
Mike Frysinger | f96c042 | 2011-04-29 18:03:29 +0000 | [diff] [blame] | 15 | #include <linux/compiler.h> |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 16 | #include <asm/io.h> |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 17 | #include <asm/arch/clk.h> |
Simon Glass | 405fd14 | 2015-07-02 18:15:53 -0600 | [diff] [blame] | 18 | #include <asm/arch/uart.h> |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 19 | #include <serial.h> |
Thomas Abraham | c81fdbe | 2016-04-23 22:18:11 +0530 | [diff] [blame] | 20 | #include <clk.h> |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 21 | |
John Rigby | 0d21ed0 | 2010-12-20 18:27:51 -0700 | [diff] [blame] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 24 | #define RX_FIFO_COUNT_SHIFT 0 |
| 25 | #define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT) |
| 26 | #define RX_FIFO_FULL (1 << 8) |
| 27 | #define TX_FIFO_COUNT_SHIFT 16 |
| 28 | #define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT) |
| 29 | #define TX_FIFO_FULL (1 << 24) |
Akshay Saraswat | 63f1090 | 2013-03-21 20:33:04 +0000 | [diff] [blame] | 30 | |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 31 | /* Information about a serial port */ |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 32 | struct s5p_serial_platdata { |
| 33 | struct s5p_uart *reg; /* address of registers in physical memory */ |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 34 | u8 port_id; /* uart port number */ |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 35 | }; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 36 | |
| 37 | /* |
Minkyu Kang | baa3688 | 2010-03-24 16:59:30 +0900 | [diff] [blame] | 38 | * The coefficient, used to calculate the baudrate on S5P UARTs is |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 39 | * calculated as |
| 40 | * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT |
| 41 | * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, |
| 42 | * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: |
| 43 | */ |
| 44 | static const int udivslot[] = { |
| 45 | 0, |
| 46 | 0x0080, |
| 47 | 0x0808, |
| 48 | 0x0888, |
| 49 | 0x2222, |
| 50 | 0x4924, |
| 51 | 0x4a52, |
| 52 | 0x54aa, |
| 53 | 0x5555, |
| 54 | 0xd555, |
| 55 | 0xd5d5, |
| 56 | 0xddd5, |
| 57 | 0xdddd, |
| 58 | 0xdfdd, |
| 59 | 0xdfdf, |
| 60 | 0xffdf, |
| 61 | }; |
| 62 | |
Simon Glass | 405fd14 | 2015-07-02 18:15:53 -0600 | [diff] [blame] | 63 | static void __maybe_unused s5p_serial_init(struct s5p_uart *uart) |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 64 | { |
Simon Glass | 405fd14 | 2015-07-02 18:15:53 -0600 | [diff] [blame] | 65 | /* enable FIFOs, auto clear Rx FIFO */ |
| 66 | writel(0x3, &uart->ufcon); |
| 67 | writel(0, &uart->umcon); |
| 68 | /* 8N1 */ |
| 69 | writel(0x3, &uart->ulcon); |
| 70 | /* No interrupts, no DMA, pure polling */ |
| 71 | writel(0x245, &uart->ucon); |
| 72 | } |
| 73 | |
| 74 | static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk, |
| 75 | int baudrate) |
| 76 | { |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 77 | u32 val; |
| 78 | |
Minkyu Kang | 36f25cf | 2010-08-24 15:51:55 +0900 | [diff] [blame] | 79 | val = uclk / baudrate; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 80 | |
| 81 | writel(val / 16 - 1, &uart->ubrdiv); |
Minkyu Kang | bfa1424 | 2010-09-28 14:35:02 +0900 | [diff] [blame] | 82 | |
Minkyu Kang | afae8aa | 2011-01-24 14:43:25 +0900 | [diff] [blame] | 83 | if (s5p_uart_divslot()) |
Minkyu Kang | bfa1424 | 2010-09-28 14:35:02 +0900 | [diff] [blame] | 84 | writew(udivslot[val % 16], &uart->rest.slot); |
| 85 | else |
| 86 | writeb(val % 16, &uart->rest.value); |
Simon Glass | 405fd14 | 2015-07-02 18:15:53 -0600 | [diff] [blame] | 87 | } |
| 88 | |
Simon Glass | 8ed4bc1 | 2015-07-02 18:15:55 -0600 | [diff] [blame] | 89 | #ifndef CONFIG_SPL_BUILD |
Simon Glass | 405fd14 | 2015-07-02 18:15:53 -0600 | [diff] [blame] | 90 | int s5p_serial_setbrg(struct udevice *dev, int baudrate) |
| 91 | { |
| 92 | struct s5p_serial_platdata *plat = dev->platdata; |
| 93 | struct s5p_uart *const uart = plat->reg; |
Thomas Abraham | c81fdbe | 2016-04-23 22:18:11 +0530 | [diff] [blame] | 94 | u32 uclk; |
| 95 | |
| 96 | #ifdef CONFIG_CLK_EXYNOS |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 97 | struct clk clk; |
Thomas Abraham | c81fdbe | 2016-04-23 22:18:11 +0530 | [diff] [blame] | 98 | u32 ret; |
| 99 | |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 100 | ret = clk_get_by_index(dev, 1, &clk); |
Thomas Abraham | c81fdbe | 2016-04-23 22:18:11 +0530 | [diff] [blame] | 101 | if (ret < 0) |
| 102 | return ret; |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 103 | uclk = clk_get_rate(&clk); |
Thomas Abraham | c81fdbe | 2016-04-23 22:18:11 +0530 | [diff] [blame] | 104 | #else |
| 105 | uclk = get_uart_clk(plat->port_id); |
| 106 | #endif |
Simon Glass | 405fd14 | 2015-07-02 18:15:53 -0600 | [diff] [blame] | 107 | |
| 108 | s5p_serial_baud(uart, uclk, baudrate); |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 109 | |
| 110 | return 0; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 111 | } |
| 112 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 113 | static int s5p_serial_probe(struct udevice *dev) |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 114 | { |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 115 | struct s5p_serial_platdata *plat = dev->platdata; |
| 116 | struct s5p_uart *const uart = plat->reg; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 117 | |
Simon Glass | 405fd14 | 2015-07-02 18:15:53 -0600 | [diff] [blame] | 118 | s5p_serial_init(uart); |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 119 | |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 120 | return 0; |
| 121 | } |
| 122 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 123 | static int serial_err_check(const struct s5p_uart *const uart, int op) |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 124 | { |
Minkyu Kang | 9455aab | 2009-11-10 20:23:50 +0900 | [diff] [blame] | 125 | unsigned int mask; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 126 | |
Minkyu Kang | 9455aab | 2009-11-10 20:23:50 +0900 | [diff] [blame] | 127 | /* |
| 128 | * UERSTAT |
| 129 | * Break Detect [3] |
| 130 | * Frame Err [2] : receive operation |
| 131 | * Parity Err [1] : receive operation |
| 132 | * Overrun Err [0] : receive operation |
| 133 | */ |
| 134 | if (op) |
| 135 | mask = 0x8; |
| 136 | else |
| 137 | mask = 0xf; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 138 | |
Minkyu Kang | 9455aab | 2009-11-10 20:23:50 +0900 | [diff] [blame] | 139 | return readl(&uart->uerstat) & mask; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 140 | } |
| 141 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 142 | static int s5p_serial_getc(struct udevice *dev) |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 143 | { |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 144 | struct s5p_serial_platdata *plat = dev->platdata; |
| 145 | struct s5p_uart *const uart = plat->reg; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 146 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 147 | if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK)) |
| 148 | return -EAGAIN; |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 149 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 150 | serial_err_check(uart, 0); |
Minkyu Kang | 7622981 | 2010-07-06 20:08:29 +0900 | [diff] [blame] | 151 | return (int)(readb(&uart->urxh) & 0xff); |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 152 | } |
| 153 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 154 | static int s5p_serial_putc(struct udevice *dev, const char ch) |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 155 | { |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 156 | struct s5p_serial_platdata *plat = dev->platdata; |
| 157 | struct s5p_uart *const uart = plat->reg; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 158 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 159 | if (readl(&uart->ufstat) & TX_FIFO_FULL) |
| 160 | return -EAGAIN; |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 161 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 162 | writeb(ch, &uart->utxh); |
| 163 | serial_err_check(uart, 1); |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 164 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 165 | return 0; |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 166 | } |
| 167 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 168 | static int s5p_serial_pending(struct udevice *dev, bool input) |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 169 | { |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 170 | struct s5p_serial_platdata *plat = dev->platdata; |
| 171 | struct s5p_uart *const uart = plat->reg; |
| 172 | uint32_t ufstat = readl(&uart->ufstat); |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 173 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 174 | if (input) |
| 175 | return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT; |
| 176 | else |
| 177 | return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT; |
Marek Vasut | 5bcdf24 | 2012-09-09 18:48:28 +0200 | [diff] [blame] | 178 | } |
Minkyu Kang | fca3084 | 2009-10-01 17:20:28 +0900 | [diff] [blame] | 179 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 180 | static int s5p_serial_ofdata_to_platdata(struct udevice *dev) |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 181 | { |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 182 | struct s5p_serial_platdata *plat = dev->platdata; |
| 183 | fdt_addr_t addr; |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 184 | |
Simon Glass | ba1dea4 | 2017-05-17 17:18:05 -0600 | [diff] [blame] | 185 | addr = devfdt_get_addr(dev); |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 186 | if (addr == FDT_ADDR_T_NONE) |
| 187 | return -EINVAL; |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 188 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 189 | plat->reg = (struct s5p_uart *)addr; |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 190 | plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
Thomas Abraham | 214a395 | 2016-04-23 22:18:10 +0530 | [diff] [blame] | 191 | "id", dev->seq); |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 192 | return 0; |
| 193 | } |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 194 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 195 | static const struct dm_serial_ops s5p_serial_ops = { |
| 196 | .putc = s5p_serial_putc, |
| 197 | .pending = s5p_serial_pending, |
| 198 | .getc = s5p_serial_getc, |
| 199 | .setbrg = s5p_serial_setbrg, |
| 200 | }; |
Rajeshwari Shinde | bd19fa9 | 2013-06-24 16:47:22 +0530 | [diff] [blame] | 201 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 202 | static const struct udevice_id s5p_serial_ids[] = { |
| 203 | { .compatible = "samsung,exynos4210-uart" }, |
| 204 | { } |
| 205 | }; |
Marek Vasut | 533e31e | 2012-09-12 19:39:57 +0200 | [diff] [blame] | 206 | |
Simon Glass | 767e737 | 2014-09-14 16:36:17 -0600 | [diff] [blame] | 207 | U_BOOT_DRIVER(serial_s5p) = { |
| 208 | .name = "serial_s5p", |
| 209 | .id = UCLASS_SERIAL, |
| 210 | .of_match = s5p_serial_ids, |
| 211 | .ofdata_to_platdata = s5p_serial_ofdata_to_platdata, |
| 212 | .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata), |
| 213 | .probe = s5p_serial_probe, |
| 214 | .ops = &s5p_serial_ops, |
| 215 | .flags = DM_FLAG_PRE_RELOC, |
| 216 | }; |
Simon Glass | 8ed4bc1 | 2015-07-02 18:15:55 -0600 | [diff] [blame] | 217 | #endif |
Simon Glass | 74afb29 | 2015-07-02 18:15:54 -0600 | [diff] [blame] | 218 | |
| 219 | #ifdef CONFIG_DEBUG_UART_S5P |
| 220 | |
| 221 | #include <debug_uart.h> |
| 222 | |
Simon Glass | 60517d7 | 2015-10-18 19:51:23 -0600 | [diff] [blame] | 223 | static inline void _debug_uart_init(void) |
Simon Glass | 74afb29 | 2015-07-02 18:15:54 -0600 | [diff] [blame] | 224 | { |
| 225 | struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; |
| 226 | |
| 227 | s5p_serial_init(uart); |
| 228 | s5p_serial_baud(uart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); |
| 229 | } |
| 230 | |
| 231 | static inline void _debug_uart_putc(int ch) |
| 232 | { |
| 233 | struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; |
| 234 | |
| 235 | while (readl(&uart->ufstat) & TX_FIFO_FULL); |
| 236 | |
| 237 | writeb(ch, &uart->utxh); |
| 238 | } |
| 239 | |
| 240 | DEBUG_UART_FUNCS |
| 241 | |
| 242 | #endif |