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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jaehoon Chung7aff9672012-10-15 19:10:31 +00002/*
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung7aff9672012-10-15 19:10:31 +00005 */
6
Sam Protsenko8d49cfb2024-08-07 22:14:22 -05007#ifndef __ASM_ARM_ARCH_DWMMC_H
8#define __ASM_ARM_ARCH_DWMMC_H
9
Sam Protsenkocda02f12024-08-07 22:14:41 -050010#include <linux/bitops.h>
Jaehoon Chung7aff9672012-10-15 19:10:31 +000011
Sam Protsenkocda02f12024-08-07 22:14:41 -050012#define DWMCI_CLKSEL 0x09c
13#define DWMCI_CLKSEL64 0x0a8
14#define DWMCI_SET_SAMPLE_CLK(x) (x)
15#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
16#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
17
18/* Protector Register */
19#define DWMCI_EMMCP_BASE 0x1000
20#define EMMCP_MPSBEGIN0 (DWMCI_EMMCP_BASE + 0x0200)
21#define EMMCP_SEND0 (DWMCI_EMMCP_BASE + 0x0204)
22#define EMMCP_CTRL0 (DWMCI_EMMCP_BASE + 0x020c)
Rajeshwari Shinde70163092013-10-29 12:53:13 +053023
Sam Protsenkocda02f12024-08-07 22:14:41 -050024#define MPSCTRL_SECURE_READ_BIT BIT(7)
25#define MPSCTRL_SECURE_WRITE_BIT BIT(6)
26#define MPSCTRL_NON_SECURE_READ_BIT BIT(5)
27#define MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
28#define MPSCTRL_USE_FUSE_KEY BIT(3)
29#define MPSCTRL_ECB_MODE BIT(2)
30#define MPSCTRL_ENCRYPTION BIT(1)
31#define MPSCTRL_VALID BIT(0)
Rajeshwari Shinde70163092013-10-29 12:53:13 +053032
Rajeshwari S Shindeccfa20b2014-02-05 10:48:15 +053033/* CLKSEL Register */
34#define DWMCI_DIVRATIO_BIT 24
35#define DWMCI_DIVRATIO_MASK 0x7
Sam Protsenko8d49cfb2024-08-07 22:14:22 -050036
37#endif /* __ASM_ARM_ARCH_DWMMC_H */