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git01.mediatek.com / filogic / uboot / a6c719fb7582c0b16495dc80df7da4a87e3772cc / . / arch / arm / dts / armada-38x-controlcenterdc.dts
blob: 5063a798df76b39bedbad380915befcbe254690c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]2/*
3 * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
4 *
5 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
6 *
7 * based on the Device Tree file for Marvell Armada 388 evaluation board
8 * (DB-88F6820), which is
9 *
10 * Copyright (C) 2014 Marvell
11 *
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]13 */
14
15/dts-v1/;
16
17#include "armada-388.dtsi"
18
19&gpio0 {
20 u-boot,dm-pre-reloc;
21};
22
23&gpio1 {
24 u-boot,dm-pre-reloc;
25};
26
27&uart0 {
28 u-boot,dm-pre-reloc;
29};
30
31&uart1 {
32 u-boot,dm-pre-reloc;
33};
34
35/ {
36 model = "Controlcenter Digital Compact";
37 compatible = "marvell,a385-db", "marvell,armada388",
38 "marvell,armada385", "marvell,armada380";
39
40 chosen {
41 bootargs = "console=ttyS1,115200 earlyprintk";
42 stdout-path = "/soc/internal-regs/serial@12100";
43 };
44
45 aliases {
46 ethernet0 = &eth0;
47 ethernet2 = &eth2;
48 mdio-gpio0 = &MDIO0;
49 mdio-gpio1 = &MDIO1;
50 mdio-gpio2 = &MDIO2;
51 spi0 = &spi0;
52 spi1 = &spi1;
53 i2c0 = &I2C0;
54 i2c1 = &I2C1;
55 };
56
57 memory {
58 device_type = "memory";
59 reg = <0x00000000 0x10000000>; /* 256 MB */
60 };
61
62 clocks {
63 sc16isclk: sc16isclk {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <11059200>;
67 };
68 };
69
70 soc {
71 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
72 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
73
74 internal-regs {
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]75 I2C0: i2c@11000 {
76 status = "okay";
77 clock-frequency = <1000000>;
78 u-boot,dm-pre-reloc;
79 PCA21: pca9698@21 {
80 compatible = "nxp,pca9698";
81 reg = <0x21>;
82 #gpio-cells = <2>;
83 gpio-controller;
84 };
85 PCA22: pca9698@22 {
86 compatible = "nxp,pca9698";
87 u-boot,dm-pre-reloc;
88 reg = <0x22>;
89 #gpio-cells = <2>;
90 gpio-controller;
91 };
92 PCA23: pca9698@23 {
93 compatible = "nxp,pca9698";
94 reg = <0x23>;
95 #gpio-cells = <2>;
96 gpio-controller;
97 };
98 PCA24: pca9698@24 {
99 compatible = "nxp,pca9698";
100 reg = <0x24>;
101 #gpio-cells = <2>;
102 gpio-controller;
103 };
104 PCA25: pca9698@25 {
105 compatible = "nxp,pca9698";
106 reg = <0x25>;
107 #gpio-cells = <2>;
108 gpio-controller;
109 };
110 PCA26: pca9698@26 {
111 compatible = "nxp,pca9698";
112 reg = <0x26>;
113 #gpio-cells = <2>;
114 gpio-controller;
115 };
116 };
117
118 I2C1: i2c@11100 {
119 status = "okay";
120 clock-frequency = <400000>;
121 at97sc3205t@29 {
122 compatible = "atmel,at97sc3204t";
123 reg = <0x29>;
124 u-boot,i2c-offset-len = <0>;
125 };
126 emc2305@2d {
127 compatible = "smsc,emc2305";
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <0x2d>;
131 fan@0 {
132 reg = <0>;
133 };
134 fan@1 {
135 reg = <1>;
136 };
137 fan@2 {
138 reg = <2>;
139 };
140 fan@3 {
141 reg = <3>;
142 };
143 fan@4 {
144 reg = <4>;
145 };
146 };
147 lm77@48 {
148 compatible = "national,lm77";
149 reg = <0x48>;
150 };
151 ads1015@49 {
152 compatible = "ti,ads1015";
153 reg = <0x49>;
154 };
155 lm77@4a {
156 compatible = "national,lm77";
157 reg = <0x4a>;
158 };
159 ads1015@4b {
160 compatible = "ti,ads1015";
161 reg = <0x4b>;
162 };
163 emc2305@4c {
164 compatible = "smsc,emc2305";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <0x4c>;
168 fan@0 {
169 reg = <0>;
170 };
171 fan@1 {
172 reg = <1>;
173 };
174 fan@2 {
175 reg = <2>;
176 };
177 fan@3 {
178 reg = <3>;
179 };
180 fan@4 {
181 reg = <4>;
182 };
183 };
184 at24c512@54 {
185 compatible = "atmel,24c512";
186 reg = <0x54>;
187 u-boot,i2c-offset-len = <2>;
188 };
189 ds1339@68 {
190 compatible = "dallas,ds1339";
191 reg = <0x68>;
192 };
193 };
194
195 serial@12000 {
196 status = "okay";
197 };
198
199 serial@12100 {
200 status = "okay";
201 };
202
203 ethernet@34000 {
204 status = "okay";
205 phy = <&phy1>;
206 phy-mode = "sgmii";
207 };
208
209 usb@58000 {
210 status = "ok";
211 };
212
213 ethernet@70000 {
214 status = "okay";
215 phy = <&phy0>;
216 phy-mode = "sgmii";
217 };
218
219 mdio@72004 {
220 phy0: ethernet-phy@0 {
221 reg = <1>;
222 };
223
224 phy1: ethernet-phy@1 {
225 reg = <0>;
226 };
227 };
228
229 sata@a8000 {
230 status = "okay";
231 };
232
233 sdhci@d8000 {
234 broken-cd;
235 wp-inverted;
236 bus-width = <4>;
237 status = "okay";
238 no-1-8-v;
239 };
240
241 usb3@f0000 {
242 status = "okay";
243 };
244 };
245
Chris Packham852a0e17c2019-03-16 20:46:20 +1300[diff] [blame]246 pcie {
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]247 status = "okay";
248 /*
249 * The two PCIe units are accessible through
250 * standard PCIe slots on the board.
251 */
252 pcie@3,0 {
253 /* Port 0, Lane 0 */
254 status = "okay";
255 };
256 };
257
258 MDIO0: mdio0 {
259 compatible = "virtual,mdio-gpio";
260 #address-cells = <1>;
261 #size-cells = <0>;
262 gpios = < /*MDC*/ &gpio0 13 0
263 /*MDIO*/ &gpio0 14 0>;
264 mv88e1240@0 {
265 reg = <0x0>;
266 };
267 mv88e1240@1 {
268 reg = <0x1>;
269 };
270 mv88e1240@2 {
271 reg = <0x2>;
272 };
273 mv88e1240@3 {
274 reg = <0x3>;
275 };
276 mv88e1240@4 {
277 reg = <0x4>;
278 };
279 mv88e1240@5 {
280 reg = <0x5>;
281 };
282 mv88e1240@6 {
283 reg = <0x6>;
284 };
285 mv88e1240@7 {
286 reg = <0x7>;
287 };
288 mv88e1240@8 {
289 reg = <0x8>;
290 };
291 mv88e1240@9 {
292 reg = <0x9>;
293 };
294 mv88e1240@a {
295 reg = <0xa>;
296 };
297 mv88e1240@b {
298 reg = <0xb>;
299 };
300 mv88e1240@c {
301 reg = <0xc>;
302 };
303 mv88e1240@d {
304 reg = <0xd>;
305 };
306 mv88e1240@e {
307 reg = <0xe>;
308 };
309 mv88e1240@f {
310 reg = <0xf>;
311 };
312 mv88e1240@10 {
313 reg = <0x10>;
314 };
315 mv88e1240@11 {
316 reg = <0x11>;
317 };
318 mv88e1240@12 {
319 reg = <0x12>;
320 };
321 mv88e1240@13 {
322 reg = <0x13>;
323 };
324 mv88e1240@14 {
325 reg = <0x14>;
326 };
327 mv88e1240@15 {
328 reg = <0x15>;
329 };
330 mv88e1240@16 {
331 reg = <0x16>;
332 };
333 mv88e1240@17 {
334 reg = <0x17>;
335 };
336 mv88e1240@18 {
337 reg = <0x18>;
338 };
339 mv88e1240@19 {
340 reg = <0x19>;
341 };
342 mv88e1240@1a {
343 reg = <0x1a>;
344 };
345 mv88e1240@1b {
346 reg = <0x1b>;
347 };
348 mv88e1240@1c {
349 reg = <0x1c>;
350 };
351 mv88e1240@1d {
352 reg = <0x1d>;
353 };
354 mv88e1240@1e {
355 reg = <0x1e>;
356 };
357 mv88e1240@1f {
358 reg = <0x1f>;
359 };
360 };
361
362 MDIO1: mdio1 {
363 compatible = "virtual,mdio-gpio";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 gpios = < /*MDC*/ &gpio0 25 0
367 /*MDIO*/ &gpio1 13 0>;
368 mv88e1240@0 {
369 reg = <0x0>;
370 };
371 mv88e1240@1 {
372 reg = <0x1>;
373 };
374 mv88e1240@2 {
375 reg = <0x2>;
376 };
377 mv88e1240@3 {
378 reg = <0x3>;
379 };
380 mv88e1240@4 {
381 reg = <0x4>;
382 };
383 mv88e1240@5 {
384 reg = <0x5>;
385 };
386 mv88e1240@6 {
387 reg = <0x6>;
388 };
389 mv88e1240@7 {
390 reg = <0x7>;
391 };
392 mv88e1240@8 {
393 reg = <0x8>;
394 };
395 mv88e1240@9 {
396 reg = <0x9>;
397 };
398 mv88e1240@a {
399 reg = <0xa>;
400 };
401 mv88e1240@b {
402 reg = <0xb>;
403 };
404 mv88e1240@c {
405 reg = <0xc>;
406 };
407 mv88e1240@d {
408 reg = <0xd>;
409 };
410 mv88e1240@e {
411 reg = <0xe>;
412 };
413 mv88e1240@f {
414 reg = <0xf>;
415 };
416 mv88e1240@10 {
417 reg = <0x10>;
418 };
419 mv88e1240@11 {
420 reg = <0x11>;
421 };
422 mv88e1240@12 {
423 reg = <0x12>;
424 };
425 mv88e1240@13 {
426 reg = <0x13>;
427 };
428 mv88e1240@14 {
429 reg = <0x14>;
430 };
431 mv88e1240@15 {
432 reg = <0x15>;
433 };
434 mv88e1240@16 {
435 reg = <0x16>;
436 };
437 mv88e1240@17 {
438 reg = <0x17>;
439 };
440 mv88e1240@18 {
441 reg = <0x18>;
442 };
443 mv88e1240@19 {
444 reg = <0x19>;
445 };
446 mv88e1240@1a {
447 reg = <0x1a>;
448 };
449 mv88e1240@1b {
450 reg = <0x1b>;
451 };
452 mv88e1240@1c {
453 reg = <0x1c>;
454 };
455 mv88e1240@1d {
456 reg = <0x1d>;
457 };
458 mv88e1240@1e {
459 reg = <0x1e>;
460 };
461 mv88e1240@1f {
462 reg = <0x1f>;
463 };
464 };
465
466 MDIO2: mdio2 {
467 compatible = "virtual,mdio-gpio";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 gpios = < /*MDC*/ &gpio1 14 0
471 /*MDIO*/ &gpio0 24 0>;
472 mv88e1240@0 {
473 reg = <0x0>;
474 };
475 mv88e1240@1 {
476 reg = <0x1>;
477 };
478 mv88e1240@2 {
479 reg = <0x2>;
480 };
481 mv88e1240@3 {
482 reg = <0x3>;
483 };
484 mv88e1240@4 {
485 reg = <0x4>;
486 };
487 mv88e1240@5 {
488 reg = <0x5>;
489 };
490 mv88e1240@6 {
491 reg = <0x6>;
492 };
493 mv88e1240@7 {
494 reg = <0x7>;
495 };
496 mv88e1240@8 {
497 reg = <0x8>;
498 };
499 mv88e1240@9 {
500 reg = <0x9>;
501 };
502 mv88e1240@a {
503 reg = <0xa>;
504 };
505 mv88e1240@b {
506 reg = <0xb>;
507 };
508 mv88e1240@c {
509 reg = <0xc>;
510 };
511 mv88e1240@d {
512 reg = <0xd>;
513 };
514 mv88e1240@e {
515 reg = <0xe>;
516 };
517 mv88e1240@f {
518 reg = <0xf>;
519 };
520 mv88e1240@10 {
521 reg = <0x10>;
522 };
523 mv88e1240@11 {
524 reg = <0x11>;
525 };
526 mv88e1240@12 {
527 reg = <0x12>;
528 };
529 mv88e1240@13 {
530 reg = <0x13>;
531 };
532 mv88e1240@14 {
533 reg = <0x14>;
534 };
535 mv88e1240@15 {
536 reg = <0x15>;
537 };
538 };
539 };
540
541 leds {
542 compatible = "gpio-leds";
543
544 finder_led {
545 label = "finder-led";
546 gpios = <&PCA22 25 0>;
547 };
548
549 status_led {
550 label = "status-led";
551 gpios = <&gpio0 29 0>;
552 };
553 };
554};
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]555
556&spi0 {
557 status = "okay";
558 sc16is741: sc16is741@0 {
559 compatible = "nxp,sc16is741";
560 reg = <0>;
561 clocks = <&sc16isclk>;
562 spi-max-frequency = <4000000>;
563 interrupt-parent = <&gpio0>;
564 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
565 gpio-controller;
566 #gpio-cells = <2>;
567 };
568};
569
570&spi1 {
571 status = "okay";
572 u-boot,dm-pre-reloc;
573 spi-flash@0 {
574 #address-cells = <1>;
575 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]576 compatible = "n25q016a", "jedec,spi-nor";
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]577 reg = <0>; /* Chip select 0 */
578 spi-max-frequency = <108000000>;
579 };
580 spi-flash@1 {
581 #address-cells = <1>;
582 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]583 compatible = "n25q128a11", "jedec,spi-nor";
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]584 reg = <1>; /* Chip select 1 */
585 spi-max-frequency = <108000000>;
586 u-boot,dm-pre-reloc;
587 };
588};