Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Collabora Ltd. |
| 4 | * |
| 5 | * Based on include/configs/xpress.h: |
| 6 | * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> |
| 7 | */ |
| 8 | #ifndef __PCL063_H |
| 9 | #define __PCL063_H |
| 10 | |
| 11 | #include <linux/sizes.h> |
| 12 | #include "mx6_common.h" |
| 13 | |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 14 | /* |
| 15 | * There is a bug in some i.MX6UL processors that results in the initial |
| 16 | * portion of OCRAM being unavailable when booting from (at least) an SD |
| 17 | * card. |
| 18 | * |
| 19 | * Tweak the SPL text base address to avoid this. |
| 20 | */ |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 21 | |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 22 | #define CFG_SYS_FSL_USDHC_NUM 1 |
Parthiban Nallathambi | c466938 | 2019-04-10 16:35:32 +0200 | [diff] [blame] | 23 | |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 24 | /* Console configs */ |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 25 | #define CFG_MXC_UART_BASE UART1_BASE |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 26 | |
| 27 | /* MMC Configs */ |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 28 | |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 29 | #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 30 | |
| 31 | /* Miscellaneous configurable options */ |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 32 | |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 33 | /* Physical Memory Map */ |
| 34 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
| 35 | #define PHYS_SDRAM_SIZE SZ_256M |
| 36 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 37 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 38 | #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 39 | #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 40 | |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 41 | /* NAND */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 42 | #define CFG_SYS_NAND_BASE 0x40000000 |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 43 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 44 | #define CFG_EXTRA_ENV_SETTINGS \ |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 45 | "console=ttymxc0,115200n8\0" \ |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 46 | "fdt_addr_r=0x82000000\0" \ |
| 47 | "fdt_high=0xffffffff\0" \ |
| 48 | "initrd_high=0xffffffff\0" \ |
| 49 | "kernel_addr_r=0x81000000\0" \ |
| 50 | "pxefile_addr_r=0x87100000\0" \ |
| 51 | "ramdisk_addr_r=0x82100000\0" \ |
| 52 | "scriptaddr=0x87000000\0" \ |
| 53 | BOOTENV |
| 54 | |
| 55 | #define BOOT_TARGET_DEVICES(func) \ |
| 56 | func(MMC, mmc, 0) \ |
Pali Rohár | dd54f6c | 2022-05-31 10:32:36 +0200 | [diff] [blame] | 57 | func(UBIFS, ubifs, 0, UBI, boot) \ |
Martyn Welch | 0a14bac | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 58 | func(PXE, pxe, na) \ |
| 59 | func(DHCP, dhcp, na) |
| 60 | |
| 61 | #include <config_distro_bootcmd.h> |
| 62 | |
| 63 | #endif /* __PCL063_H */ |