commit 0a14bace898c9439925d2d6075a16ebf6b3607d1
author Martyn Welch <martyn@welchs.me.uk> Tue Dec 11 11:34:46 2018 +0000
committer Stefano Babic <sbabic@denx.de> Mon Jan 28 12:47:27 2019 +0100
tree e7731f4076e5294feaf8f98d4287e9f1538d2dab
parent d1ac23f7d730d350aa36bf468c29d3728f7a6e27

imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>