| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Microchip I2S Multi-Channel Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Codrin Ciubotariu <codrin.ciubotariu@microchip.com> |
| 11 | |
| 12 | description: |
| 13 | The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and |
| 14 | supports a Time Division Multiplexed (TDM) interface with external |
| 15 | multi-channel audio codecs. It consists of a receiver, a transmitter and a |
| 16 | common clock generator that can be enabled separately to provide Adapter, |
| 17 | Client or Controller modes with receiver and/or transmitter active. |
| 18 | On later I2SMCC versions (starting with Microchip's SAMA7G5) I2S |
| 19 | multi-channel is supported by using multiple data pins, output and |
| 20 | input, without TDM. |
| 21 | |
| 22 | properties: |
| 23 | "#sound-dai-cells": |
| 24 | const: 0 |
| 25 | |
| 26 | compatible: |
| 27 | enum: |
| 28 | - microchip,sam9x60-i2smcc |
| 29 | - microchip,sama7g5-i2smcc |
| 30 | |
| 31 | reg: |
| 32 | maxItems: 1 |
| 33 | |
| 34 | interrupts: |
| 35 | maxItems: 1 |
| 36 | |
| 37 | clocks: |
| 38 | items: |
| 39 | - description: Peripheral Bus Clock |
| 40 | - description: Generic Clock (Optional). Should be set mostly when Master |
| 41 | Mode is required. |
| 42 | minItems: 1 |
| 43 | |
| 44 | clock-names: |
| 45 | items: |
| 46 | - const: pclk |
| 47 | - const: gclk |
| 48 | minItems: 1 |
| 49 | |
| 50 | dmas: |
| 51 | items: |
| 52 | - description: TX DMA Channel |
| 53 | - description: RX DMA Channel |
| 54 | |
| 55 | dma-names: |
| 56 | items: |
| 57 | - const: tx |
| 58 | - const: rx |
| 59 | |
| 60 | microchip,tdm-data-pair: |
| 61 | description: |
| 62 | Represents the DIN/DOUT pair pins that are used to receive/send |
| 63 | TDM data. It is optional and it is only needed if the controller |
| 64 | uses the TDM mode. |
| 65 | $ref: /schemas/types.yaml#/definitions/uint8 |
| 66 | enum: [0, 1, 2, 3] |
| 67 | default: 0 |
| 68 | |
| 69 | allOf: |
| 70 | - $ref: dai-common.yaml# |
| 71 | - if: |
| 72 | properties: |
| 73 | compatible: |
| 74 | const: microchip,sam9x60-i2smcc |
| 75 | then: |
| 76 | properties: |
| 77 | microchip,tdm-data-pair: false |
| 78 | |
| 79 | required: |
| 80 | - "#sound-dai-cells" |
| 81 | - compatible |
| 82 | - reg |
| 83 | - interrupts |
| 84 | - clocks |
| 85 | - clock-names |
| 86 | - dmas |
| 87 | - dma-names |
| 88 | |
| 89 | unevaluatedProperties: false |
| 90 | |
| 91 | examples: |
| 92 | - | |
| 93 | #include <dt-bindings/dma/at91.h> |
| 94 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 95 | |
| 96 | i2s@f001c000 { |
| 97 | #sound-dai-cells = <0>; |
| 98 | compatible = "microchip,sam9x60-i2smcc"; |
| 99 | reg = <0xf001c000 0x100>; |
| 100 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; |
| 101 | dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 102 | AT91_XDMAC_DT_PERID(36))>, |
| 103 | <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 104 | AT91_XDMAC_DT_PERID(37))>; |
| 105 | dma-names = "tx", "rx"; |
| 106 | clocks = <&i2s_clk>, <&i2s_gclk>; |
| 107 | clock-names = "pclk", "gclk"; |
| 108 | pinctrl-names = "default"; |
| 109 | pinctrl-0 = <&pinctrl_i2s_default>; |
| 110 | }; |