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Mathieu J. Poirier4a036fe2012-08-03 11:05:12 +00001/*
2 * Copyright (C) ST-Ericsson SA 2009
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <config.h>
20#include <common.h>
21#include <malloc.h>
22#include <i2c.h>
23#include <mmc.h>
24#include <asm/types.h>
25#include <asm/io.h>
26#include <asm/errno.h>
27#include <asm/arch/db8500_pincfg.h>
Mathieu J. Poiriercc1bb792012-07-31 08:59:28 +000028#include <asm/arch/prcmu.h>
29#include <asm/arch/hardware.h>
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +000030#include <asm/arch/sys_proto.h>
Mathieu J. Poirier4a036fe2012-08-03 11:05:12 +000031
32#include "db8500_pins.h"
33
34/*
35 * Get a global data pointer
36 */
37DECLARE_GLOBAL_DATA_PTR;
38
39/*
40 * Memory controller register
41 */
42#define DMC_BASE_ADDR 0x80156000
43#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
44
45/*
46 * GPIO pin config common for MOP500/HREF boards
47 */
48unsigned long gpio_cfg_common[] = {
49 /* I2C */
50 GPIO147_I2C0_SCL,
51 GPIO148_I2C0_SDA,
52 GPIO16_I2C1_SCL,
53 GPIO17_I2C1_SDA,
54 GPIO10_I2C2_SDA,
55 GPIO11_I2C2_SCL,
56 GPIO229_I2C3_SDA,
57 GPIO230_I2C3_SCL,
58
59 /* SSP0, to AB8500 */
60 GPIO143_SSP0_CLK,
61 GPIO144_SSP0_FRM,
62 GPIO145_SSP0_RXD | PIN_PULL_DOWN,
63 GPIO146_SSP0_TXD,
64
65 /* MMC0 (MicroSD card) */
66 GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
67 GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
68 GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
69 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
70 GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
71 GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
72 GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
73 GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
74 GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
75 GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
76 GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
77
78 /* MMC4 (On-board eMMC) */
79 GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
80 GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
81 GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
82 GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
83 GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
84 GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
85 GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
86 GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
87 GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
88 GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
89 GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
90
91 /* UART2, console */
92 GPIO29_U2_RXD | PIN_INPUT_PULLUP,
93 GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
94 GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
95 GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
96
97 /*
98 * USB, pin 256-267 USB, Is probably already setup correctly from
99 * BootROM/boot stages, but we don't trust that and set it up anyway
100 */
101 GPIO256_USB_NXT,
102 GPIO257_USB_STP,
103 GPIO258_USB_XCLK,
104 GPIO259_USB_DIR,
105 GPIO260_USB_DAT7,
106 GPIO261_USB_DAT6,
107 GPIO262_USB_DAT5,
108 GPIO263_USB_DAT4,
109 GPIO264_USB_DAT3,
110 GPIO265_USB_DAT2,
111 GPIO266_USB_DAT1,
112 GPIO267_USB_DAT0,
113};
114
115unsigned long gpio_cfg_snowball[] = {
116 /* MMC0 (MicroSD card) */
117 GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */
118 GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */
119 GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */
120
121 /* eMMC */
122 GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */
123
124 /* LAN */
125 GPIO131_SM_ADQ8,
126 GPIO132_SM_ADQ9,
127 GPIO133_SM_ADQ10,
128 GPIO134_SM_ADQ11,
129 GPIO135_SM_ADQ12,
130 GPIO136_SM_ADQ13,
131 GPIO137_SM_ADQ14,
132 GPIO138_SM_ADQ15,
133
134 /* RSTn_LAN */
135 GPIO141_GPIO | PIN_OUTPUT_HIGH,
136};
137
138/*
139 * Miscellaneous platform dependent initialisations
140 */
141
142int board_init(void)
143{
144 /*
145 * Setup board (bd) and board-info (bi).
146 * bi_arch_number: Unique id for this board. It will passed in r1 to
147 * Linux startup code and is the machine_id.
148 * bi_boot_params: Where this board expects params.
149 */
150 gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL;
151 gd->bd->bi_boot_params = 0x00000100;
152
153 /* Configure GPIO pins needed by U-boot */
154 db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common));
155
156 db8500_gpio_config_pins(gpio_cfg_snowball,
157 ARRAY_SIZE(gpio_cfg_snowball));
158
159 return 0;
160}
161
162int dram_init(void)
163{
164 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
165 gd->ram_size = gd->bd->bi_dram[0].size =
166 get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
167
168 return 0;
169}
Mathieu J. Poiriercc1bb792012-07-31 08:59:28 +0000170
171static int raise_ab8500_gpio16(void)
172{
173 int ret;
174
175 /* selection */
176 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG);
177 if (ret < 0)
178 goto out;
179
180 ret |= 0x80;
181 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret);
182 if (ret < 0)
183 goto out;
184
185 /* direction */
186 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG);
187 if (ret < 0)
188 goto out;
189
190 ret |= 0x80;
191 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret);
192 if (ret < 0)
193 goto out;
194
195 /* out */
196 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG);
197 if (ret < 0)
198 goto out;
199
200 ret |= 0x80;
201 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret);
202
203out:
204 return ret;
205}
206
207static int raise_ab8500_gpio26(void)
208{
209 int ret;
210
211 /* selection */
212 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG);
213 if (ret < 0)
214 goto out;
215
216 ret |= 0x2;
217 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret);
218 if (ret < 0)
219 goto out;
220
221 /* out */
222 ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG);
223 if (ret < 0)
224 goto out;
225
226 ret |= 0x2;
227 ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret);
228
229out:
230 return ret;
231}
232
233int board_late_init(void)
234{
235 /* enable 3V3 for LAN controller */
236 if (raise_ab8500_gpio26() >= 0) {
237 /* Turn on FSMC device */
238 writel(0x1, 0x8000f000);
239 writel(0x1, 0x8000f008);
240
241 /* setup FSMC for LAN controler */
242 writel(0x305b, 0x80000000);
243
244 /* run at the highest possible speed */
245 writel(0x01010210, 0x80000004);
246 } else
247 printf("error: can't raise GPIO26\n");
248
249 /* enable 3v6 for GBF chip */
250 if ((raise_ab8500_gpio16() < 0))
251 printf("error: cant' raise GPIO16\n");
252
Mathieu J. Poiriera50f83b2012-07-31 08:59:30 +0000253#ifdef CONFIG_MMC
254 u8500_mmc_power_init();
255#endif /* CONFIG_MMC */
256
Mathieu J. Poiriercc1bb792012-07-31 08:59:28 +0000257 return 0;
258}