Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 1 | /* |
Stefan Roese | fc85260 | 2007-04-29 14:13:01 +0200 | [diff] [blame] | 2 | * (C) Copyright 2005-2007 |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /************************************************************************ |
| 9 | * bamboo.h - configuration for BAMBOO board |
| 10 | ***********************************************************************/ |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /*----------------------------------------------------------------------- |
| 15 | * High Level Configuration Options |
| 16 | *----------------------------------------------------------------------*/ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 17 | #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ |
Stefan Roese | b30f2a1 | 2005-08-08 12:42:22 +0200 | [diff] [blame] | 18 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
Grzegorz Bernacki | 837bc5b | 2007-06-15 11:19:28 +0200 | [diff] [blame] | 19 | #define CONFIG_440 1 /* ... PPC440 family */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 20 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
| 21 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 22 | #ifndef CONFIG_SYS_TEXT_BASE |
| 23 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
| 24 | #endif |
| 25 | |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 26 | /* |
| 27 | * Include common defines/options for all AMCC eval boards |
| 28 | */ |
| 29 | #define CONFIG_HOSTNAME bamboo |
| 30 | #include "amcc-common.h" |
| 31 | |
Tom Rini | e3e4f7d | 2016-01-19 13:01:59 -0500 | [diff] [blame] | 32 | /* Reclaim some space. */ |
| 33 | #undef CONFIG_SYS_LONGHELP |
| 34 | |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 35 | /* |
| 36 | * Please note that, if NAND support is enabled, the 2nd ethernet port |
| 37 | * can't be used because of pin multiplexing. So, if you want to use the |
| 38 | * 2nd ethernet port you have to "undef" the following define. |
| 39 | */ |
| 40 | #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ |
| 41 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 42 | /*----------------------------------------------------------------------- |
| 43 | * Base addresses -- Note these are effective addresses where the |
| 44 | * actual resources get mapped (not physical addresses) |
| 45 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ |
| 47 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ |
| 48 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 |
| 49 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 |
| 50 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 51 | |
| 52 | /*Don't change either of these*/ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 53 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 54 | /*Don't change either of these*/ |
| 55 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
| 57 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000 |
| 58 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
| 59 | #define CONFIG_SYS_NAND_ADDR 0x90000000 |
| 60 | #define CONFIG_SYS_NAND2_ADDR 0x94000000 |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 61 | |
| 62 | /*----------------------------------------------------------------------- |
| 63 | * Initial RAM & stack pointer (placed in SDRAM) |
| 64 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
| 66 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 70 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 71 | /*----------------------------------------------------------------------- |
| 72 | * Serial Port |
| 73 | *----------------------------------------------------------------------*/ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 74 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 76 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 77 | /*----------------------------------------------------------------------- |
| 78 | * NVRAM/RTC |
| 79 | * |
| 80 | * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF |
| 81 | * The DS1558 code assumes this condition |
| 82 | * |
| 83 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 85 | #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 86 | |
| 87 | /*----------------------------------------------------------------------- |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 88 | * Environment |
| 89 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 90 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 91 | |
| 92 | /*----------------------------------------------------------------------- |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 93 | * FLASH related |
| 94 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ |
| 96 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 97 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 98 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 99 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 100 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 101 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_FLASH_ADDR0 0x555 |
| 103 | #define CONFIG_SYS_FLASH_ADDR1 0x2aa |
| 104 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 105 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ |
| 107 | #define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 108 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 109 | #ifdef CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 110 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 112 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 113 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 114 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 115 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 116 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 117 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 118 | |
| 119 | /*----------------------------------------------------------------------- |
Stefan Roese | fc85260 | 2007-04-29 14:13:01 +0200 | [diff] [blame] | 120 | * NAND FLASH |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 121 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
| 124 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } |
| 125 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_NAND_CS 1 |
Stefan Roese | 4274351 | 2007-06-01 15:27:11 +0200 | [diff] [blame] | 127 | |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 128 | /*----------------------------------------------------------------------- |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 129 | * DDR SDRAM |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 130 | *----------------------------------------------------------------------------- */ |
| 131 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ |
Stefan Roese | c45d1e3 | 2005-11-15 16:04:58 +0100 | [diff] [blame] | 132 | #undef CONFIG_DDR_ECC /* don't use ECC */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ |
| 134 | #define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51} |
| 135 | #define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 136 | #define CONFIG_PROG_SDRAM_TLB |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 137 | |
| 138 | /*----------------------------------------------------------------------- |
| 139 | * I2C |
| 140 | *----------------------------------------------------------------------*/ |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 141 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 142 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) |
| 144 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 145 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 146 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 147 | |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 148 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 149 | #define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ |
| 150 | #define CONFIG_ENV_OFFSET 0x0 |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 151 | #endif /* CONFIG_ENV_IS_IN_EEPROM */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 152 | |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 153 | /* |
| 154 | * Default environment variables |
| 155 | */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 156 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 157 | CONFIG_AMCC_DEF_ENV \ |
| 158 | CONFIG_AMCC_DEF_ENV_POWERPC \ |
| 159 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ |
| 160 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 161 | "kernel_addr=fff00000\0" \ |
| 162 | "ramdisk_addr=fff10000\0" \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 163 | "" |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 164 | |
Stefan Roese | a98dfe6 | 2008-05-08 11:05:15 +0200 | [diff] [blame] | 165 | #define CONFIG_HAS_ETH0 |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 166 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
Stefan Roese | 0c7ffc0 | 2005-08-16 18:18:00 +0200 | [diff] [blame] | 167 | #define CONFIG_PHY1_ADDR 1 |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 168 | |
| 169 | #ifndef CONFIG_BAMBOO_NAND |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 170 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 171 | #endif /* CONFIG_BAMBOO_NAND */ |
| 172 | |
Stefan Roese | b30f2a1 | 2005-08-08 12:42:22 +0200 | [diff] [blame] | 173 | #ifdef CONFIG_440EP |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 174 | /* USB */ |
| 175 | #define CONFIG_USB_OHCI |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 176 | |
| 177 | /*Comment this out to enable USB 1.1 device*/ |
| 178 | #define USB_2_0_DEVICE |
Stefan Roese | b30f2a1 | 2005-08-08 12:42:22 +0200 | [diff] [blame] | 179 | #endif /*CONFIG_440EP*/ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 180 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 181 | /* |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 182 | * Commands additional to the ones defined in amcc-common.h |
Jon Loeliger | e54e77a | 2007-07-10 09:29:01 -0500 | [diff] [blame] | 183 | */ |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 184 | #define CONFIG_CMD_DATE |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 185 | #define CONFIG_CMD_PCI |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 186 | #define CONFIG_CMD_SDRAM |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 187 | |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 188 | #ifdef CONFIG_BAMBOO_NAND |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 189 | #define CONFIG_CMD_NAND |
| 190 | #endif |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 191 | |
Stefan Roese | 764784c | 2005-10-14 15:37:34 +0200 | [diff] [blame] | 192 | #define CONFIG_SUPPORT_VFAT |
| 193 | |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 194 | /* Partitions */ |
Stefan Roese | 529330e | 2006-07-27 16:14:05 +0200 | [diff] [blame] | 195 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 196 | /*----------------------------------------------------------------------- |
| 197 | * PCI stuff |
| 198 | *----------------------------------------------------------------------- |
| 199 | */ |
| 200 | /* General PCI */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 201 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 202 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 204 | |
| 205 | /* Board-specific PCI */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 207 | #define CONFIG_SYS_PCI_MASTER_INIT |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 208 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 210 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 211 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 212 | #endif /* __CONFIG_H */ |