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git01.mediatek.com / filogic / uboot / a431289a1023a34ac006788f856131524e29e3cb / . / arch / arm / dts / rk3308-rock-pi-s-u-boot.dtsi
blob: a6fb8b12da384cb6ff697b5dca994e2e09416559 [file] [log] [blame]
Akash Gajjar60a9f712023-02-14 21:01:09 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
4 */
5#include "rk3308-u-boot.dtsi"
6
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]7&emmc {
8 cap-sd-highspeed;
9 pinctrl-names = "default";
10 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
Akash Gajjar60a9f712023-02-14 21:01:09 +0530[diff] [blame]11};
12
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]13&emmc_bus4 {
14 bootph-pre-ram;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]15 bootph-some-ram;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]16};
17
Jonas Karlman905cc162024-04-08 18:14:10 +0000[diff] [blame]18&u2phy_otg {
19 /delete-property/ phy-supply;
20};
21
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]22&uart0 {
23 bootph-all;
24 clock-frequency = <24000000>;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]25};
26
27&uart0_cts {
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]28 bootph-all;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]29};
30
31&uart0_rts {
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]32 bootph-all;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]33};
34
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame]35&uart0_xfer {
36 bootph-all;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]37};
Jonas Karlmanc8c20092024-04-08 18:14:07 +0000[diff] [blame]38
Jonas Karlman905cc162024-04-08 18:14:10 +0000[diff] [blame]39&vcc5v0_otg {
40 /delete-property/ regulator-always-on;
41};
42
Jonas Karlmanc8c20092024-04-08 18:14:07 +0000[diff] [blame]43&vdd_core {
44 regulator-init-microvolt = <1015000>;
45};