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git01.mediatek.com / filogic / uboot / a499c98cbf7aa5e946c7e767176cc9156059651c / . / arch / arm / dts / rk3308-rock-pi-s-u-boot.dtsi
blob: e458fb3142ee998aa80a612aa6c4500bb84b9f00 [file] [log] [blame]
Akash Gajjar60a9f712023-02-14 21:01:09 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
4 */
5#include "rk3308-u-boot.dtsi"
6
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame^]7&emmc {
8 cap-sd-highspeed;
9 pinctrl-names = "default";
10 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
Akash Gajjar60a9f712023-02-14 21:01:09 +0530[diff] [blame]11};
12
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame^]13&emmc_bus4 {
14 bootph-pre-ram;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]15 bootph-some-ram;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]16};
17
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame^]18&uart0 {
19 bootph-all;
20 clock-frequency = <24000000>;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]21};
22
23&uart0_cts {
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame^]24 bootph-all;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]25};
26
27&uart0_rts {
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame^]28 bootph-all;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]29};
30
Jonas Karlmana499c982024-04-08 18:14:03 +0000[diff] [blame^]31&uart0_xfer {
32 bootph-all;
Massimo Pegorer03b293b2023-08-03 13:08:13 +0200[diff] [blame]33};