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git01.mediatek.com / filogic / uboot / a3d6939ca80e6628505268a9753ad42e50529efb / . / dts / upstream / src / arm64 / mediatek / mt8395-radxa-nio-12l.dts
blob: e5d9b671a405717372923f6e041b5b784d3295d9 [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2023 Radxa Limited
4 * Copyright (C) 2024 Collabora Ltd.
5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6 */
7
8#include "mt8195.dtsi"
9#include "mt6359.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
13#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
14#include <dt-bindings/spmi/spmi.h>
15#include <dt-bindings/usb/pd.h>
16
17/ {
18 model = "Radxa NIO 12L";
19 chassis-type = "embedded";
20 compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195";
21
22 aliases {
23 i2c0 = &i2c2;
24 i2c1 = &i2c3;
25 i2c2 = &i2c4;
26 i2c3 = &i2c0;
27 i2c4 = &i2c1;
28 ethernet0 = &eth;
29 serial0 = &uart0;
30 serial1 = &uart1;
31 spi0 = &spi1;
32 spi1 = &spi2;
33 };
34
35 chosen {
36 stdout-path = "serial0:921600n8";
37 };
38
39 firmware {
40 optee {
41 compatible = "linaro,optee-tz";
42 method = "smc";
43 };
44 };
45
46 memory@40000000 {
47 device_type = "memory";
48 reg = <0 0x40000000 0x1 0x0>;
49 };
50
51 wifi_vreg: regulator-wifi-3v3-en {
52 compatible = "regulator-fixed";
53 regulator-name = "wifi_3v3_en";
54 regulator-always-on;
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 enable-active-high;
58 gpio = <&pio 67 GPIO_ACTIVE_HIGH>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&wifi_vreg_pins>;
61 vin-supply = <&vsys>;
62 };
63
64 /* system wide switching 5.0V power rail */
65 vsys: regulator-vsys {
66 compatible = "regulator-fixed";
67 regulator-name = "vsys";
68 regulator-always-on;
69 regulator-boot-on;
70 regulator-min-microvolt = <5000000>;
71 regulator-max-microvolt = <5000000>;
72 vin-supply = <&vcc5v0_vsys>;
73 };
74
75 vsys_buck: regulator-vsys-buck {
76 compatible = "regulator-fixed";
77 regulator-name = "vsys_buck";
78 regulator-always-on;
79 regulator-boot-on;
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 vin-supply = <&vcc5v0_vsys>;
83 };
84
85 /* Rail from power-only "TYPE C DC" port */
86 vcc5v0_vsys: regulator-vcc5v0-sys {
87 compatible = "regulator-fixed";
88 regulator-name = "vcc5v0_sys";
89 regulator-always-on;
90 regulator-boot-on;
91 };
92
93 reserved-memory {
94 #address-cells = <2>;
95 #size-cells = <2>;
96 ranges;
97
98 /*
99 * 12 MiB reserved for OP-TEE (BL32)
100 * +-----------------------+ 0x43e0_0000
101 * | SHMEM 2MiB |
102 * +-----------------------+ 0x43c0_0000
103 * | | TA_RAM 8MiB |
104 * + TZDRAM +--------------+ 0x4340_0000
105 * | | TEE_RAM 2MiB |
106 * +-----------------------+ 0x4320_0000
107 */
108 optee_reserved: optee@43200000 {
109 reg = <0 0x43200000 0 0xc00000>;
110 no-map;
111 };
112
113 scp_mem: memory@50000000 {
114 compatible = "shared-dma-pool";
115 reg = <0 0x50000000 0 0x2900000>;
116 no-map;
117 };
118
119 vpu_mem: memory@53000000 {
120 compatible = "shared-dma-pool";
121 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
122 };
123
124 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
125 bl31_secmon_mem: memory@54600000 {
126 reg = <0 0x54600000 0x0 0x200000>;
127 no-map;
128 };
129
130 afe_mem: memory@60000000 {
131 compatible = "shared-dma-pool";
132 reg = <0 0x60000000 0 0x1100000>;
133 no-map;
134 };
135
136 apu_mem: memory@62000000 {
137 compatible = "shared-dma-pool";
138 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
139 };
140 };
141};
142
143&eth {
144 phy-mode = "rgmii-rxid";
145 phy-handle = <&rgmii_phy>;
146 pinctrl-names = "default", "sleep";
147 pinctrl-0 = <&eth_default_pins>;
148 pinctrl-1 = <&eth_sleep_pins>;
149 mediatek,tx-delay-ps = <2030>;
150 mediatek,mac-wol;
151 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
152 snps,reset-delays-us = <0 20000 100000>;
153 status = "okay";
154
155 mdio {
156 rgmii_phy: ethernet-phy@1 {
157 compatible = "ethernet-phy-id001c.c916";
158 reg = <0x1>;
159 };
160 };
161};
162
163&gpu {
164 mali-supply = <&mt6315_7_vbuck1>;
165 status = "okay";
166};
167
168&i2c2 {
169 clock-frequency = <400000>;
170 pinctrl-0 = <&i2c2_pins>;
171 pinctrl-names = "default";
172 status = "okay";
173
174 typec-mux@48 {
175 compatible = "ite,it5205";
176 reg = <0x48>;
177
178 mode-switch;
179 orientation-switch;
180
181 vcc-supply = <&mt6359_vibr_ldo_reg>;
182
183 port {
184 it5205_sbu_mux: endpoint {
185 remote-endpoint = <&typec_con_mux>;
186 };
187 };
188 };
189};
190
191&i2c4 {
192 clock-frequency = <400000>;
193 pinctrl-0 = <&i2c4_pins>;
194 pinctrl-names = "default";
195 status = "okay";
196
197 /* I2C4 exposed at 39-pins MIPI-LCD connector */
198};
199
200&i2c6 {
201 clock-frequency = <400000>;
202 pinctrl-0 = <&i2c6_pins>;
203 pinctrl-names = "default";
204 status = "okay";
205
206 mt6360: pmic@34 {
207 compatible = "mediatek,mt6360";
208 reg = <0x34>;
209 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
210 interrupt-names = "IRQB";
211 interrupt-controller;
212 #interrupt-cells = <1>;
213 pinctrl-0 = <&mt6360_pins>;
214
215 charger {
216 compatible = "mediatek,mt6360-chg";
217 richtek,vinovp-microvolt = <14500000>;
218
219 otg_vbus_regulator: usb-otg-vbus-regulator {
220 regulator-name = "usb-otg-vbus";
221 regulator-min-microvolt = <4425000>;
222 regulator-max-microvolt = <5825000>;
223 };
224 };
225
226 regulator {
227 compatible = "mediatek,mt6360-regulator";
228 LDO_VIN1-supply = <&vsys_buck>;
229 LDO_VIN3-supply = <&mt6360_buck2>;
230
231 mt6360_buck1: buck1 {
232 regulator-name = "emi_vdd2";
233 regulator-min-microvolt = <300000>;
234 regulator-max-microvolt = <1300000>;
235 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
236 MT6360_OPMODE_LP
237 MT6360_OPMODE_ULP>;
238 regulator-always-on;
239 };
240
241 mt6360_buck2: buck2 {
242 regulator-name = "emi_vddq";
243 regulator-min-microvolt = <300000>;
244 regulator-max-microvolt = <1300000>;
245 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
246 MT6360_OPMODE_LP
247 MT6360_OPMODE_ULP>;
248 regulator-always-on;
249 };
250
251 mt6360_ldo1: ldo1 {
252 regulator-name = "ext_lcd_3v3";
253 regulator-min-microvolt = <3300000>;
254 regulator-max-microvolt = <3300000>;
255 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
256 MT6360_OPMODE_LP>;
257 regulator-always-on;
258 };
259
260 mt6360_ldo2: ldo2 {
261 regulator-name = "panel1_p1v8";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
265 MT6360_OPMODE_LP>;
266 };
267
268 mt6360_ldo3: ldo3 {
269 regulator-name = "vmc_pmu";
270 regulator-min-microvolt = <1200000>;
271 regulator-max-microvolt = <3600000>;
272 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
273 MT6360_OPMODE_LP>;
274 };
275
276 mt6360_ldo5: ldo5 {
277 regulator-name = "vmch_pmu";
278 regulator-min-microvolt = <3300000>;
279 regulator-max-microvolt = <3300000>;
280 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
281 MT6360_OPMODE_LP>;
282 regulator-always-on;
283 };
284
285 mt6360_ldo6: ldo6 {
286 regulator-name = "mt6360_ldo6"; /* Test point */
287 regulator-min-microvolt = <500000>;
288 regulator-max-microvolt = <2100000>;
289 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
290 MT6360_OPMODE_LP>;
291 };
292
293 mt6360_ldo7: ldo7 {
294 regulator-name = "emi_vmddr_en";
295 regulator-min-microvolt = <500000>;
296 regulator-max-microvolt = <2100000>;
297 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
298 MT6360_OPMODE_LP>;
299 regulator-always-on;
300 };
301 };
302
303 typec {
304 compatible = "mediatek,mt6360-tcpc";
305 interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>;
306 interrupt-names = "PD_IRQB";
307
308 connector {
309 compatible = "usb-c-connector";
310 label = "USB-C";
311 data-role = "dual";
312 op-sink-microwatt = <10000000>;
313 power-role = "dual";
314 try-power-role = "sink";
315
316 source-pdos = <PDO_FIXED(5000, 1000,
317 PDO_FIXED_DUAL_ROLE |
318 PDO_FIXED_DATA_SWAP)>;
319 sink-pdos = <PDO_FIXED(5000, 3000,
320 PDO_FIXED_DUAL_ROLE |
321 PDO_FIXED_DATA_SWAP)>;
322
323 ports {
324 #address-cells = <1>;
325 #size-cells = <0>;
326
327 port@0 {
328 reg = <0>;
329 typec_con_hs: endpoint {
330 remote-endpoint = <&mtu3_hs0_role_sw>;
331 };
332 };
333
334 port@2 {
335 reg = <2>;
336 typec_con_mux: endpoint {
337 remote-endpoint = <&it5205_sbu_mux>;
338 };
339 };
340 };
341 };
342 };
343 };
344};
345
346/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */
347&mmc0 {
348 pinctrl-names = "default", "state_uhs";
349 pinctrl-0 = <&mmc0_default_pins>;
350 pinctrl-1 = <&mmc0_uhs_pins>;
351 bus-width = <8>;
352 max-frequency = <200000000>;
353 hs400-ds-delay = <0x14c11>;
354 cap-mmc-highspeed;
355 cap-mmc-hw-reset;
356 mmc-hs200-1_8v;
357 mmc-hs400-1_8v;
358 no-sdio;
359 no-sd;
360 non-removable;
361 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
362 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
363 status = "okay";
364};
365
366/* MMC1 Controller: MicroSD card slot */
367&mmc1 {
368 pinctrl-names = "default", "state_uhs";
369 pinctrl-0 = <&mmc1_default_pins>, <&mmc1_pins_detect>;
370 pinctrl-1 = <&mmc1_default_pins>;
371 bus-width = <4>;
372 max-frequency = <200000000>;
373 cap-sd-highspeed;
374 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
375 no-mmc;
376 no-sdio;
377 sd-uhs-sdr50;
378 sd-uhs-sdr104;
379 vmmc-supply = <&mt6360_ldo5>;
380 vqmmc-supply = <&mt6360_ldo3>;
381 status = "okay";
382};
383
384&mt6359_vaud18_ldo_reg {
385 regulator-always-on;
386};
387
388&mt6359_vbbck_ldo_reg {
389 regulator-always-on;
390};
391
392/* For USB Hub */
393&mt6359_vcamio_ldo_reg {
394 regulator-always-on;
395};
396
397&mt6359_vcn33_2_bt_ldo_reg {
398 regulator-min-microvolt = <3300000>;
399 regulator-max-microvolt = <3300000>;
400};
401
402&mt6359_vcore_buck_reg {
403 regulator-always-on;
404};
405
406&mt6359_vgpu11_buck_reg {
407 regulator-always-on;
408};
409
410&mt6359_vproc1_buck_reg {
411 regulator-always-on;
412};
413
414&mt6359_vproc2_buck_reg {
415 regulator-always-on;
416};
417
418&mt6359_vpu_buck_reg {
419 regulator-always-on;
420};
421
422&mt6359_vrf12_ldo_reg {
423 regulator-always-on;
424};
425
426&mt6359_vsram_md_ldo_reg {
427 regulator-always-on;
428};
429
430/* for GPU SRAM */
431&mt6359_vsram_others_ldo_reg {
432 regulator-min-microvolt = <750000>;
433 regulator-max-microvolt = <750000>;
434};
435
436&pio {
437 eth_default_pins: eth-default-pins {
438 pins-cc {
439 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
440 <PINMUX_GPIO86__FUNC_GBE_RXC>,
441 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
442 <PINMUX_GPIO88__FUNC_GBE_TXEN>;
443 drive-strength = <8>;
444 };
445
446 pins-mdio {
447 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
448 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
449 input-enable;
450 };
451
452 pins-power {
453 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
454 <PINMUX_GPIO92__FUNC_GPIO92>;
455 output-high;
456 };
457
458 pins-rst {
459 pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
460 };
461
462 pins-rxd {
463 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
464 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
465 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
466 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
467 };
468
469 pins-txd {
470 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
471 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
472 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
473 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
474 drive-strength = <8>;
475 };
476 };
477
478 eth_sleep_pins: eth-sleep-pins {
479 pins-cc {
480 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
481 <PINMUX_GPIO86__FUNC_GPIO86>,
482 <PINMUX_GPIO87__FUNC_GPIO87>,
483 <PINMUX_GPIO88__FUNC_GPIO88>;
484 };
485
486 pins-mdio {
487 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
488 <PINMUX_GPIO90__FUNC_GPIO90>;
489 bias-disable;
490 input-disable;
491 };
492
493 pins-rxd {
494 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
495 <PINMUX_GPIO82__FUNC_GPIO82>,
496 <PINMUX_GPIO83__FUNC_GPIO83>,
497 <PINMUX_GPIO84__FUNC_GPIO84>;
498 };
499
500 pins-txd {
501 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
502 <PINMUX_GPIO78__FUNC_GPIO78>,
503 <PINMUX_GPIO79__FUNC_GPIO79>,
504 <PINMUX_GPIO80__FUNC_GPIO80>;
505 };
506 };
507
508 i2c2_pins: i2c2-pins {
509 pins-bus {
510 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
511 <PINMUX_GPIO13__FUNC_SCL2>;
512 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
513 drive-strength = <6>;
514 drive-strength-microamp = <1000>;
515 };
516 };
517
518 i2c4_pins: i2c4-pins {
519 pins-bus {
520 pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
521 <PINMUX_GPIO17__FUNC_SCL4>;
522 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
523 drive-strength-microamp = <1000>;
524 };
525 };
526
527 i2c6_pins: i2c6-pins {
528 pins {
529 pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
530 <PINMUX_GPIO26__FUNC_SCL6>;
531 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
532 };
533 };
534
535 mmc0_default_pins: mmc0-default-pins {
536 pins-clk {
537 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
538 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
539 drive-strength = <6>;
540 };
541
542 pins-cmd-dat {
543 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
544 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
545 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
546 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
547 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
548 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
549 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
550 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
551 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
552 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
553 drive-strength = <6>;
554 input-enable;
555 };
556
557 pins-rst {
558 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
559 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
560 drive-strength = <6>;
561 };
562 };
563
564 mmc0_uhs_pins: mmc0-uhs-pins {
565 pins-clk {
566 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
567 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
568 drive-strength = <8>;
569 };
570
571 pins-cmd-dat {
572 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
573 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
574 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
575 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
576 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
577 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
578 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
579 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
580 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
581 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
582 drive-strength = <8>;
583 input-enable;
584 };
585
586 pins-ds {
587 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
588 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
589 drive-strength = <8>;
590 };
591
592 pins-rst {
593 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
594 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
595 drive-strength = <8>;
596 };
597 };
598
599 mmc1_default_pins: mmc1-default-pins {
600 pins-clk {
601 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
602 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
603 drive-strength = <8>;
604 };
605
606 pins-cmd-dat {
607 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
608 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
609 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
610 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
611 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
612 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
613 drive-strength = <8>;
614 input-enable;
615 };
616 };
617
618 mmc1_pins_detect: mmc1-detect-pins {
619 pins-insert {
620 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
621 bias-pull-up;
622 };
623 };
624
625 mt6360_pins: mt6360-pins {
626 pins-irq {
627 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>,
628 <PINMUX_GPIO101__FUNC_GPIO101>;
629 input-enable;
630 bias-pull-up;
631 };
632 };
633
634 pcie0_default_pins: pcie0-default-pins {
635 pins-bus {
636 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
637 <PINMUX_GPIO20__FUNC_PERSTN>,
638 <PINMUX_GPIO21__FUNC_CLKREQN>;
639 bias-pull-up;
640 };
641 };
642
643 pcie1_default_pins: pcie1-default-pins {
644 pins-bus {
645 pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>,
646 <PINMUX_GPIO1__FUNC_CLKREQN_1>,
647 <PINMUX_GPIO2__FUNC_WAKEN_1>;
648 bias-disable;
649 };
650 };
651
652 spi1_pins: spi1-default-pins {
653 pins-bus {
654 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
655 <PINMUX_GPIO137__FUNC_SPIM1_CLK>,
656 <PINMUX_GPIO138__FUNC_SPIM1_MO>,
657 <PINMUX_GPIO139__FUNC_SPIM1_MI>;
658 bias-disable;
659 };
660 };
661
662 spi2_pins: spi2-default-pins {
663 pins-bus {
664 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
665 <PINMUX_GPIO141__FUNC_SPIM2_CLK>,
666 <PINMUX_GPIO142__FUNC_SPIM2_MO>,
667 <PINMUX_GPIO143__FUNC_SPIM2_MI>;
668 bias-disable;
669 };
670 };
671
672 uart0_pins: uart0-pins {
673 pins-bus {
674 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
675 <PINMUX_GPIO99__FUNC_URXD0>;
676 };
677 };
678
679 uart1_pins: uart1-pins {
680 pins-bus {
681 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
682 <PINMUX_GPIO103__FUNC_URXD1>;
683 };
684 };
685
686 wifi_vreg_pins: wifi-vreg-pins {
687 pins-wifi-pmu-en {
688 pinmux = <PINMUX_GPIO65__FUNC_GPIO65>;
689 output-high;
690 };
691
692 pins-wifi-vreg-en {
693 pinmux = <PINMUX_GPIO67__FUNC_GPIO67>;
694 };
695 };
696};
697
698&pcie0 {
699 pinctrl-names = "default";
700 pinctrl-0 = <&pcie0_default_pins>;
701 status = "okay";
702};
703
704&pcie1 {
705 pinctrl-names = "default";
706 pinctrl-0 = <&pcie1_default_pins>;
707 status = "okay";
708};
709
710&pmic {
711 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
712};
713
714&scp {
715 memory-region = <&scp_mem>;
716 status = "okay";
717};
718
719&spi1 {
720 /* Exposed at 40 pin connector */
721 pinctrl-0 = <&spi1_pins>;
722 pinctrl-names = "default";
723 mediatek,pad-select = <0>;
724 #address-cells = <1>;
725 #size-cells = <0>;
726 status = "okay";
727};
728
729&spi2 {
730 /* Exposed at 40 pin connector */
731 pinctrl-0 = <&spi2_pins>;
732 pinctrl-names = "default";
733 mediatek,pad-select = <0>;
734 #address-cells = <1>;
735 #size-cells = <0>;
736 status = "okay";
737};
738
739&spmi {
740 #address-cells = <2>;
741 #size-cells = <0>;
742
743 mt6315_6: pmic@6 {
744 compatible = "mediatek,mt6315-regulator";
745 reg = <0x6 SPMI_USID>;
746
747 regulators {
748 mt6315_6_vbuck1: vbuck1 {
749 regulator-compatible = "vbuck1";
750 regulator-name = "Vbcpu";
751 regulator-min-microvolt = <300000>;
752 regulator-max-microvolt = <1193750>;
753 regulator-enable-ramp-delay = <256>;
754 regulator-allowed-modes = <0 1 2>;
755 regulator-always-on;
756 };
757 };
758 };
759
760 mt6315_7: pmic@7 {
761 compatible = "mediatek,mt6315-regulator";
762 reg = <0x7 SPMI_USID>;
763
764 regulators {
765 mt6315_7_vbuck1: vbuck1 {
766 regulator-compatible = "vbuck1";
767 regulator-name = "Vgpu";
768 regulator-min-microvolt = <300000>;
769 regulator-max-microvolt = <1193750>;
770 regulator-enable-ramp-delay = <256>;
771 regulator-allowed-modes = <0 1 2>;
772 };
773 };
774 };
775};
776
777&uart0 {
778 /* Exposed at 40 pin connector */
779 pinctrl-0 = <&uart0_pins>;
780 pinctrl-names = "default";
781 status = "okay";
782};
783
784&uart1 {
785 /* Exposed at 40 pin connector */
786 pinctrl-0 = <&uart1_pins>;
787 pinctrl-names = "default";
788 status = "okay";
789};
790
791&ssusb0 {
792 role-switch-default-mode = "host";
793 usb-role-switch;
794 vusb33-supply = <&mt6359_vusb_ldo_reg>;
795 status = "okay";
796
797 port {
798 mtu3_hs0_role_sw: endpoint {
799 remote-endpoint = <&typec_con_hs>;
800 };
801 };
802};
803
804&ssusb2 {
805 vusb33-supply = <&mt6359_vusb_ldo_reg>;
806 status = "okay";
807};
808
809&xhci0 {
810 vbus-supply = <&otg_vbus_regulator>;
811 status = "okay";
812};
813
814&xhci1 {
815 /* MT7921's USB Bluetooth has issues with USB2 LPM */
816 usb2-lpm-disable;
817 vusb33-supply = <&mt6359_vusb_ldo_reg>;
818 vbus-supply = <&vsys>;
819 status = "okay";
820};
821
822&xhci2 {
823 vbus-supply = <&vsys>;
824 status = "okay";
825};