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git01.mediatek.com / filogic / uboot / a3782b1197d19ea5f0ee4e9de53507cca525976a / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: 4e0587fd441a23c9826476094cff43c92a6e4c9a [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi1aed3dd2023-09-11 16:10:48 +0200[diff] [blame]5 * (C) Copyright 2019 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]7 *
Michal Simeka8c94362023-07-10 14:35:49 +0200[diff] [blame]8 * Michal Simek <michal.simek@amd.com>
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]9 */
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
16
17/ {
18 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
19 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
20 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem0;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]27 nvmem0 = &eeprom;
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]28 nvmem1 = &eeprom_ebm;
29 nvmem2 = &eeprom_fmc1;
30 nvmem3 = &eeprom_fmc2;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]31 rtc0 = &rtc;
32 serial0 = &uart0;
33 serial1 = &dcc;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]39 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>;
44 };
45
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]46 si5332_1: si5332-1 { /* u142 - GEM0 */
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <125000000>;
50 };
51
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]52 ina226-vccint {
53 compatible = "iio-hwmon";
54 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
55 };
56 ina226-vcc-soc {
57 compatible = "iio-hwmon";
58 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
59 };
60 ina226-vcc-pmc {
61 compatible = "iio-hwmon";
62 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
63 };
64 ina226-vcc-ram {
65 compatible = "iio-hwmon";
66 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
67 };
68 ina226-vcc-pslp {
69 compatible = "iio-hwmon";
70 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
71 };
72 ina226-vcc-psfp {
73 compatible = "iio-hwmon";
74 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
75 };
76 ina226-vccaux {
77 compatible = "iio-hwmon";
78 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
79 };
80 ina226-vccaux-pmc {
81 compatible = "iio-hwmon";
82 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
83 };
84 ina226-vcco-500 {
85 compatible = "iio-hwmon";
86 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
87 };
88 ina226-vcco-501 {
89 compatible = "iio-hwmon";
90 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
91 };
92 ina226-vcco-502 {
93 compatible = "iio-hwmon";
94 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
95 };
96 ina226-vcco-503 {
97 compatible = "iio-hwmon";
98 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
99 };
100 ina226-vcc-1v8 {
101 compatible = "iio-hwmon";
102 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
103 };
104 ina226-vcc-3v3 {
105 compatible = "iio-hwmon";
106 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
107 };
108 ina226-vcc-1v2-ddr4 {
109 compatible = "iio-hwmon";
110 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
111 };
112 ina226-vcc-1v1-lp4 {
113 compatible = "iio-hwmon";
114 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
115 };
116 ina226-vadj-fmc {
117 compatible = "iio-hwmon";
118 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
119 };
120 ina226-mgtyavcc {
121 compatible = "iio-hwmon";
122 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
123 };
124 ina226-mgtyavtt {
125 compatible = "iio-hwmon";
126 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
127 };
128 ina226-mgtyvccaux {
129 compatible = "iio-hwmon";
130 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
131 };
132};
133
134&uart0 { /* uart0 MIO38-39 */
135 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]136};
137
138&sdhci1 { /* sd1 MIO45-51 cd in place */
139 status = "okay";
140 no-1-8-v;
141 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]142 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]143};
144
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]145/* GEM SGMII */
146&psgtr {
147 status = "okay";
148 /* gem0 */
149 clocks = <&si5332_1>;
150 clock-names = "ref0";
151};
152
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]153&gem0 {
154 status = "okay";
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]155 phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]156 phy-handle = <&phy0>;
157 phy-mode = "sgmii";
Michal Simek8acb6b72022-09-06 12:39:11 +0200[diff] [blame]158 mdio: mdio {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 phy0: ethernet-phy@0 { /* u131 M88E1512 */
162 reg = <0>;
163 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]164 };
165};
166
167&gpio {
168 status = "okay";
169 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
170 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
171 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
172 "", "", "", "", "", /* 15 - 19 */
173 "", "", "", "", "", /* 20 - 24 */
174 "", "", "", "", "", /* 25 - 29 */
175 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
176 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
177 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
178 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
179 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
180 "", "", "", "", "", /* 55 - 59 */
181 "", "", "", "", "", /* 60 - 64 */
182 "", "", "", "", "", /* 65 - 69 */
183 "", "", "", "", "", /* 70 - 74 */
184 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]185 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]186 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
187 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
188 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
189 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]190 "", "", "", "", "", /* 100 - 104 */
191 "", "", "", "", "", /* 105 - 109 */
192 "", "", "", "", "", /* 110 - 114 */
193 "", "", "", "", "", /* 115 - 119 */
194 "", "", "", "", "", /* 120 - 124 */
195 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]196 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]197 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]198 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
199 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]200 "", "", "", "", "", /* 150 - 154 */
201 "", "", "", "", "", /* 155 - 159 */
202 "", "", "", "", "", /* 160 - 164 */
203 "", "", "", "", "", /* 165 - 169 */
Michal Simekfdf3fc62023-07-10 14:37:31 +0200[diff] [blame]204 "", "", "", ""; /* 170 - 173 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]205};
206
207&i2c0 { /* MIO 34-35 - can't stay here */
208 status = "okay";
209 clock-frequency = <400000>;
Michal Simeka43fdcd2022-08-23 15:00:25 +0200[diff] [blame]210
211 tca6416_u233: gpio@20 { /* u233 */
212 compatible = "ti,tca6416";
213 reg = <0x20>;
214 gpio-controller; /* interrupt not connected */
215 #gpio-cells = <2>;
216 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
217 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */
218 "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */
219 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
220 };
221
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]222 i2c-mux@74 { /* u33 */
223 compatible = "nxp,pca9548";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x74>;
227 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
228 i2c@0 { /* PMBUS */
229 #address-cells = <1>;
230 #size-cells = <0>;
231 reg = <0>;
232 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]233 /* u179 ir38164 0x19/0x49 vcco_500 */
234 /* u181 ir38164 0x1a/0x4a vcco_501 */
235 /* u183 ir38164 0x1b/0x4b vcco_502 */
236 /* u185 ir38164 0x1e/0x4e vadj_fmc */
237 /* u187 ir38164 0x1F/0x4f mgtyavcc */
238 /* u189 ir38164 0x20/0x50 mgtyavtt */
239 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
240 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]241
242 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
243 compatible = "infineon,irps5401";
244 reg = <0x47>; /* pmbus / i2c 0x17 */
245 };
246 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
247 compatible = "infineon,irps5401";
248 reg = <0x4c>; /* pmbus / i2c 0x1c */
249 };
250 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
251 compatible = "infineon,irps5401";
252 reg = <0x4d>; /* pmbus / i2c 0x1d */
253 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]254 };
255 i2c@1 { /* PMBUS1_INA226 */
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <1>;
259 /* FIXME check alerts coming to SC */
260 vccint: ina226@40 { /* u65 */
261 compatible = "ti,ina226";
262 #io-channel-cells = <1>;
263 label = "ina226-vccint";
264 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]265 shunt-resistor = <500>; /* R440 */
266 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]267 };
268 vcc_soc: ina226@41 { /* u161 */
269 compatible = "ti,ina226";
270 #io-channel-cells = <1>;
271 label = "ina226-vcc-soc";
272 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]273 shunt-resistor = <500>; /* R1702 */
274 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]275 };
276 vcc_pmc: ina226@42 { /* u163 */
277 compatible = "ti,ina226";
278 #io-channel-cells = <1>;
279 label = "ina226-vcc-pmc";
280 reg = <0x42>;
281 shunt-resistor = <5000>; /* R1214 */
282 /* 0.78V @ 500mA */
283 };
284 vcc_ram: ina226@43 { /* u162 */
285 compatible = "ti,ina226";
286 #io-channel-cells = <1>;
287 label = "ina226-vcc-ram";
288 reg = <0x43>;
289 shunt-resistor = <5000>; /* r1221 */
290 /* 0.78V @ 4A */
291 };
292 vcc_pslp: ina226@44 { /* u165 */
293 compatible = "ti,ina226";
294 #io-channel-cells = <1>;
295 label = "ina226-vcc-pslp";
296 reg = <0x44>;
297 shunt-resistor = <5000>; /* R1216 */
298 /* 0.78V @ 1A */
299 };
300 vcc_psfp: ina226@45 { /* u164 */
301 compatible = "ti,ina226";
302 #io-channel-cells = <1>;
303 label = "ina226-vcc-psfp";
304 reg = <0x45>;
305 shunt-resistor = <5000>; /* R1219 */
306 /* 0.78V @ 2A */
307 };
308 };
309 i2c@2 { /* PCIE_CLK */
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <2>;
Michal Simek11fae8c2023-11-08 08:36:40 +0100[diff] [blame]313 /* u39 8T49N240 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]314 };
315 i2c@3 { /* PMBUS2_INA226 */
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <3>;
319 /* FIXME check alerts coming to SC */
320 vccaux: ina226@40 { /* u166 */
321 compatible = "ti,ina226";
322 #io-channel-cells = <1>;
323 label = "ina226-vccaux";
324 reg = <0x40>;
325 shunt-resistor = <5000>; /* R382 */
326 /* 1.5V @ 3A */
327 };
328 vccaux_pmc: ina226@41 { /* u168 */
329 compatible = "ti,ina226";
330 #io-channel-cells = <1>;
331 label = "ina226-vccaux-pmc";
332 reg = <0x41>;
333 shunt-resistor = <5000>; /* R1246 */
334 /* 1.5V @ 500mA */
335 };
336 vcco_500: ina226@42 { /* u178 */
337 compatible = "ti,ina226";
338 #io-channel-cells = <1>;
339 label = "ina226-vcco-500";
340 reg = <0x42>;
341 shunt-resistor = <2000>; /* R1300 */
342 /* 3.3V @ 5A */
343 };
344 vcco_501: ina226@43 { /* u180 */
345 compatible = "ti,ina226";
346 #io-channel-cells = <1>;
347 label = "ina226-vcco-501";
348 reg = <0x43>;
349 shunt-resistor = <2000>; /* R1313 */
350 /* 3.3V @ 5A */
351 };
352 vcco_502: ina226@44 { /* u182 */
353 compatible = "ti,ina226";
354 #io-channel-cells = <1>;
355 label = "ina226-vcco-502";
356 reg = <0x44>;
357 shunt-resistor = <2000>; /* R1330 */
358 /* 3.3V @ 5A */
359 };
360 vcco_503: ina226@45 { /* u172 */
361 compatible = "ti,ina226";
362 #io-channel-cells = <1>;
363 label = "ina226-vcco-503";
364 reg = <0x45>;
365 shunt-resistor = <5000>; /* R1229 */
366 /* 1.8V @ 2A */
367 };
368 vcc_1v8: ina226@46 { /* u173 */
369 compatible = "ti,ina226";
370 #io-channel-cells = <1>;
371 label = "ina226-vcc-1v8";
372 reg = <0x46>;
373 shunt-resistor = <5000>; /* R400 */
374 /* 1.8V @ 6A */
375 };
376 vcc_3v3: ina226@47 { /* u174 */
377 compatible = "ti,ina226";
378 #io-channel-cells = <1>;
379 label = "ina226-vcc-3v3";
380 reg = <0x47>;
381 shunt-resistor = <5000>; /* R1232 */
382 /* 3.3V @ 500mA */
383 };
384 vcc_1v2_ddr4: ina226@48 { /* u176 */
385 compatible = "ti,ina226";
386 #io-channel-cells = <1>;
387 label = "ina226-vcc-1v2-ddr4";
388 reg = <0x48>;
389 shunt-resistor = <5000>; /* R1275 */
390 /* 1.2V @ 4A */
391 };
392 vcc1v1_lp4: ina226@49 { /* u177 */
393 compatible = "ti,ina226";
394 #io-channel-cells = <1>;
395 label = "ina226-vcc1v1-lp4";
396 reg = <0x49>;
397 shunt-resistor = <5000>; /* R1286 */
398 /* 1.1V @ 4A */
399 };
400 vadj_fmc: ina226@4a { /* u184 */
401 compatible = "ti,ina226";
402 #io-channel-cells = <1>;
403 label = "ina226-vadj-fmc";
404 reg = <0x4a>;
405 shunt-resistor = <2000>; /* R1350 */
406 /* 1.5V @ 10A */
407 };
408 mgtyavcc: ina226@4b { /* u186 */
409 compatible = "ti,ina226";
410 #io-channel-cells = <1>;
411 label = "ina226-mgtyavcc";
412 reg = <0x4b>;
413 shunt-resistor = <2000>; /* R1367 */
414 /* 0.88V @ 6A */
415 };
416 mgtyavtt: ina226@4c { /* u188 */
417 compatible = "ti,ina226";
418 #io-channel-cells = <1>;
419 label = "ina226-mgtyavtt";
420 reg = <0x4c>;
421 shunt-resistor = <2000>; /* R1384 */
422 /* 1.2V @ 10A */
423 };
424 mgtyvccaux: ina226@4d { /* u234 */
425 compatible = "ti,ina226";
426 #io-channel-cells = <1>;
427 label = "ina226-mgtyvccaux";
428 reg = <0x4d>;
429 shunt-resistor = <5000>; /* r1679 */
430 /* 1.5V @ 500mA */
431 };
432 };
433 i2c@4 { /* LP_I2C_SM */
434 #address-cells = <1>;
435 #size-cells = <0>;
436 reg = <4>;
437 /* FIXME wires ready but chip is missing */
438 };
439 i2c@5 { /* zSFP_SI570 */
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <5>;
443 si570_zsfp: clock-generator@5d { /* u192 */
444 #clock-cells = <0>;
445 compatible = "silabs,si570";
446 reg = <0x5d>;
447 temperature-stability = <50>;
448 factory-fout = <156250000>;
449 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]450 clock-output-names = "si570_zsfp_clk";
Saeed Nowshadi196e52f2024-01-25 09:07:58 +0100[diff] [blame]451 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]452 };
453 };
454 i2c@6 { /* USER_SI570_1 */
455 #address-cells = <1>;
456 #size-cells = <0>;
457 reg = <6>;
Saeed Nowshadi1aed3dd2023-09-11 16:10:48 +0200[diff] [blame]458 si570_user1: clock-generator@5f { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]459 #clock-cells = <0>;
460 compatible = "silabs,si570";
Saeed Nowshadi1aed3dd2023-09-11 16:10:48 +0200[diff] [blame]461 reg = <0x5f>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]462 temperature-stability = <50>;
463 factory-fout = <100000000>;
464 clock-frequency = <100000000>;
465 clock-output-names = "si570_user1";
Saeed Nowshadi196e52f2024-01-25 09:07:58 +0100[diff] [blame]466 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]467 };
468
469 };
470 i2c@7 { /* USER_SI570_2 */
471 #address-cells = <1>;
472 #size-cells = <0>;
473 reg = <7>;
474 /* FIXME wires ready but chip is missing */
475 };
476 };
477};
478
479&i2c1 { /* i2c1 MIO 36-37 */
480 status = "okay";
481 clock-frequency = <400000>;
482
483 i2c-mux@74 { /* u35 */
484 compatible = "nxp,pca9548";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]488 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]489 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
490 dc_i2c: i2c@0 { /* DC_I2C */
491 #address-cells = <1>;
492 #size-cells = <0>;
493 reg = <0>;
494 /* Use for storing information about SC board */
495 eeprom: eeprom@54 { /* u34 - m24128 16kB */
496 compatible = "st,24c128", "atmel,24c128";
497 reg = <0x54>; /* 0x5c too */
498 };
499 si570_ref_clk: clock-generator@5d { /* u32 */
500 #clock-cells = <0>;
501 compatible = "silabs,si570";
502 reg = <0x5d>;
503 temperature-stability = <50>;
504 factory-fout = <33333333>;
505 clock-frequency = <33333333>;
506 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]507 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]508 };
509 /* and connector J212D */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]510 eeprom_ebm: eeprom@52 { /* x-ebm module */
511 compatible = "st,24c128", "atmel,24c128";
512 reg = <0x52>;
513 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]514 };
515 fmc1: i2c@1 { /* FMCP1_IIC */
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <1>;
519 /* FIXME connection to Samtec J51C */
520 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]521 eeprom_fmc1: eeprom@50 {
522 compatible = "st,24c128", "atmel,24c128";
523 reg = <0x50>;
524 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]525 };
526 fmc2: i2c@2 { /* FMCP2_IIC */
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <2>;
530 /* FIXME connection to Samtec J53C */
531 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]532 eeprom_fmc2: eeprom@50 {
533 compatible = "st,24c128", "atmel,24c128";
534 reg = <0x50>;
535 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]536 };
537 i2c@3 { /* DDR4_DIMM1 */
538 #address-cells = <1>;
539 #size-cells = <0>;
540 reg = <3>;
541 si570_ddr_dimm1: clock-generator@60 { /* u2 */
542 #clock-cells = <0>;
543 compatible = "silabs,si570";
544 reg = <0x60>;
545 temperature-stability = <50>;
546 factory-fout = <200000000>;
547 clock-frequency = <200000000>;
548 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]549 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]550 };
551 };
552 i2c@4 { /* LPDDR4_SI570_CLK2 */
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]556 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]557 #clock-cells = <0>;
558 compatible = "silabs,si570";
559 reg = <0x60>;
560 temperature-stability = <50>;
561 factory-fout = <200000000>;
562 clock-frequency = <200000000>;
563 clock-output-names = "si570_lpddr4_clk2";
Saeed Nowshadi196e52f2024-01-25 09:07:58 +0100[diff] [blame]564 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]565 };
566 };
567 i2c@5 { /* LPDDR4_SI570_CLK1 */
568 #address-cells = <1>;
569 #size-cells = <0>;
570 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]571 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]572 #clock-cells = <0>;
573 compatible = "silabs,si570";
574 reg = <0x60>;
575 temperature-stability = <50>;
576 factory-fout = <200000000>;
577 clock-frequency = <200000000>;
578 clock-output-names = "si570_lpddr4_clk1";
Saeed Nowshadi196e52f2024-01-25 09:07:58 +0100[diff] [blame]579 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]580 };
581 };
582 i2c@6 { /* HSDP_SI570 */
583 #address-cells = <1>;
584 #size-cells = <0>;
585 reg = <6>;
586 si570_hsdp: clock-generator@5d { /* u5 */
587 #clock-cells = <0>;
588 compatible = "silabs,si570";
589 reg = <0x5d>;
590 temperature-stability = <50>;
591 factory-fout = <156250000>;
592 clock-frequency = <156250000>;
593 clock-output-names = "si570_hsdp_clk";
Saeed Nowshadi196e52f2024-01-25 09:07:58 +0100[diff] [blame]594 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]595 };
596 };
597 i2c@7 { /* 8A34001 - U219B and J310 connector */
598 #address-cells = <1>;
599 #size-cells = <0>;
600 reg = <7>;
601 };
602 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]603 i2c-mux@75 { /* u214 */
604 compatible = "nxp,pca9548";
605 #address-cells = <1>;
606 #size-cells = <0>;
607 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]608 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]609 i2c@0 { /* SFP0_IIC */
610 #address-cells = <1>;
611 #size-cells = <0>;
612 reg = <0>;
613 /* SFP0 */
614 };
615 i2c@1 { /* SFP1_IIC */
616 #address-cells = <1>;
617 #size-cells = <0>;
618 reg = <1>;
619 /* SFP1 */
620 };
621 i2c@2 { /* QSFP1_I2C */
622 #address-cells = <1>;
623 #size-cells = <0>;
624 reg = <2>;
625 /* QSFP1 */
626 };
627 /* 3 - 7 unused */
628 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]629};
630
631&xilinx_ams {
632 status = "okay";
633};
634
635&ams_ps {
636 status = "okay";
637};
638
639&ams_pl {
640 status = "okay";
641};